JPS62128216A - Tone squelch circuit - Google Patents

Abstract

PURPOSE:To attain a digitized constitution circuit by comparing a reference count value with a counted value of a tone signal of a PLL circuit during a locking period, for a prescribed period, and applying on/off control to a mute circuit. CONSTITUTION:An output pulse (g) of an AND gate 37 is fed to a counter 43 and counted for a period of '1' of a timing signal (h) fed from a timing circuit 41. The count of the counter 43 during the period synchronizes with the leading edge of the timing signal (h), latched by a latch circuit 44, and the latched counted value and the reference count value stored in a register 42 are compared by a comparator 45. The comparator 45 outputs a signal '1' when the relation of latched count >= reference count exists and the muting of a mute circuit 9 is released. In changing the reference count, the probability of mute release in response to the S/N is changed and the squelch level is set taking the S/N of the tone signal into account and adjusted digitally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a tone squelch circuit suitable for use in a receiver of a wireless communication system such as a cellular one-way radio telephone.

[Background of the invention]

2. Description of the Related Art Conventionally, wireless receivers, such as cellular one-way wireless telephones, are known that use tone signals to control squelch. In a wireless communication system using such tone signals, the transmitter sends a message to the receiver of the other party to be called.
A predetermined specific tone signal is sent as a transmitting radio wave, and the other party's receiver turns on the audio circuit according to the specific tone signal to adjust the receiving state. The circuit for this purpose is a tone squelch circuit.

The tone squelch circuit detects a specific tone signal in the received radio waves and turns on the audio signal.
Then, the audio generated by the received radio waves is generated from the speaker, and if there is no specific tone signal in the received radio waves, the audio circuit is turned OFF to prevent the generation of noise from the speaker.

By the way, there are multiple types of tone signals, and for example, very close frequencies may be used between these different types, such as 5970f(z, 60001(Z, 6030Hz).In such cases, In the tone squelch circuit, a bandpass filter with a large Q must be used in order to clearly distinguish and detect these tone signals.However, bandpass filters have temperature characteristics and changes in characteristics over time. It is necessary to compensate for these, which increases the number of parts in the tone squelch circuit, complicates the circuit configuration, and increases the cost of the radio receiver.

On the other hand, for example, as in an AM stereo device, a PLL is used as a muting circuit for selectively muting a synchronous detection output signal, and the input signal to be synchronously detected is supplied to form a carrier wave for synchronous detection. (Phase Locked Loop) A technique is known in which a locked state of a circuit is detected and a muting switch is controlled depending on whether or not it is locked.
-52236).

To briefly explain such a muting circuit with reference to FIG. 6, an input signal from input terminal j is passed through limiter 2 to P1. ,, is supplied to the L circuit 3.

When the PLL circuit 3 is locked to the input signal, it outputs a signal whose phase is shifted by π/2 with respect to the input signal. The output signal of the PLI circuit 3 is phase shifted by Tc/2 in the phase shift circuit 5, and is supplied to the multiplier circuit 4 together with the output signal of the limiter 2.

When the PLL circuit 3 is locked to the input signal, the output signal of the phase shift circuit 5 is in phase with the input signal, and the multiplier circuit 4 outputs a DC voltage of a predetermined level or higher. However, when the PLL circuit 3 is not locked to the input signal, no DC voltage is obtained from the multiplication circuit 4, or a DC voltage at a level lower than the predetermined level is output.

The output of the multiplier circuit 4 is supplied to a comparator 22 via a low-pass filter 6. The comparator 22 compares the input voltage from the low-pass filter 6 with the reference voltage E at the predetermined level, and when the input voltage is higher than the reference voltage E, a high-level control voltage is output, for example, and the muting switch 9 In the opposite case, a low level control voltage is output and the muting switch 9 is turned off.

On the other hand, the output signal of the PLL circuit 3 is supplied as a carrier wave to the multiplication circuit 8, and the input signal from the input terminal 1 is
ll detection.

Therefore, if a human input signal is supplied from the input terminal 1 and the PLL circuit 3 is locked to this signal, the multiplication circuit 8 performs synchronous detection on this input signal to obtain an audio signal. Since the muting switch 9 is on at this time, this audio signal is output from the output terminal 10 via the muting switch 9. In contrast,
If there is no input signal at the input terminal 1, or if there is an input signal but the PLL circuit 3 is not locked to it, no audio signal will be obtained from the multiplier circuit 8, and noise will occur. Since the muting switch 9 is off at this time, unnecessary signals such as noise are blocked.

Here, PLL circuits generally lock to input signals with a very high Q, and yet lock to input signals of different frequencies. Therefore, by applying the principle of the muting circuit described above to the tone squelch circuit of a radio receiver, it becomes possible to reliably discriminate among the plurality of types of tone signals that are very close to each other as described above.

By the way, whether or not the PLL circuit 3 is locked is also influenced by the S/N of the tone signal. Therefore, the squelch level should be set in consideration of this S/N ratio, and for this purpose, an adjusting means for making the reference voltage of the comparator circuit 22 variable is provided. As a means of this adjustment, it is possible to use a so-called mechanical rotating polyurethane, but in recent years, with the development of microcomputers and digital technology, wireless communication devices have come to have built-in microcomputers. In this case, it is undesirable to use rotating polyurethane because of the external design of the wireless communication device.
It is desirable to use electronic polyum. This is the same for the squelch level 811 adjustment means. However, with the above-mentioned conventional technology, it is very difficult to meet such requirements.

Furthermore, since processing is performed in an analog manner, the circuit scale becomes large, which poses a major problem in the case of car telephones installed in automobiles, portable radio telephones, and the like.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a tone squelch circuit which eliminates such problems, allows the squelch level to be adjusted digitally, and allows the constituent circuits to be converted into digital circuits.

[Summary of the invention]

To achieve this objective, the present invention provides P
The feature is that the lock period of the LL circuit to the tone signal is counted, the obtained count value is compared with a reference count value, and the mute circuit is controlled to be turned on or off according to the comparison result.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a tone squelch circuit according to the present invention, in which 1 is an input terminal, 9 is a mute circuit, 10 is an output terminal, 29 is an FM detection circuit, and 30 is a B
PF (band pass filter), 31 is a rising edge detection circuit, 32 is a PLL circuit, 33 is an oscillation circuit, 34 is a timing circuit, 35 is an up/down counter, 36 is an R
-S flip-flop, 37-39 are AND gates, 4
0 is an inverter, 41 is a timing circuit, 42 is a register, 43 is a counter, 44 is a latch circuit, and 45 is a comparator.

In the figure, when receiving an audio signal, an FM-modulated signal obtained by frequency multiplexing the audio signal and the tone signal a is input to the input terminal 1, and is detected by the FM detection circuit 29. The output signal of the FM detection circuit 29 is supplied to the mute circuit 9 and the BPF 30, and the BPF 30 separates the tone signal a.

Tone signal a has frequencies of 5970Hz, 6000Hz,
There are three types of 6030 Hz, and the BPF 30 has a pass band that allows any one of these to pass. Here, it is assumed that the tone signal a of 6000 Hz is passed.

Therefore, the PLL circuit 32 passes through the BPF 30.
It will lock to tone signal a of 00 Hz,
In order to determine whether the PLL circuit 32 has locked onto this tone signal a, a timing circuit 34, an up/down counter 35 . A lock detection circuit A consisting of an R-37 lip flop 36, AND gates 38 and 39, and an inverter 40 is provided.

The operation of this lock detection circuit A will be explained below with reference to FIG. In this figure, signals corresponding to those in FIG. 1 are given the same reference numerals.

The timing circuit 34 receives the output signal of the PLL circuit 32 and the pulse f from the oscillator 33, and generates a window signal that becomes "1" (high level) in a phase range of ±20' around the rising edge of this output signal. generate. This window signal is
As a gate pulse, it is inverted by an AND gate 39 and an inverter 4o and supplied to an AND gate I.38.

Further, the tone signal a separated by the BPF 30 is supplied to a rising edge detection circuit 31, the rising edge of which is detected, and a rising pulse a' representing this is sent to the AND gate 3.
Delivered at 8.39.

Therefore, the AND gate 39 passes the rising pulse a' within the window signal SU's "1" period, and the AND gate 38 passes the rising pulse a' within the window signal SU's O" period. AND gate 39 The output pulse C of is counted up by the up/down counter 35, and the output pulse C of
The output pulse d is counted down by an up/down counter 35. When the count value reaches a predetermined value (here, 16), the up/down counter 35 generates a set pulse and outputs a set pulse to the R-S flip-flop 36.
is set, and when the count value reaches another predetermined value (here, 0), a reset pulse is generated and the R-S
Reset flip-flop 36.

In the lock detection circuit that operates as described above, when the PLL circuit 32 is completely locked to the tone signal a,
The rising edge of this tone signal a is almost in the "1" period of the window signal, and the up/down counter 35 counts up. When the up/down counter 35 reaches 16, the R'-S flip-flop 3
6 is set, and when a certain value is reached thereafter, that value is held and up-counting is stopped. Therefore, P.L.
When the L circuit 32 is completely locked to the tone signal a, the R-S flip-flop 36 is held in the set state, and its Q output, that is, the lock detection signal e of the PLL circuit 32 is held at '1''. Ru.

However, even if the PLL circuit 32 is locked to the tone signal a, the received electric field strength of the radio receiver decreases, and the BPF 3
If the S/N of the tone signal a output from 0 is low, the rising edge of the tone signal a may be outside the "1" period of the window signal.

That is, in such a low S/N state, whether or not the rising edge of the tone signal a is within the "1" period of the window signal S is a matter of probability. Simply, the PLL circuit 32 is 1-
In order to determine whether or not it is locked to the window signal a, it is sufficient to determine whether the rising edge is in the "1" period of the window signal A. The R-S flip-flop 36 can be set and reset by the output j pulses C1d of −39 and 38 (thereby, the lock detection signal e becomes “1” when locked, and # when not locked). 0"). In this way, as described above, in a low S/N state, even though the PLL circuit 32 is locked, the R-S flip-flop 36 is reset and the lock detection signal is not output. e becomes 0'',
The operation becomes ambiguous.

The up/down counter 35 is provided to reduce such ambiguity, and even if the rising edge of the tone signal a deviates from the "1" period of the window signal,
If there is a high probability that this rising edge is within the 1" period of the window signal, it is assumed that the PLL circuit 32 is locked to the tone signal a, and the lock detection signal e is set to #1#. A circuit that acts like this is generally called a random walk filter.

When the S/N is low, as shown in FIG. 3, the lock signal e is stochastically in the "1#" state and the "50" state. This lock detection signal e is applied to the AND gate 37 as a gate pulse.
is supplied to gate the 1 kHz pulse f from the oscillation circuit 33.

The output pulse g of the AND gate 37 is supplied to the counter 43, and is counted for a period of '1' of 100m5ec according to the timing signal supplied from the timing circuit 41.The count value of the counter 43 during this period is The latched count value is latched by the latch circuit 44 in synchronization with the rising edge of the signal, and the latched count value and the reference count value stored in the register 42 are compared by the comparator 45.

When the latched count value≧the reference count value, the comparator 45 outputs a signal of 91″, whereby the mute circuit 9 is unmuted.

By the way, the count value latched by the latch circuit 44 differs stochastically depending on the S/N of the received signal. S/
The average value and variance of this count value for N are shown in Figure 4, and the probability density function is
If the variance is σ, then the count value follows a normal distribution, and the probability that the mute circuit 9 is unmuted using the reference count value as a parameter is expressed as follows.

PP(y) = , /' p(x) dx where,
y is a value determined by the S/N ratio and the reference count value. S/N
The probability of unmuting of the mute circuit 9 for each reference count value of 60.75°90 is shown as follows:
It will look like Figure 5.

In this way, by changing the 1 count value stored in the register 42, the probability of unmuting depending on the S/N also changes. Therefore, by adjusting this reference count value, it is possible to set the squelch level in consideration of the S/N ratio of the tone signal, and moreover, this squelch level can be adjusted digitally.

It goes without saying that in this embodiment, the timing circuit 41, register 42, counter 43, latch circuit 44, and comparator 45 can be realized by microcomputer software. In addition, if the processing speed of the microcomputer is fast, the PLL circuit 32 and lock detection circuit A can also be realized by software, and the entire tone squelch circuit can be made into a digital circuit, making it suitable for LSI implementation and reducing the number of parts. It is possible to achieve a significant reduction in circuit size and a significant reduction in circuit size.

〔Effect of the invention〕

As explained above, according to the present invention, since the squelch level can be adjusted digitally, there is no need for a rotary volume, which greatly alleviates constraints on the design of a wireless receiver. It becomes possible to convert the circuit into a digital circuit, making it suitable for LSI, and it is possible to significantly reduce the number of parts and scale.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the tone squelch circuit according to the present invention, FIGS. 2 and 3 are timing charts for explaining the operation of this embodiment, and FIGS.
The figure is a graph showing the performance of this embodiment, and FIG. 6 is a block diagram showing an example of a conventional muting circuit. 1...Input terminal, 9...Mute circuit, 10...Audio signal output terminal, 30...
... Band pass filter, 31 ... Rising edge detection circuit, 32 ... PLL circuit, 33.
...Oscillation circuit, 34...Timing circuit, 35...Up/down counter, 36...
...R-S flip-flop, 41...timing circuit, 42...register, 43...
...Counter, 44...Latch circuit, 45...
... Comparator, A ... Lock detection circuit. Beauty. 2;",;+-・-Iu-mu-Figure 2Figure 3

Claims (1)

[Claims] A phase synchronizing means synchronizes with a tone signal supplied together with a predetermined signal, a lock detecting means detecting whether or not the phase synchronizing means is locked to the tone signal, and a detection output of the lock detecting means is determined to be constant. a counting means for counting the period during which the phase synchronization means is locked to the tone signal; a comparison means for comparing the count value of the counting means with a reference value; and an output of the comparison means to which the predetermined signal is supplied. A tone squelch circuit comprising: opening/closing means that is controlled to turn on and off depending on the timing of the tone squelch circuit.