JPH0430830Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to an unlock detection circuit for a PLL circuit used to obtain a local oscillation frequency signal or a carrier wave signal in radio equipment such as a transceiver.

(b) Conventional technology In transmitting equipment, etc., in which the transmitting carrier is created by a PLL circuit, if the PLL transmits radio waves in an unlocked state, it will transmit a frequency other than the specified frequency, which poses a problem. Also, when switching channels on receivers such as electronically tuned radios,
If the PLL is in an unlocked state, no station detection signal will be output even though a broadcasting station is present, and there is a risk that the station may be missed, especially when using automatic search. Therefore, a circuit is required to detect whether or not the PLL is in an unlocked state. Conventionally, the frequency divided output is extracted from any output stage of the reference frequency divider circuit, and the phase is compared using the width of the output pulse as a reference. An unlock detection circuit is used to discriminate the phase difference signals from the circuit.

The above-mentioned unlock detection circuit was developed in Japanese Patent Publication No. 58-11138.
The details are described in the publication.

(c) Problems to be solved by the invention However, the conventional unlock detection circuit
Like a CB transceiver, the frequency bandwidth used is narrow, the PLL loop gain is almost constant,
If it is easy to distinguish between the phase difference that occurs even in the lock state due to slight fluctuations in the VCO frequency due to mechanical vibrations or leaks from the charge pump or low-pass filter, and the phase difference caused by channel switching or frequency fluctuations that exceed the allowable limit, Although effective,
When the loop gain of the PLL varies greatly from band to band, such as in a multi-band radio, the allowable range of the lock state differs for each band, making it difficult to use conventional unlock detection circuits with a fixed discrimination width. It was hot.

(d) Means for solving the problem The present invention has been made in view of the above points, and is a switching gate means to which a plurality of divided outputs having different periods extracted from a reference frequency dividing circuit are applied. and,
A discrimination circuit that uses the divided output output from the switching gate means as a discrimination pulse and discriminates the pulse width of the phase difference signal from the phase comparison circuit, and a data input that holds data applied from the outside and controls the switching gate circuit. By inputting data from the outside, the allowable range of the lock state can be set according to the state of the PLL.

(E) Effect According to the above-described means, when predetermined data based on the state of the PLL loop gain, etc. is applied to the input means and held, the switching gate means changes the reference portion according to the data. One of the plurality of divided outputs having different periods applied from the frequency circuit is selectively applied to the discrimination circuit. Thereby, the discrimination circuit discriminates the pulse width of the phase difference signal based on the pulse period of the applied frequency-divided output. Therefore, it becomes possible to arbitrarily select the discrimination width based on the applied data.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. The variable frequency divider circuit 1 is a frequency divider circuit that divides the oscillation frequency of the voltage controlled oscillator (VCO) 2, with a frequency division ratio determined according to preset data. The oscillation frequency is determined. The reference frequency divider circuit 3 is a frequency divider circuit that divides the reference frequency ref of the crystal oscillation circuit 4, and is, for example, a binary frequency divider circuit. The frequency division output P ₀ of the variable frequency division circuit 1 and the frequency division output of the reference frequency division circuit 3, that is, the reference comparison pulse R ₀ are applied to the phase comparison circuit 5, and the frequency division output P ₀ and the reference comparison pulse R ₀ are applied to the phase comparison circuit 5. The signal PD from the phase comparator circuit 5 according to the phase difference of is passed through a low pass filter (LPF) 6.
A phase difference signal PE that controls the oscillation frequency of the VCO 2 and indicates the phase difference is applied to the discrimination circuit 7. The discrimination circuit 7 includes D-FF8, R-SFF9, and counter 1.
The phase difference signal PE output from the phase comparison circuit 5 is applied to the input D of the D-FF 8, and the output of the switching gate circuit 13 is applied to the clock input CL. The output Q of the D-FF8 is connected to the set input S of the R-SFF9, and the output Q of the R-SFF9 is outputted as an unlock detection signal UNLOCK. Also,
The counter 10 resets the R-SFF 9 when it counts a predetermined number of frequency-divided outputs _R0 from the reference frequency divider circuit 3 after the last unlock is detected.

The data input means 14 consists of a 4-bit shift register 15 and a 4-bit latch circuit 16 for latching the data taken into the shift register 15, and these are integrated on a single-chip semiconductor substrate together with the aforementioned PLL circuit. The data input D of the shift register 15 is connected to the external terminal 17,
Clock input CL is connected to external terminal 18, and latch clock input φ of latch circuit 16 is connected to external terminal 19. That is, the external terminal 17,
18 and 19 are connected to a control device such as a microcomputer, and external terminals 17 and 18 are connected to 4
Bit serial data and a synchronization pulse that synchronizes with it are applied, and after the serial data transfer is completed,
A latch clock is applied to external terminal 19.

The switching gate circuit 13 is applied with the 4-bit outputs D ₁ , D ₂ , D ₃ and D ₄ from the latch circuit 14, and also receives the divided outputs φ ₁ , φ 2 , φ ₂ , which have different periods from the reference frequency divider circuit 3, respectively. φ ₃ and φ ₄ are applied. That is, the switching gate circuit 13 outputs the divided outputs φ ₁ , φ ₂ , φ ₃ and φ ₄ according to the data applied from the latch circuit 16.
One frequency-divided output is sent to the discrimination circuit 7. Therefore, the discrimination width of the discrimination circuit 7 can be arbitrarily selected.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. Frequency division outputs φ ₁ , φ ₂ , φ ₃ , and φ ₄ applied from the reference frequency divider circuit 3 to the switching gate circuit 13
Assuming that the pulses are sequentially binary frequency- _divided pulses as _shown in _{FIG .} Synchronized with all falls of ₄ . The phase comparison circuit 5 has a reference comparison pulse.
Rise of R ₀ and divided output of variable frequency divider circuit 1 P ₀
A phase difference device generates a pulse equal to the difference between the rising edge of
Output as PE. Therefore, the discrimination circuit 7 outputs D-FF8 before and after the rise of the reference comparison pulse _R0 .
The phase difference signal PE is captured at the rising edge of the pulse applied to the clock input CL, and that period becomes the discrimination width. Therefore, the divided outputs φ ₁ , φ ₂ , selected by the selection gate circuit 13
The discrimination widths in each of φ ₃ and φ ₄ are t ₁ , t ₂ , t ₃ ,
and the period indicated by t ₄ .

On the other hand, after applying four synchronization pulses and four bits of serial data to the shift register 15, data is taken into the shift register 15 by applying a latch clock, but the data is transferred to the variable frequency divider circuit 1. According to conditions such as the loop gain in the frequency division ratio set, only one of the four bits becomes "1". For example, when D ₂ of the data held in the latch circuit 16 is “1”, the selection gate circuit 13 outputs the frequency-divided output φ ₂ to the discrimination circuit 7 . The discrimination width in this case is the period _t2 , and for example, when the phase difference signal PE is the pulse shown in FIG. 2, it is detected that the unlocked state is present. On the other hand, even if the pulse width of the phase difference signal PE is the same, if the divided output φ ₃ selected when the data D ₃ is “1” is applied to the discrimination circuit 7, it is determined that the lock state is present.
Unlock detection signal UNLOCK is not output.

In this way, by selecting data according to conditions such as loop gain and transmitting it serially,
It is possible to select a discrimination width that matches the conditions.

(g) Effects of the invention As described above, according to the invention, optimal unlock detection is performed according to the PLL state, an unlock detection circuit that is easy to use in multi-band radios, etc. is obtained, and the versatility of the PLL circuit is improved. It has the advantage of improving Further, it has the advantage that connection with a control device such as a microcomputer is simple.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG. 1... variable frequency divider circuit, 2... voltage controlled oscillation circuit, 3... reference frequency divider circuit, 4... crystal oscillation circuit,
5... Phase comparator circuit, 6... Low pass filter,
7...Discrimination circuit, 13...Switching gate circuit, 14
...Data input means.

Claims (1)

[Scope of utility model registration request] A variable frequency divider circuit that divides the frequency output from the voltage controlled oscillator circuit, a reference frequency divider circuit that divides the reference frequency, and a divided output from the variable frequency divider circuit and a frequency divider from the reference frequency divider circuit. A PLL unlock detection circuit includes a phase comparison circuit for detecting a phase difference between outputs, and a switching gate circuit to which a plurality of divided outputs having different periods extracted from the reference frequency dividing circuit are applied; A discrimination circuit that uses the divided output output from the switching gate circuit as a discrimination pulse and discriminates the pulse width of the phase difference signal from the phase comparison circuit, and inputs and holds data related to the output frequency of the PLL applied from the outside. A PLL unlock detection circuit comprising: data input means for controlling the switching gate circuit, and varying the discrimination width of the discrimination circuit according to the frequency of the PLL.