FI72626B - ANORDING FOR COMPENSATION OF FREQUENCY VARIATION IN FM SYSTEM. - Google Patents

Description

1 72626

Switching to compensate for frequency variations in FM systems

The invention relates to a circuit for compensating for frequency variations in FM systems, in particular for data transmission with FSK modems in single-sideband operation using a phase control loop.

In data transmission, which often operates with FSK (Frequency-Shift-Keying) signals, there is uncertainty in the oscillator frequency in the demodulator due to individual elements and side deflection tolerances caused by aging and temperature fluctuations. The potential aid obtained by using highly frequency stable elements is very expensive. Similarly, additive frequency transfer is poor, especially in high frequency oscillators in mixers of radio transceivers. This is problematic in data transfer in the single page banding method. The missing carrier must be produced again at the receiver. In this case, there may be a difference of 100 Hz between the transmitted and received frequencies. A demodulator that cannot compensate for this deviation will cause errors under these conditions.

Limitations have been placed in such a system for adjusting the stable mode and compensating for slow frequency slip errors. The code must be aligned, or at least a certain part of it must be aligned.

This does not only apply to a balanced data code where there is a constant ratio of logic numbers 1 and 0 in the data stream over a specified time, but also to all FM systems that have a constant center frequency during τ. This integration time is an important parameter in this system.

2 72626 Such a system is explained by means of a PLL (Phase Locked Loop) for equalizing the FSK signal shown in Figure 1 below:

The phase control loop consists of a phase detector 1 to which an FSK signal and a voltage controlled oscillator 3 (VCO) output signal are applied, and a loop filter 2, a data filter 4 and then a comparator 5 for producing binary signals (DATA) to which a signal is input from a second input. Oscillator 3 is adjusted to the center frequency of the input signal. A DC voltage is applied to the output D of the loop for a given input frequency. At this DC voltage, when the input frequency is similar to the center frequency of the oscillator, the output as a reference signal will be inversely proportional to the loop gain K TT, i.e. ~ -. For a given

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with the frequency difference between the input signal and the center frequency of the oscillator, the output can be made particularly narrow as the loop gain increases.

The object of the invention is to provide a connection by means of which frequency fluctuations in FM systems can be compensated in a simple manner.

This object is solved by a connection of the type described at first according to the invention with a control loop consisting of a low-gain, fast detector branch consisting of a phase detector, a loop filter and a voltage-controlled oscillator. consists of a differential amplifier having a detector branch output signal on the one hand and a reference voltage on the other hand connected to a differential amplifier 3 72626 and an interpretation and holding circuit having a second input connected to the output of the low output filter and a second input input to the second input

Preferred embodiments and further development of the invention are set out in the subclaims.

In the following, the invention will be explained in more detail by means of exemplary embodiments shown in the drawing, in which Figures 2 to 4 show three different embodiments in block diagram form.

Figure 2 shows a first embodiment of the connection. The control loop is divided into two branches, namely a low gain, fast branch for rectifying the FM signal and a high gain, slow branch for frequency error compensation and slow side deviation in some part of the system. The detector branch includes a phase detector 1, a loop filter 2 formed as a low-pass filter and a voltage-controlled oscillator (VCO) 3, the signal and the switching input signal (FSK signal) of which are fed to the phase detector 1. On the output side there is a having two inputs and having an output connected to an oscillator 3. An output D of the phase control loop PLL is derived from the output connected to the second input of the low pass filter 2 amplifier 7, which is connected on the one hand to the second input of the comparator 5 and on the other The second input of the comparator 5 and the differential amplifier 8 is connected to a reference voltage source 6 producing the reference signal VREF. Binary data (DATA) can be taken from the output of the comparator 5. The differential amplifier 8 forms a compensating branch together with a subsequent interpretation and holding circuit 10, the second input of which is supplied with a holding signal and the output of which is connected to the second input of the summing amplifier 7 in the detector circuit. The interpretation and holding circuit is used to detect the reference voltage with respect to the controlled oscillator when the control loop has compensated for the frequency error or when the control loop falls out of the holding position.

The interpretation and hold circuit can be replaced with an A / D-D / A (analog / digital-to-digital / analog) transformer with digital memory to eliminate side deviation against time. The accuracy of the compensation is determined by the amplifier and the control time is determined by the low-pass filter in the compensation branch. The stability criteria must be taken into account in the application of the control loop. This is not a problem when a slow-functioning compensation network can be assumed. The integration filter 9 must then have a longer integration time than the stable center frequency integration time of the input signal.

There are two possibilities for exploiting the connection. On the other hand, a continuously balanced code with an uninterrupted data stream with a stable center frequency can be used. In this case, the interpretation and hold circuit does not work. Another possibility is to use a certain frequency of the input signal for equalization. This can be the start character at the beginning of the interpretation field. The time constant of the integration in the low-pass filter of the compensation loop can then be made much faster after the frequency is in a stable state.

This capability can be used in both continuous and non-continuous systems, i. both in a medium-frequency stable uninterrupted data stream and also when the length of the transmitted message is limited when the code is not aligned.

5,72626

When the control loop is no longer locked, a lock is required for the input signal. This depends on the loop gain and loop filters. In the first-order control loop, i.e. without loop filters, the bandwidth of the lock is equal to the loop gain. In a higher order control loop, loop filters play a major role. The interlocking bandwidth can be extremely narrow and the control loop is not interlocked unless the input frequency is in a narrow band near the oscillator center frequency. When the control loop is locked, the holding range is equal to the loop gain.

To avoid this locking problem, the loop filters can be short-circuited when the loop is not locked. The locking area can then be made extremely wide. As soon as the loop is locked, the short circuits are slowly removed and the connection operates as described above in connection with the embodiment according to Fig. 2. An embodiment with short-circuits in the loop filters is shown in Fig. 3, in which a short-circuit transistor T1, T2 (FET transistors) is in each case connected in parallel to the low-pass filter 1 in the detector branch and the low-pass filter 9 in the compensation branch to keep the control loop slow. The rest of the connection structure corresponds to the connection according to Figure 2.

Figure 4 shows another embodiment of a connection according to the invention. This is a variation using a first-order external Phase Locked Loop (PLL) with a wide retention area. In addition, the PLL1 arranged on the input side next to the already existing control loop PLL2 consists of a phase detector 12 and a voltage-controlled oscillator 13. Through a low-pass filter 14 at the output D1 of the PLL1, this is whose central contact is connected to the second input of the summing amplifier 7 in the detector branch of the PLL2 of the 6,72626 loop. The output signal of the loop PLL1 is filtered in the low-pass filter 14 and results in the locking of the second loop PLL2. After locking, the extra loop PLL1 is cut off and the high-gain, slow compensation branch is connected to another loop PLL2, which now operates as already described above. The other structure of the connection then corresponds to the structure of the connection according to Fig. 2.

Claims (4)

7,72626 1. Coupling to compensate for frequency fluctuations in FM systems, in particular for data transmission with FSK modems in single-side band operation using a phase control loop with a phase detector, a filter and a voltage-controlled oscillator, characterized in that the control loop consists of a low-gain 2) and a voltage-controlled oscillator (3), the output signal of which is passed through a filter (4) from its second input to a comparator (5) connected to a reference voltage source (6), and a high-gain, slow compensation branch consisting of a differential amplifier (8) output signal and, on the other hand, a reference voltage, a subsequent low-pass filter (9) and an interpretation and holding circuit (10), one input of which is connected to the output of the low-pass filter and the second input of which is supplied with a holding signal and The output is directed to the input of the summing amplifier (7) in the detector branch. Circuit according to Claim 1, characterized in that short-circuit transistors (T1, T2) are connected in parallel with the loop filter (2) in the detector branch and the low-pass filter (9) in the compensation branch. A circuit according to claim 1, characterized in that a second phase control loop (PLL1) is connected in front of the control loop (PLL2), the input of which is connected in parallel with the input of the first control loop and the output of which is connected to a changeover switch (S3) with the output of the interpretation and holding circuit (10) alternatively to the second input of the sum amplifier (7) in the detector branch of the first control loop. 72626 Switching according to one of Claims 1 to 3, characterized in that the interpretation and holding circuit (10) is replaced by an analog-to-digital-to-analogue converter with a digital memory.