JPS5923644A - Stereophonic signal reproducing circuit - Google Patents

Stereophonic signal reproducing circuit

Info

Publication number
JPS5923644A
JPS5923644A JP13348282A JP13348282A JPS5923644A JP S5923644 A JPS5923644 A JP S5923644A JP 13348282 A JP13348282 A JP 13348282A JP 13348282 A JP13348282 A JP 13348282A JP S5923644 A JPS5923644 A JP S5923644A
Authority
JP
Japan
Prior art keywords
circuit
sound field
signal
detector
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13348282A
Other languages
Japanese (ja)
Inventor
Shuichi Ninomiya
二宮 周一
Noriyuki Azuma
東 憲行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13348282A priority Critical patent/JPS5923644A/en
Publication of JPS5923644A publication Critical patent/JPS5923644A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H40/00Arrangements specially adapted for receiving broadcast information
    • H04H40/18Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/72Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for noise suppression
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/1646Circuits adapted for the reception of stereophonic signals

Abstract

PURPOSE:To prevent an increase in discomfort noise by stopping the functions of a sound field controlling circuit automatically when a weal signal or multipath disturbing wave is received. CONSTITUTION:The sound field controlling circuit 17 is so controlled by the output of a signal intensity detector 19 or multipath detector 20 so that its internal switch 18 is turned off. When the extent of disturbance increases up to a specific value, the detector 10 sends out the OR output of an OR circuit 21 and when a weak signal is received, on the other hand, the signal intensity detector 19 sends out the OR output of the circuit 21. Consequently, the switch 18 controlled by the OR output of detector 19 or 20 is turned on in response to an increase in discomfort noise generated by the sound field controlling circuit during weak signal or multipath disturbance reception to stop the sound field controlling functions forcibly.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はステレオ受信時に音場制御を行なうためステレ
オ復調器と低周波増幅器の間に音場制御回路を付加した
ステレオ信号再生回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a stereo signal reproducing circuit in which a sound field control circuit is added between a stereo demodulator and a low frequency amplifier to perform sound field control during stereo reception.

従来例の構成とその問題点 第1図は従来より使用されている音場制御回路を説明す
るためのブロックダイヤグラムである。
1. Configuration of conventional example and its problems FIG. 1 is a block diagram for explaining a conventional sound field control circuit.

第1図において、左右のステレオ信号り、Rは端子1,
2から各々の加算器3,4に加えられる一方、差信号発
生回路6に加ふられ、差信号発生回路6で差信号(L−
R)に変換され、遅延回路6によって一定の遅延時間m
だけ遅らされる。そしてこの遅延回路6の出力は利得係
数Kを有する係数回路7に加えられ、さらに係数回路7
の出力は位相反転信号発生回路8に加えられ互いに逆位
相の差信号9および10として出力される0この時の差
信号9.10は、 K(L−R)m        ・・・・・・・・・ 
 (1)K(R−L)m        ・・・・・・
・・・  (2)で表わされ、これらがそれぞれ加算器
3,4に加えられる。したがって加算器3.4の出力信
号はそれぞれ、 L+K(L−R)m      =−−・・・・(3)
R+K(R−L)m      ・・・・・・・・・ 
 (萄で表わすことができる。そして(3)式、(4)
式で表わされる加算器3,4の出力信号はそれぞれ低周
波増幅器11.12で増幅されスピーカ13.14に印
加される。したがってスピーカ13からは(3)式で表
わされる出力信号に相当する音が出力されスピーカ14
からは(4)式で表わされる出力信号に相当する音が出
力される。ここで、(3)式、(4)式中の利得係数K
、遅延時間mを適尚な値に設定することによりステレオ
音をワイド化してステレオ効果をより高めることができ
ることは周知の通りであり、テープレコーダのステレオ
信号再生に広く用いられている。
In Figure 1, left and right stereo signals are shown, R is terminal 1,
2 to each adder 3, 4, and is added to the difference signal generation circuit 6, where the difference signal (L-
R) and is converted into a constant delay time m by the delay circuit 6.
only delayed. The output of this delay circuit 6 is then applied to a coefficient circuit 7 having a gain coefficient K, and further the coefficient circuit 7
The output of 0 is applied to the phase inversion signal generation circuit 8 and output as difference signals 9 and 10 with mutually opposite phases.The difference signal 9.10 at this time is K(L-R)m...・・・
(1) K(R-L)m ・・・・・・
... (2), and these are added to adders 3 and 4, respectively. Therefore, the output signals of adder 3.4 are respectively L+K(L-R)m =-- (3)
R+K(R-L)m ・・・・・・・・・
(It can be expressed as a grape.Then, equation (3), (4)
The output signals of adders 3 and 4 expressed by the equations are respectively amplified by low frequency amplifiers 11.12 and applied to speakers 13.14. Therefore, the speaker 13 outputs a sound corresponding to the output signal expressed by equation (3), and the speaker 14
, a sound corresponding to the output signal expressed by equation (4) is output. Here, the gain coefficient K in equations (3) and (4)
It is well known that by setting the delay time m to an appropriate value, it is possible to widen the stereo sound and further enhance the stereo effect, and it is widely used for stereo signal reproduction in tape recorders.

しかしながら、前述の音場制御回路をFMステレオ放送
などの受信機のステレオ信号再生に用いると、弱信号受
信時およびマルチパス妨害波受信時において左右チャン
ネルのステレオ信号り、R中にノイズが重畳しているた
め、前記位相反転信号発生回路8の各々の差信号9,1
0を加算器3゜4にそれぞれ加算したとき(1)式、(
掲式より明らかなようにノイズ成分の増加を招くことに
な9ステレオ信号再生に対し極めて大きな音質劣化を招
くという問題があった。
However, when the above-mentioned sound field control circuit is used for stereo signal reproduction in a receiver such as FM stereo broadcasting, noise is superimposed on the left and right channel stereo signals and R when receiving a weak signal or receiving a multipath interference wave. Therefore, each difference signal 9, 1 of the phase inverted signal generation circuit 8
When adding 0 to each adder 3゜4, equation (1), (
As is clear from the above formula, there was a problem in that the noise component increased and the sound quality deteriorated significantly when reproducing nine stereo signals.

発明の目的 本発明は以上のような従来の欠点を除去するものであり
、弱信号受信時、マルチパス妨害波受信時でも不快なノ
イズの増加を来たすことなく常に優れた再生状態が得ら
れるようにすることを目的とするものである。
Purpose of the Invention The present invention is intended to eliminate the above-mentioned drawbacks of the prior art, and to provide an excellent reproduction state at all times without increasing unpleasant noise even when receiving weak signals or receiving multipath interference waves. The purpose is to

発明の構成 本発明はステレオ復調器と低周波増幅器との間に差信号
発生回路、遅延回路、加算器などで構成される音場制御
回路を設けるとともに、この音場制御回路の機能が弱信
号受信時、マルチパス妨害波受信時に自動的に停止する
ように構成したものである。
Structure of the Invention The present invention provides a sound field control circuit composed of a difference signal generation circuit, a delay circuit, an adder, etc. between a stereo demodulator and a low frequency amplifier, and the function of this sound field control circuit is to detect weak signals. It is configured to automatically stop when receiving multipath interference waves.

実施例の説明 第2図は本発明の一実施例のブロックダイヤグラムであ
る。
DESCRIPTION OF THE EMBODIMENT FIG. 2 is a block diagram of an embodiment of the present invention.

図中、15はFM検波器、16はステレオ復調器、17
は音場制御回路であシ、係数回路7と位相反転信号発生
回路8の間にスイッチ18が接続されている以外は第1
図に示す構成と同一の構成である。図で明らかなように
音場制御回路17は信号強度検出器19とマルチパス検
出器20のそれぞれの出力のいずれかでスイッチ18を
遮断するように制御される。
In the figure, 15 is an FM detector, 16 is a stereo demodulator, and 17
is a sound field control circuit, except that a switch 18 is connected between the coefficient circuit 7 and the phase inversion signal generation circuit 8.
This is the same configuration as shown in the figure. As is clear from the figure, the sound field control circuit 17 is controlled to cut off the switch 18 using either of the outputs of the signal strength detector 19 and the multipath detector 20.

ここでマルチパス検出器20としては、(1)中間周波
信号の振幅変調レベル、(2)検波信号におけるパイロ
ット信号の振幅変調レベル、(3)検波信号におけるコ
ンポジット信号帯域外の高調波レベルなどを検出する回
路を用いることができる。そしてマルチパス検出器2o
はその妨害の程度が大きくなって所定の値となるとオア
回路21から論理和出力を、一方信号強度検出器19は
弱信号時オア回路21−から論理和出力を出力するよう
設定される0 すなわち弱信号受信時およびマルチパス妨害受信時にお
ける音場制御回路によって生ずる耳ざわりなノイズ増加
を信号強度検出器19とマルチパス妨害検出器2oとの
論理和出力によって制御されるスイッチ18の遮断によ
り強制的弧音場制御機能を停止するものである。これに
より聴感上のノイズ感を大きく減少することができる。
Here, the multipath detector 20 detects (1) the amplitude modulation level of the intermediate frequency signal, (2) the amplitude modulation level of the pilot signal in the detected signal, (3) the harmonic level outside the composite signal band in the detected signal, etc. A detection circuit can be used. and multipath detector 2o
is set to output an OR output from the OR circuit 21 when the degree of interference increases to a predetermined value, and on the other hand, the signal strength detector 19 is set to output an OR output from the OR circuit 21- when the signal is weak. The increase in harsh noise caused by the sound field control circuit when receiving a weak signal and when receiving multipath interference is forcibly suppressed by shutting off the switch 18 controlled by the OR output of the signal strength detector 19 and the multipath interference detector 2o. This stops the arc sound field control function. As a result, the auditory sense of noise can be greatly reduced.

なお、第2図に示す実施例では音場制御機能を停止する
スイッチ18を係数回路7と位相反転信号発生回路80
間に接続したが、差信号発生回路6より加算器3,4に
至るまでの信号経路であればどこに挿入しても同様に実
現することが可能である。
In the embodiment shown in FIG. 2, the switch 18 for stopping the sound field control function is connected to the coefficient circuit 7 and the phase inversion signal generation circuit 80.
However, the same effect can be achieved by inserting the signal anywhere in the signal path from the difference signal generation circuit 6 to the adders 3 and 4.

発明の効果 上記実施例より明らかなように本発明のステレオ信号再
生回路によれば弱信号受信時、およびマルチパス妨害波
受信時にそれぞれ音場制御回路がその機能を自動的に停
止するように構成されているため、弱信号受信時、マル
チパス妨害受信時でも不快なノイズの増加がなく、実用
上きわめて有利なものである。
Effects of the Invention As is clear from the above embodiments, according to the stereo signal reproducing circuit of the present invention, the sound field control circuit is configured to automatically stop its function when a weak signal is received and when a multipath interference wave is received. Therefore, there is no increase in unpleasant noise even when receiving a weak signal or receiving multipath interference, which is extremely advantageous in practice.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来用いられている音場制御回路のブロック図
、第2図は本発明のステレオ信号再生回路の一実施例の
ブロック図である。 3,4・・・・・・加算回路、6・・・・・・差信号発
生回路、6・・・・遅延回路、7・・・・・・係数回路
、8・・・・・・位相反転信号発生回路、15・・・・
・・FM検波器、16・・・・・・ステレオ復調器、1
7・・・・・・音場制御回路、18・・・・・・スイッ
チ、19・・・・・・信号強度検出器、2o・・・・・
・マルチパス検出器、21・・・・・・オア回路。
FIG. 1 is a block diagram of a conventional sound field control circuit, and FIG. 2 is a block diagram of an embodiment of the stereo signal reproducing circuit of the present invention. 3, 4... Addition circuit, 6... Difference signal generation circuit, 6... Delay circuit, 7... Coefficient circuit, 8... Phase Inverted signal generation circuit, 15...
...FM detector, 16...Stereo demodulator, 1
7...Sound field control circuit, 18...Switch, 19...Signal strength detector, 2o...
・Multipath detector, 21...OR circuit.

Claims (1)

【特許請求の範囲】[Claims] ステレオ復調器と低周波増幅器との間に差信号発生回路
、遅延回路、加算器などで構成される音場制御回路を接
続するとともに上記音場制御回路内にスイッチ回路を設
は弱信号受信時、マルチパス妨害波受信時にそれぞれ所
定の信号を出力する受信信号強度検出器、FMマルチパ
ス妨害検出器の出力信号によって上記スイッチ回路をオ
ン、オフ制御し弱信号受信時、マルチパス妨害波受信時
に上記音場制御回路の機能を停止するように構成したス
テレオ信号再生回路。
A sound field control circuit consisting of a difference signal generation circuit, a delay circuit, an adder, etc. is connected between the stereo demodulator and the low frequency amplifier, and a switch circuit is installed within the sound field control circuit to detect weak signals. , a received signal strength detector that outputs a predetermined signal when receiving a multipath interference wave, and an FM multipath interference detector that controls the above switch circuits on and off according to the output signals, respectively, when receiving a weak signal and when receiving a multipath interference wave. A stereo signal reproduction circuit configured to stop the function of the sound field control circuit.
JP13348282A 1982-07-29 1982-07-29 Stereophonic signal reproducing circuit Pending JPS5923644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13348282A JPS5923644A (en) 1982-07-29 1982-07-29 Stereophonic signal reproducing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13348282A JPS5923644A (en) 1982-07-29 1982-07-29 Stereophonic signal reproducing circuit

Publications (1)

Publication Number Publication Date
JPS5923644A true JPS5923644A (en) 1984-02-07

Family

ID=15105796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13348282A Pending JPS5923644A (en) 1982-07-29 1982-07-29 Stereophonic signal reproducing circuit

Country Status (1)

Country Link
JP (1) JPS5923644A (en)

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