JPS5955537A - ネクストアドレス方式のプロセッサ - Google Patents

ネクストアドレス方式のプロセッサ

Info

Publication number
JPS5955537A
JPS5955537A JP57165088A JP16508882A JPS5955537A JP S5955537 A JPS5955537 A JP S5955537A JP 57165088 A JP57165088 A JP 57165088A JP 16508882 A JP16508882 A JP 16508882A JP S5955537 A JPS5955537 A JP S5955537A
Authority
JP
Japan
Prior art keywords
output
address
circuit
gate
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57165088A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0445863B2 (enrdf_load_stackoverflow
Inventor
Akio Iba
章雄 伊庭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP57165088A priority Critical patent/JPS5955537A/ja
Publication of JPS5955537A publication Critical patent/JPS5955537A/ja
Publication of JPH0445863B2 publication Critical patent/JPH0445863B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Executing Machine-Instructions (AREA)
JP57165088A 1982-09-24 1982-09-24 ネクストアドレス方式のプロセッサ Granted JPS5955537A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57165088A JPS5955537A (ja) 1982-09-24 1982-09-24 ネクストアドレス方式のプロセッサ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57165088A JPS5955537A (ja) 1982-09-24 1982-09-24 ネクストアドレス方式のプロセッサ

Publications (2)

Publication Number Publication Date
JPS5955537A true JPS5955537A (ja) 1984-03-30
JPH0445863B2 JPH0445863B2 (enrdf_load_stackoverflow) 1992-07-28

Family

ID=15805649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57165088A Granted JPS5955537A (ja) 1982-09-24 1982-09-24 ネクストアドレス方式のプロセッサ

Country Status (1)

Country Link
JP (1) JPS5955537A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421143A (en) * 1977-07-18 1979-02-17 Toshiba Corp Address designation circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421143A (en) * 1977-07-18 1979-02-17 Toshiba Corp Address designation circuit

Also Published As

Publication number Publication date
JPH0445863B2 (enrdf_load_stackoverflow) 1992-07-28

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