JPS595330A - Cycle steal controlling system - Google Patents

Abstract

PURPOSE:To simplify a cycle steal controlling circuit, by using a storage holding address also as a signal for a cycle steal request or a cycle steal permisson. CONSTITUTION:Peripheral equipments 1A, 1B execute processing of input/output of data processed by a data processing device 4. Each peripheral equipment 1A, 1B is provided with comparing circuits 2A, 2B and storage protecting address generating circuits 3A, 3B, respectively. Each storage protecting address generating circuit 3A, 3B generates a storage protecting address corresponding to a degree of priority of a cycle steal request. This storage protecting address is used also as a signal of the cycle steal request or a cycle steal permission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention connects a plurality of peripheral devices and a data processing device in a loop, and transfers a memory protection address to achieve cycle recovery.
A cycle steal control method that makes it possible to efficiently control steal requests and acceptance of cycle steal requests. [Prior art and problems] Data is transferred from peripheral devices to the storage device of the data processing device. In some cases, the peripheral device issues a cycle steal request and receives a cycle steal permission signal from the data processing device in order to interrupt the execution of instructions in the control circuitry of the data processing device and to control memory protection. In response, a cycle steal operation is entered, and data is transferred via the address bus and data path.

Conventionally, when controlling the cycle steal described above, a signal line for cycle steal request is provided as well as a signal line for cycle steal permission, and whether the data processing device is a path connection or a star connection, each data processing device Peripheral devices were controlled individually. Furthermore, the memory protection address was sent out through a different path from the cycle steal request signal line. So there was a cycle.

(Object of the Invention) The present invention solves the above-mentioned problems, and uses a cycle +1:) tail control method that simplifies the control of the cycle [phase] steel and reduces the amount of no. The purpose is to provide

[Structure of the invention]

To this end, the cycle resteal control method of the present invention has a memory protection address creation circuit that creates its own memory protection address, and the memory protection address created by the memory protection address creation circuit and the memory protection address input from another device. A plurality of peripheral devices each have a comparison and selection circuit that compares the magnitude of the memory protection address and outputs the one with higher priority, and performs memory protection boonicking based on the memory protection address notified from the control circuit and the peripheral device. comprising a data processing device having a storage protection circuit and a storage device;
The plurality of peripheral devices are connected in series to the data processing device such that the memory protection address of each peripheral device is selected and notified to the data processing device through the comparison and selection circuit, and the control circuit is configured to A cycle in a data processing system that determines a notified memory protection address as a cycle-steal request, starts a cycle steal operation, holds the notified memory protection address, and sends it back to the peripheral device in a loop. In the control method, the comparison and selection circuit notifies the data processing device of the memory protection address, and starts cycle stealing of the peripheral device on the condition that the input memory protection address and its own memory protection address match. The control circuit is configured to prohibit
The control circuit holds the memory protection address and sends it back to the peripheral device again in a loop, and then the comparison circuit compares the memory protection address returned through the loop with the memory retention address held, and the comparison result is The present invention is characterized in that it is configured to perform control to prohibit execution of a cycle steal operation on the condition that there is a mismatch.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are flow charts showing the flow of processing of a data processing system according to the present invention. In Figure 1, IA and IB
is a peripheral device (ADP), 2 people and 2B are comparison selection circuits,
3A and 3B are storage protection address generation circuits, 4 is a data processing unit (DPU), 5 is a control circuit, 6 is a comparison circuit, 7 is a PEXC (memory protection check circuit), and 8 is a storage device.

In FIG. 1, peripheral devices IA and IB are used to input and output data processed by the data processing device 4. Each peripheral device tlA and IB includes two comparison selection circuits and 2B, and three memory protection address generation circuits and 8B.
is provided, and when a plurality of peripheral devices issue cycle steal requests at the same time, a priority order is arbitrarily assigned in advance to determine which cycle steal request should be handled preferentially. Then, when a value corresponding to the assigned priority is set, each memory protection address generation circuit 3 and 3B
is the memory protection address PKA (
Create Protect Key Addresses3). The two comparison and selection circuits and 2B have a terminal for inputting the memory protection address PKA from the PKA (Protect Key Address) path and a terminal for outputting the memory protection address PKA to the PKA bus,
The input storage protection address PKA sent from other devices (data processing device 4 in the case of two comparison and selection circuits, peripheral device [IA) in the case of comparison and selection circuit 2B and the storage protection address of the own device,
The path creation circuit compares the size relationship with the memory protection address PKA created by 3 people or 3B, and if the own memory protection address PKA is larger, outputs the own memory protection address PKA to the PKA path, and also outputs the own memory protection address PKA to the PKA path. If the storage protection address PKA is small, the input storage protection address sent from another device is output to the PKAtl-PKA bus and transferred, and various other processes are performed. That is, in the comparison of the above-mentioned size relationships, the one with the largest comparison result is determined to have a higher priority, and conversely, the one with a lower priority is determined to have a lower priority, and the storage protection address PKA with the higher priority is determined to be the one with the highest priority. Output to path.

Therefore, the comparison and selection circuits 2 and 2B transfer the input storage protection address PKA as is to the next device if their own device does not issue a cycle steal request. For example, if the peripheral device IB is about to issue a cycle steal request, the storage protection address PKA created by the storage protection address creation circuit 3B is the input storage protection address PKA sent from the peripheral device IA. Therefore, in such a case, the comparison and selection circuit 2B determines that there is an error and selects the own device, that is, the peripheral device IB.
Prohibit disclosure of cycle steals.

However, if the input memory protection address PKA matches the memory protection address PKA created by the memory protection address creation circuit 3B while the peripheral device IB has already issued a cycle O steal request, then the cycle Since it is determined that the steal request is permitted, in such a case, the comparison and selection circuit 2B performs control to enter a cycle steal operation. The data processing device 4 has a storage device 8, and uses a control circuit 5 to sequentially fetch and execute instructions. A PEXC (memory protection check circuit) 7 performs a memory protection check based on a memory protection address PKA sent from a peripheral device. When the control circuit 5 receives the memory protection address PKA from the peripheral device IB, after confirming the check by the PEXC (memory protection check circuit) 7, it starts a cycle steal operation on the data processing device 4 side. Control is performed to send the sent storage protection address PKA back to the farthest peripheral device 1tlA in a loop. The storage protection address PKA is transferred from the data processing device 4 to the peripheral device IA via a loop-connected PKA path.

The data is transferred to the IB and then transferred again to the data processing device 4. The memory protection address PKA that is returned at this time is
It should match the memory protection address PKA that was previously accepted by the control circuit 5, but when the comparison is performed by the comparison circuit 6 and it is found that they do not match, the peripheral device fiilAt
It is determined that IB or IB was not selected correctly, and execution of the cycle fist steal motion is stopped.

Next, the flow of processing of the data processing system configured as described above will be explained with reference to FIG.

Below, the memory protection address PKA of the peripheral device tlA=″1
A case will be described in which the storage protection address PKA of the peripheral device IB is set to "2" and the peripheral devices IA and IB issue cycle steal requests at the same time.

(2) Before the cycle steal is executed, that is, in the initial state, the storage protection address on the PKA path is in the "0" state.

(2) Here, when a cycle steal request is issued to the peripheral device IA, the memory protection address creation circuit 3A creates +1" as the memory protection address PKA and sends it to the two comparison and selection circuits.

(2) At the same time, when a cycle steal request occurs in the peripheral device IB, the memory protection address creation circuit 3B creates "2" as the memory protection address PKA, and sends it to the comparison selection circuit 2B.

(2) Comparison and selection circuit Two people compare the input storage protection address PKA "O" with its own storage protection address PKA "1".

■ Compare the size of the input storage protection address PKA″O″ and its own storage protection address PKA″′1″, and if a judgment result of size is obtained, perform the process of the next ■, and check the size judgment result. If cannot be obtained, i.e., both are the same, then
Withdraw own cycle steal request and cycle Φ
Prohibit initiation of steal. (This is because each peripheral device is assigned a unique memory protection address PKA, so at this point it is impossible for the above input memory protection address PKA to match its own memory protection address PKA. In this case, it is determined that vAυ has occurred in either PKA ■ Comparison and selection circuit The two people output their own memory protection address PKA "1", which is considered to be the larger one, to PKAKS, and the comparison and selection circuit of the peripheral device IB Notify 2B.

■or■ Performs the same process as ■or■ in the peripheral device IB for the input memory protection address PKA"1" and its own memory protection address PKA"2", and outputs its own memory protection address PKA"2" to the PKAK address. and notifies the control circuit 5 of the data processing device 4.

[Phase] Check whether cycle stealing is possible in the control circuit 5. In the case of Yes, the process of ■ is performed.

(2) The control circuit 5 determines that the memory protection address PKA "2" is a cycle steal request and starts preprocessing.

If it is determined that there is a cycle steal request from the above peripheral device and the process up to the start of the cycle steal operation is the first stage process, then the process after the next ◎ is the second stage process.

0 The control circuit 5 stores the stored memory protection address PKA''
2'' is sent back to the peripheral [IA] in a loop via the PKAK bus.

[Phase] In the two comparison and selection circuits, the input storage protection address PKA″2″ and its own storage protection address PKA″1
” to check for a match.

(2) Since the boonick result is No, the process of [phase] is performed, the peripheral device IA is made unable to execute the cycle operation steal, and the three memory protection address generation circuits are turned off.

0 Comparison selection circuit 2 people use memory protection address PKA''2
'' is output as a PK bus and notified to the comparison selection circuit 2B of the peripheral device IB.

[Phase] In the comparison selection circuit 2B, the input memory protection address PKA"2" and its own memory protection address PKA"2
” to check for a match.

■ Since the check result is Yes, perform the process of [phase].

[Phase] The comparison selection circuit 2B selects the memory protection address PKA.
"'2" is output to the PKAK bus to notify the control circuit of the data processing device 4.

[Phase] Compare and select the memory protection address PKA ``2'' received by the control circuit at 0 above with the selection circuit 2 at 0 above.
It is checked whether it matches the memory protection address PKA "2" sent back from B, and since the result is Yes, 0 processing is performed. If No here, the peripheral device uses the memory protection address PKA "2" returned in 0 above.
It is determined that the cycle steal operation has not been correctly selected according to the above, and execution of the cycle steal operation is aborted.

(This is because, if normal, the memory protection address PKA "2" received by the control circuit 5 in the first stage processing and the memory protection address PKA sent back to the peripheral device in the second stage processing and returned to the control circuit 5 again match) This is because it is supposed to be done.

) ■ Peripheral device IB and storage device 80 in data processing device 4
A cycle steal is performed between.

Note that in the first stage processing, the value of the memory protection address PKA notified from the peripheral device IB is
If it is a value other than the value assigned to B, of course PE
An error occurs in XC7 (memory protection check circuit).

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the memory protection address is also used as a cycle steal request and cycle steal permission signal, which simplifies the cycle steal control circuit. In addition, the amount of hardware can be reduced. Moreover,
Since an error can be detected when a memory protection address is input to a peripheral device or a data processing device, it is possible to improve RAS such as usability. Furthermore, the priority of each peripheral device can be arbitrarily determined by the memory protection address, and even if peripheral devices are added, the control will not change.
It has various effects such as being highly flexible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are flow charts showing the processing flow of the data processing system according to the present invention. IA and IB...Peripheral device (ADP), 2A and 2B...
... Comparison selection circuit, 3A and 3B... Memory protection address creation circuit, 4... Data processing unit [(DPU), 5.
...Control circuit, 6...Comparison circuit, 7...PEXC (
memory protection check circuit), 8... storage device. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (1)

[Claims] It has a memory protection address generation circuit that creates its own memory protection address, and compares the size of its own memory protection address created by the memory protection address generation circuit with the memory protection address input from another device to determine the priority. A data processing device comprising a plurality of peripheral devices including a comparison and selection circuit that outputs the larger of the two, and a storage device and a storage protection check circuit that performs a storage protection check based on a storage protection address notified from the control circuit and the peripheral device. the plurality of peripheral devices are connected in series to the data processing device such that the memory protection address of each peripheral device is selected through the comparison and selection circuit and notified to the data processing device; , determines that the notified memory protection address is a cycle steal request, starts a cycle steal operation, retains the notified memory protection address, and sends the data back to the peripheral device in a loop again. In the cycle steal control method in the processing system, when the comparison and selection circuit notifies the data processing device of the storage protection address, the comparison and selection circuit determines whether the input storage protection address and its own storage protection address match. The control circuit is configured to inhibit initiation of a cycle steal, and the control circuit includes a comparison circuit, and the control circuit retains the memory protection address and loops it back to the peripheral device, and then returns the memory protection address through the loop. The comparison circuit compares the stored storage protection address with the stored storage address held by the comparison circuit, and if the comparison result does not match, control is performed to prohibit execution of the cycle steal operation. A cycle steal control system featuring