JPH05158781A - Exclusive flag management device for shared memory system - Google Patents

Abstract

PURPOSE:To immediately permit the access of the other computer to the shared memory in case of a fault generation in a computer with the exclusive flag. CONSTITUTION:The number of a computer with the exclusive flag is extracted by an encoder 13 to be recorded on a register 16. In case of a fault generation, the computer number is extracted by an encoder 12, and a comparator 17 collates it with the computer number with the exclusive flag on the register 16. If both numbers are matched, a flip-flop 19 outputs a forced reset signal of the exclusive flag.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exclusive flag management device in a shared memory system.

[0002]

2. Description of the Related Art In a composite computer system in which a plurality of computers are connected, a shared memory system is one of the means for connecting a plurality of computers.

FIG. 3 shows four computers 101, 102, 1
3 shows a composite computer system in which 03 and 104 are connected by a shared memory device 105. The shared memory device 105 is provided with an exclusive flag 106 that excludes the reference process and the update process of each computer.

In the above configuration, two computers 101, 1 are now used for the data X at address A in the shared memory.
Assume that 02 executes a process of adding "1".

First, as shown in FIG. 4, when exclusive control is not performed, the computer 101 reads the data X and outputs "1".
Is added to obtain data X + 1. This addition data X + 1
Is written in the address A, and the processing by the computer 101 is terminated. After reading the data X of the computer 101, the computer 102 also reads the data X and adds “1” to obtain the data X + 1. This addition data X + 1 is also the address A
Written in. As a result, the data finally written in the address A becomes X + 1, and the expected result, that is, the data X + 2 finally written in the address A is obtained.
Can't get

On the other hand, as shown in FIG. 5, in the case of exclusive control, when the computer 101 sets the exclusion flag 106, the access by the computer 102 is suspended during that period. The computer 101 reads the data X from the address A, adds “1”, and writes the added data X + 1 to the address A. After the writing is completed, the exclusive flag 106 is reset to release the exclusive control. Next, the computer 102 sets the exclusive flag 106. The computer 102 reads the data X + 1 from the address A, adds "1", and writes the added data X + 2 to the address A. After writing,
The exclusive flag 106 is reset to release the exclusive control.
As a result, the expected data X + 2 is obtained at the address A.

[0007]

However, the computer 101 that has set the exclusive flag 106 sets the flag 10
If any failure occurs in the computer 101 before or while resetting 6, the exclusive flag 106 may not be reset. In this case, the exclusion flag 106 is not reset forever even after the processing of the computer 101 ends, so that the shared memory device 105 cannot be accessed by another computer 102.

Therefore, as a means for solving this, an exclusive flag management device using a watchdog timer has been conventionally known.

This conventional apparatus monitors the time when the exclusion flag is set by a watchdog timer, and forcibly resets the exclusion flag when the exclusion flag continues to be set for a certain period of time. Is.

However, in this conventional apparatus, in order to prevent the exclusive flag from being accidentally reset, the monitoring time is set to a time obtained by adding a margin to the maximum value of the normally set exclusive flag set times. .. For this reason, this monitoring time becomes quite long, and even if a computer with the exclusive flag set fails, other computers cannot immediately access the shared memory and the monitoring period is There was a problem that we had to wait until the end.

The present invention has been made in view of the above circumstances, and an object of the present invention is to permit access to a shared memory by another computer immediately when a computer having an exclusive flag set fails. An object of the present invention is to provide an exclusive flag management device in a shared memory system that can be used.

[0012]

In order to achieve the above object, the present invention provides an exclusive flag management device for managing setting and resetting of an exclusive flag provided on a shared memory device shared by a plurality of computers. A recording means for recording the number of the computer having the exclusive flag set, and when a failure occurs in any of the computers, the number of the computer and the computer number having the exclusive flag set in the recording means And a resetting means for forcibly resetting the exclusive flag when both numbers match as a result of the matching.

[0013]

When the access request to the shared memory device is issued from any of the computers, the exclusive flag is set first.
The number of the computer that sets this exclusion flag is recorded.

When a failure occurs in any of the computers, a failure notification is supplied from the computer, and the computer number is extracted from this failure notification and compared with the computer number with the exclusive flag set. As a result of the comparison, when the two numbers match, the exclusive reset flag forced reset signal is output.

[0015]

1 is a block diagram showing a configuration of an embodiment of an exclusive flag management device according to the present invention, and FIG. 2 is a configuration diagram of a compound computer system to which the exclusive flag management device according to the present invention is applied. ..

As shown in FIG. 2, the composite computer system of this embodiment comprises four computers 1, 2, 3 and 4 and a shared memory device 5 shared by these computers 1 to 4. The shared memory device 5 includes an input / output device 6 that receives access requests from the computers 1 to 4 and sends data to the computers 1 to 4, and the computers 1 to 4
The exclusion flag 7 for eliminating the reference process and the update process for the shared memory device 5 from the device, the exclusion flag management device 8 for managing the setting and resetting of the exclusion flag 7, and the data shared by the computers 1 to 4 are And a stored memory 9.

As shown in FIG. 1, the exclusive flag management device 8 is an OR circuit for inputting any of the fault notifications E1 to E4 from the computers 1 to 4 and generating the fault occurrence signal S11 by inputting the fault notifications E1 to E4. 11, an encoder 12 for inputting each of the fault notifications E1 to E4 to extract the number of the computer that has output the fault notification, and a set request SD1 to SD4 for the exclusive flag 7 from each of the computers 1 to 4 to input and set An encoder 13 that extracts the numbers of the computers 1 to 4 that output the request,
An OR circuit 14 that inputs the exclusive flag set requests SD1 to SD4 from any of the computers 1 to 4 to generate a flag set command S14 and the exclusive flag reset requests RD1 to RD4 from each of the computers 1 to 4 are input. And the OR circuit 15 for generating the flag reset command S15 by the encoder 1
A register 16 for storing the computer number extracted in 3;
Output S16 of register 16 and output S1 of encoder 12
Comparing 2 with each other, a comparator 17 which outputs a coincidence signal S17 when they coincide with each other, and an AND circuit 18 which takes a logical product of the coincidence signal S17 of the comparator 17 and the output signal (fault occurrence signal) S11 of the OR circuit 11 And the output signal (forced reset command) S18 of the AND circuit 18, the output signal (flag reset command) S15 of the OR circuit 15 and the clock signal CL, and outputs the set / reset signal S19 of the exclusive flag to the exclusive flag 7. And a JK flip-flop 19 that operates.

Next, the operation of this embodiment will be described.

Now, assume that the computer 3 exclusively accesses the shared memory device 5. When the computer 3 outputs the exclusive flag set request SD3, this request signal SD3 is input to the encoder 13 and the OR circuit 14. The encoder 13 extracts the computer number from the request signal SD3 and supplies the number signal S13 to the register 16. The register 16 stores the computer number.

When the request signal SD3 is input, O
The R circuit 14 outputs the set command signal S14 to the J terminal of the flip-flop 19. As a result, the flip-flop 19 outputs the set signal S19 to the exclusion flag 7 to set the exclusion flag 7. If an access request is issued from any of the other computers 1, 2 and 4 while the exclusion flag 7 is set, a signal indicating that the exclusion flag 7 is being set is output to the corresponding computer, and this computer Access is excluded.

When access to the memory 9 of the computer 3 is completed and the reset request RD3 is output from the computer 3, the OR circuit 15 outputs the reset command signal S15 to the K terminal of the flip-flop 19. As a result, the flip-flop 19 resets the exclusive flag 7. By resetting the exclusive flag 7, access to other computers 1, 2, 4 is permitted.

On the other hand, the computer 3 with the exclusive flag 7 set
However, if any failure occurs before the reset request RD3 is output, the failure notification E3 of the computer 3 is supplied to the OR circuit 11 and the encoder 12. The OR circuit 11 outputs a failure detection signal S11 to the AND circuit 8 in response to the failure notification signal E3. Also, the failure notification E3
Thus, the encoder 12 extracts the number of the failure occurrence computer and supplies the number signal S12 to the comparator 17. The comparator 17 is supplied with the number signal S16 of the computer with the exclusive flag set. This computer number is compared with the faulty computer number, and if both numbers match, AND is performed.
The coincidence signal S17 is output to the circuit 18. As a result, AN
The forced reset command S18 is output from the D circuit 18 to the clear terminal of the flip-flop 19, whereby the forced reset signal is output from the flip-flop 19 to the exclusion flag 7 and the exclusion flag 7 is forcibly reset.

On the other hand, when a failure occurs in a computer that does not set the exclusion flag 7, for example, the computer 1, the failure notification E1 from this computer 1 is also input to the OR circuit 11 and the encoder 12, but the exclusion flag is set. Since the set computer number and the faulty computer number do not match, the match signal S17 is not output from the comparator 7 and the exclusion flag 7 is not reset.

As described above, according to this embodiment, the exclusion flag 7 is reliably reset without delay when a failure occurs in the computer in which the exclusion flag 7 is set.

In this embodiment, the exclusion flag management device 5 is constructed by hardware. However, the firmware compares the failure computer number with the computer number for which the exclusion flag 7 is set, requests for resetting the exclusion flag 7, and the like. You may do it. Furthermore, it is also possible to combine the present embodiment with an exclusive flag management method of another method such as the watchdog timer method described above.

[0026]

As described above, according to the present invention, the exclusion flag can be surely reset without delay when a failure occurs in the computer in which the exclusion flag is set, and the shared computer system is adopted. Improves reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an exclusive flag management device according to the present invention.

FIG. 2 is a configuration diagram of a compound computer system to which an exclusive flag management device according to the present invention is applied.

FIG. 3 is a block diagram of a conventional complex computer system.

FIG. 4 is an explanatory diagram showing an operation when exclusive control is not performed in the composite computer system.

FIG. 5 is an explanatory diagram showing an operation when exclusive control is performed in the complex computer system.

[Explanation of symbols]

 1, 2, 3, 4 Computer 5 Shared memory device 6 Input / output device 7 Exclusive flag 8 Exclusive flag management device 9 Memory 11, 14, 15 OR circuit 12, 13 Encoder 16 Register (recording means) 17 Comparator (verifying means) 18 AND circuit 19 flip-flop (reset means)

Claims (1)

[Claims] 1. An exclusive flag management device for managing the setting and resetting of an exclusive flag provided on a shared memory device shared by a plurality of computers, and a recording means for recording the number of the computer that has set the exclusive flag. When a failure occurs in any of the computers, a collating unit that collates the computer number with the computer number that sets the exclusive flag recorded in the recording unit, and as a result of the collation, both numbers are An exclusive flag management device in a shared memory system, comprising: resetting means for forcibly resetting the exclusive flag when they match.