JPS5952835A - Plasma vapor reactor - Google Patents

Plasma vapor reactor

Info

Publication number
JPS5952835A
JPS5952835A JP57163730A JP16373082A JPS5952835A JP S5952835 A JPS5952835 A JP S5952835A JP 57163730 A JP57163730 A JP 57163730A JP 16373082 A JP16373082 A JP 16373082A JP S5952835 A JPS5952835 A JP S5952835A
Authority
JP
Japan
Prior art keywords
reaction
substrate
reaction vessel
semiconductor layer
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57163730A
Other languages
Japanese (ja)
Other versions
JPH0436449B2 (en
Inventor
Shunpei Yamazaki
山崎 「しゆん」平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP57163730A priority Critical patent/JPS5952835A/en
Publication of JPS5952835A publication Critical patent/JPS5952835A/en
Publication of JPH0436449B2 publication Critical patent/JPH0436449B2/ja
Granted legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/54Apparatus specially adapted for continuous coating

Landscapes

  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To improve productivity by disposing substrates at regular intervals in mutually parallel while setting up a heat source in the direction of the surfaces, to which films are formed, of the substrates and installing reaction vessels while mutually connecting them. CONSTITUTION:To improve the uniformity of film thickness and the homogeneity of film quality in the upper sections, lower sections, and central sections ans peripheral sections of the substrates 4, 4', the surfaces thereof to which the films are formed are arranged in approximately parallel at regular intervals of 3- 5cm, infrared lamps 11, 11' are set up in the direction of the surfaces, to which the films are formed, and the substrates 4, 4' are heated by the infrared heaters 11, 11' at 100-400 deg.C such as 200 deg.C. Since the heaters 11, 11' have cylindrical parts, the heaters are arranged in the directions in which the upper heaters and the lower heaters cross mutually at right angles, and spaces, particularly, cylindrical spaces, in the reaction vessels are kept at 200+ or -10 deg.C, preferably, within + or -5 deg.C.

Description

【発明の詳細な説明】 本発明は基板上KP型、1型およびN型の導電型を有す
る非単結晶半導体を層状に積層して形成゛するに際し、
それぞれの半導体層をそれぞれに対応したプラズマ気相
反応用反応容器で形成せしめ、かつそれぞれの反応容器
を互いに連結して設けることによシ、外気(大気)Kふ
れさせることなく半導体層を形成せしめるプラズマ気相
反応装置に関する。
DETAILED DESCRIPTION OF THE INVENTION When forming non-single crystal semiconductors having conductivity types of KP type, 1 type and N type on a substrate in a layered manner,
By forming each semiconductor layer in a corresponding plasma gas phase application reaction vessel and by connecting the respective reaction vessels to each other, the semiconductor layer can be formed without exposure to outside air (atmosphere). It relates to a gas phase reactor.

本発明は水素またはハロゲン元素が添加された非単結晶
半導体層、好ましくは珪素、ゲルマニューム、炭化珪素
(810のみではなく、本発明においてはBIXOt−
AO<Xζ1の総称を意味する)、珪化ゲルマニューム
(81xGe、−、0<x<1)珪化スズ(81X8n
I−2、O<x<1)であって、この被膜中に活性状態
の水素またはハロゲン元素を充填することによシ、再結
合中心置数の小さなP工およびN型の導電型を有する半
導体層を複数層形成し、その積層境界にて接合例えばP
N接合、P工接合、N工接合またはP工N接合を形成す
るとともに、それぞれの半導体層に他の隣接する半導体
層からの不純物が混入して接合特性を劣化させることな
く形成するとともに、またそれぞれに半導体層を形成す
る工程間に大気特に酸素にふれさせて、半導体の一部が
酸化されることによシ、層間絶縁物が形成されることの
ないようにした連続生産を行なうためのプラズマ気相反
応用製造装置に関する。
The present invention is directed to a non-single crystal semiconductor layer doped with hydrogen or a halogen element, preferably silicon, germanium, silicon carbide (not only 810 but also BIXOt-
AO<Xζ1), germanium silicide (81xGe, -, 0<x<1) tin silicide (81X8n
I-2, O<x<1), and by filling this film with hydrogen or a halogen element in an active state, it has P-type and N-type conductivity types with a small number of recombination centers. A plurality of semiconductor layers are formed and bonded at the layer boundary, for example, P.
In addition to forming an N-junction, a P-junction, an N-junction, or a P-N junction, the formation is performed without impurities from other adjacent semiconductor layers being mixed into each semiconductor layer and deteriorating the junction characteristics; A method for continuous production in which interlayer insulators are not formed due to oxidation of part of the semiconductor by exposing it to air, particularly oxygen, between the steps of forming semiconductor layers on each semiconductor layer. Regarding plasma gas phase application manufacturing equipment.

本発明は形成される半導体被膜がスパッタ(損傷)され
ることなく、さらに非単結晶半導体といえども基板上よ
ジ結晶学的に成長(GROWTFOさせるため、被形成
面に平行に反応性気体およびプラズマ発生用の電界を供
給せしめることを特徴としている。
In the present invention, the semiconductor film to be formed is not sputtered (damaged), and even non-single-crystal semiconductors are grown crystallographically (GROWTFO) on the substrate. It is characterized by supplying an electric field for plasma generation.

さらに本発明は、かかる多数の反応容器を連結したマル
チチアンバ一方式のプラズマ反応装置において、一度に
多数の基板を同時にその被膜成長速度を大きくしたいわ
ゆる多量生産方式このため、反応性気体が反応容器内の
すべてに分散してしまうことを防ぎ、基板の被形成面を
利用して、筒状の空間に被形成面を1つの側に有する基
板を裏面を互いに密接して、一定の鹸離例えば2−y6
am代表的には3〜4cm離して平行に配列し、この基
板が林立した筒状空間においてのみプジズマ放電を行な
わしめ、加えて反応性気体を選択的に導びき、結果とし
て反応性気体の収集効率を従来の1〜3%よシその20
〜60倍の40〜)0チに゛まで高めたことを特徴とし
ている。
Furthermore, the present invention uses a multi-chamber type plasma reactor in which a large number of reaction vessels are connected, and uses a so-called mass production method in which a large number of substrates are simultaneously grown at a high film growth rate. By using the surface of the substrate to be formed, the back surfaces of the substrates having the surface to be formed on one side are brought into close contact with each other in a cylindrical space, and a certain distance, for example, 2 -y6
am is typically arranged in parallel at a distance of 3 to 4 cm, and performs psismal discharge only in the cylindrical space where these substrates stand, and in addition, selectively guides the reactive gas, resulting in the collection of the reactive gas. Efficiency improved by 1-3% compared to conventional method Part 20
It is characterized by increasing the temperature to 0 (~60 times 40~).

さらにその際多数回くシかえして被膜形成を行なうと、
その時反応容器上部に付着形成されたフレーク(微少せ
つ片)(微粉末)が基板の被形成面上に拓f;1ピンホ
ールの発生を訪発してしまうことを防ぐため、基板の被
形成面を重力にそって配向せしめたことを%徴としてい
る。
Furthermore, when forming a film by repeating it many times,
At that time, in order to prevent the flakes (fine particles) that were formed on the upper part of the reaction vessel from forming pinholes on the surface of the substrate to be formed, the surface of the substrate to be formed was The % sign is that the material is oriented along the direction of gravity.

本発明は、このフレークが反応性気体の導入口側で多数
発生してしまうことを防ぐため、反応性気体の導入口側
に網目状または多穴状に設けられた電極を負電極とし、
排気口側に正電極を設けたことを特徴としている。即ち
、本発明は実験的にフレークが正電極近傍に多く発生し
やすいことを見出し、このため負電極側を反応炉の上部
または反応性気体の導入口側に配したことを特徴として
いる。
In order to prevent a large number of flakes from being generated on the reactive gas inlet side, the present invention uses an electrode provided in a mesh or multi-hole shape on the reactive gas inlet side as a negative electrode,
It is characterized by a positive electrode provided on the exhaust port side. That is, the present invention has experimentally found that many flakes tend to occur near the positive electrode, and is therefore characterized by arranging the negative electrode side at the upper part of the reactor or at the reactive gas inlet side.

本発明け2〜10cm好ましくは3〜5cmの一定17
、’[1をへて被形成面を概略平行に配置、とされた基
板の上部、下部および中央部;周辺部での膜厚の均一性
、また膜質の均質性を促すため、赤外線ランプを被形成
面方向に設け、さらに少なくとも一ヒ方向および下方向
よシ棒状赤外線ランプを互いに90曲げて配置し、均熱
化をはかった。即ち10 c m’または電極方向K 
10−20 c mを有する巾10〜1100aの基板
の多くが、その温 ′度分布において、100〜400
°C例えば200±10°C以内好ましくは±5’0以
内としたことを特徴としている。
According to the present invention, the constant length is 2 to 10 cm, preferably 3 to 5 cm.
, ' [The upper, lower and central parts of the substrate, where the surfaces to be formed are arranged approximately parallel to each other; The infrared lamps were provided in the direction of the surface to be formed, and furthermore, at least one rod-shaped infrared lamp was bent toward the other side and downward by 90 degrees to achieve uniform heating. i.e. 10 cm' or electrode direction K
Many substrates with a width of 10 to 1100 mm and a width of 10 to 20 cm have a temperature distribution of 100 to 400 mm.
°C, for example, within 200±10°C, preferably within ±5'0.

゛に主として選択的にプラズマ放電させるとともに、反
応性気体をその空間に主として選択的に流入せしめるべ
きガイドを設けたことを特徴としている。さらに不発I
JAにおいては、かかる条件を満しながらも互いに横方
向に連結したマルチチアンバー間を基板が移動するに際
し何らの支障にならないように、電極、反応性ガスの導
入口および排気口を設け、さらに加熱赤外線を設けたこ
とを特徴としている。
The present invention is characterized in that it is provided with a guide that primarily causes selective plasma discharge and selectively causes reactive gas to primarily flow into the space. Further misfire I
In JA, electrodes, reactive gas inlets, and exhaust ports are provided so as to satisfy these conditions and not cause any hindrance when the substrate moves between the multi-chambers that are laterally connected to each other. It is characterized by the provision of heating infrared rays.

かくの如くにマルチチアンバ一方式を基本条件としてい
るため、それぞれの反応容器内での被膜の特性の向上に
加えて、チアンバー内壁に不要の反応生成物が付着する
ことを防ぎ、逆に加えて供給した反応性気体の被膜にな
る割合即ち集取効率を高めるため、チムニ−(煙突)状
に反応性気体を基板の配置されている筒状空間に設け、
基板の被形成面が実質的にチムニ−の内壁を構成せしめ
たことを特徴とするプラズマ気相反応装置に関する。
As described above, since the multi-chamber one-type system is the basic condition, in addition to improving the properties of the coating in each reaction vessel, it also prevents unnecessary reaction products from adhering to the inner wall of the chamber, and conversely, it also improves the supply. In order to increase the rate at which the reactive gas forms a film, that is, the collection efficiency, the reactive gas is provided in a chimney shape in the cylindrical space where the substrate is placed.
The present invention relates to a plasma vapor phase reactor characterized in that the surface of the substrate to be formed substantially constitutes the inner wall of a chimney.

また本発明は、反応容器を積層する半導体層の数だけ連
設したプラズマ反応用製造装置に関する。
The present invention also relates to a plasma reaction manufacturing apparatus in which reaction vessels are successively arranged in equal numbers to the number of semiconductor layers to be laminated.

従来非単結晶半導体例えばアモルファス珪素のプラズマ
気相反応において、その製造装置の放電方式は13.5
6MHz等の高周波を一対の面状の平板電極を平行平板
型電極方式として設け、その一方の電極上に被形成面を
有する基板を配置させ、基板の一生面側のみ選択的に被
膜成長をさせたものであった。さらにかかる方法におい
ては、反応性気体の導入に関しても、電極の他方よシ被
形成面に垂直方向にふき出す方式、また反応容器内に単
に反応性気体のガスを導入し、反応°容器全体に反応性
気体を充満させ、特忙反応性気体に一方方向へのガス流
を構成させることなく供給する方式が知られている。し
かしこの従来よシ知られているこれらの方式においては
、被膜の成長速度が0.1−2に秒と小さい0特に反応
性気体を反応容器内全体に充満させる方式においては、
0.1−0.45秒ときわめて小さく、加えて反応生成
物がフレーク状にチアンバー内壁に付着し、それらが基
板上に落下してピンホールの発生を誘発してしまった。
Conventionally, in the plasma vapor phase reaction of non-single crystal semiconductors such as amorphous silicon, the discharge method of the manufacturing equipment is 13.5
A high frequency such as 6 MHz is applied to a pair of planar flat plate electrodes as a parallel plate type electrode system, a substrate having a surface to be formed is placed on one of the electrodes, and a film is selectively grown only on the whole surface side of the substrate. It was something like that. Furthermore, in this method, regarding the introduction of the reactive gas, there is a method in which the reactive gas is blown out from the other side of the electrode in a direction perpendicular to the surface to be formed, and a method in which the reactive gas is simply introduced into the reaction vessel and the entire reaction vessel is A system is known in which the reactive gas is filled and the reactive gas is supplied without forming a unidirectional gas flow. However, in these conventionally known methods, the growth rate of the film is as low as 0.1-2 seconds.Especially in the method in which the entire reactor is filled with reactive gas,
The reaction time was extremely small, 0.1-0.45 seconds, and in addition, reaction products adhered to the inner wall of the chamber in the form of flakes, which fell onto the substrate and induced the generation of pinholes.

また基板を電極間に1まいのみ電極と平行に配置し、そ
の−主面上のみに半導体層を形成する。仁のため量産性
が全く十分でなく、その代表的な応用例である太陽電池
を作製した時、その製造原価は100:ff+”の基板
の大きさにて5000円をこえ、さらにその内の400
0円以上は設備償却費という全く非常識な現状であった
〇このため10cm0(7)基板の大きさでその’10
−30倍の生産性を同じ大きさの反応容器にて作製する
ための製造装置が強く求められていたQ本発明はかかる
目的を満たすためなされたものである。
Further, the substrate is arranged parallel to the electrodes only once between the electrodes, and a semiconductor layer is formed only on the main surface thereof. However, when manufacturing a solar cell, which is a typical example of its application, the manufacturing cost exceeds 5,000 yen for a substrate size of 100:ff+'', and of that, 400
It was a completely absurd situation that more than 0 yen was equipment depreciation cost.For this reason, the size of 10cm0(7) board was
- There has been a strong demand for a manufacturing apparatus that can produce products with 30 times higher productivity in the same size reaction vessel.The present invention was made to meet this objective.

半導体装置は単に真性の半導体のみではなくP型1.N
Wの半導体層をその設計事項に従って自由に重ね合わせ
て接合を有せしめ得ることがその工学的応用を広げるも
のである。
Semiconductor devices are not only intrinsic semiconductors, but also P-type 1. N
The fact that W semiconductor layers can be freely stacked and bonded according to their design expands its engineering applications.

このため、かかる異種導電型の半導体層を同一反応容器
で作ることは、その生産性が向上しても、それぞれの導
電型用の不純物が互いに半導体層内でスパッタ効果によ
シ混合してしまう。
For this reason, even if productivity is improved when semiconductor layers of different conductivity types are made in the same reaction vessel, impurities for each conductivity type will mix with each other within the semiconductor layer due to the sputtering effect. .

そのためP乳P工、Nl’iたはP工N接合を少なくと
も1つ有する半導体層を複数ff4積層するに際し、そ
の界面で接合を十分構成させようとした時、それぞれの
導電型用の反応容器′を前記したように独立分離せしめ
ることがきわめて重要である。
Therefore, when stacking multiple ff4 semiconductor layers having at least one P-type, Nl'i, or P-N junction, when trying to form a sufficient junction at the interface, it is necessary to separate the reaction vessels for each conductivity type. It is extremely important to independently separate the '' as described above.

本発明はかかる分離独立方式に加えて、さらにその不純
物の混合を排除させ、接合特性の向上を計ったものであ
る。すなわち例えば1つのP工N接合を積層して形成さ
せようとする時、第゛1の半導体層としてのP型半導体
層を形成させた場合、その半導体層の形成の際同時にこ
の不純物の吸着が反応容器の内壁また基板ホルダー表面
におきる。本発明においてはこれら基板上の被形成面以
外の壁面、表面からの不純物の再放出を防ぎ、また供給
系、排気系からの一度吸着した反応性気体の第2の半導
体層の形成に際し、離脱混入することを防ぐため、反応
容器のみではなく、反応性気体の供給系、排気系もそれ
ぞれ独立に各反応容器に対応して設けられている。また
基板ホルダーに関しても、基板のみが実質的に反応生成
物の付着被膜化がおきるように、基板の核形成面も11
1のみプラズマ化された反応性気体が導びかれるように
設けている0しかしさらにその不純物の混合の詳細検討
をずずめた結果、これだけでは不十分であシ、さらに形
成された第1の半導体層それ自体も不純物の混入源とな
り得ることが明らかになった。
In addition to such a separate and independent method, the present invention aims to improve the bonding characteristics by eliminating the mixing of impurities. That is, for example, when trying to form one P-N junction by laminating a P-type semiconductor layer as the first semiconductor layer, this impurity is adsorbed at the same time as the semiconductor layer is formed. It occurs on the inner wall of the reaction vessel or on the surface of the substrate holder. In the present invention, impurities are prevented from being re-released from walls and surfaces other than the surface on which they are formed on the substrate, and reactive gases once adsorbed from the supply system and exhaust system are released when forming the second semiconductor layer. In order to prevent contamination, not only reaction vessels but also reactive gas supply systems and exhaust systems are provided independently for each reaction vessel. In addition, regarding the substrate holder, the nucleation surface of the substrate is also 11°C so that only the substrate is substantially coated with reaction products.
However, as a result of further detailed study of the mixing of impurities, we found that this alone was not sufficient, and that the first It has become clear that the semiconductor layer itself can also be a source of impurity contamination.

そのためその上面に第2の半導体層を形成させようとす
る時、この下地に対し第2の半導体層を成長させ、下地
半導rt=層を反応性気体が衝突するように被形成前上
に供給され1スパツタ効果を極力さけることがきわめて
京猥であることが判明した0 即ち核形成面に対し高周波電昇が垂直にカロえられア゛
こ場合、この電界によシプラズマ化された反応性気体が
下地に強く衝突する0このため第21/;半導【ト層を
積層している時同時にその界面ではお互いが混合し合っ
てしまった。その結果従来よシ知られた平行平板型′「
u極の一方の電極面に平行に被形成面を配向させる(す
なわち電界は基板表面に垂直)と、たとえ不純物の混合
を独立反応容器方式にて排除しても十分でなくそのお互
いの混合部は約1000−200 OAもあることが判
明した。
Therefore, when trying to form a second semiconductor layer on the upper surface, the second semiconductor layer is grown on this base, and the base semiconductor rt=layer is grown on the base semiconductor rt= layer before being formed so that the reactive gas collides with the base semiconductor layer. It has been found that it is extremely important to avoid the spatter effect as much as possible when the nucleation surface is supplied. The gas strongly collides with the underlying layer.For this reason, when the 21st semiconductor layers were being laminated, they mixed with each other at the interface. As a result, the conventionally known parallel plate type
If the surface to be formed is oriented parallel to one electrode surface of the u-electrode (that is, the electric field is perpendicular to the substrate surface), even if the mixing of impurities is eliminated using the independent reaction vessel method, it will not be sufficient to eliminate the mixing of impurities with each other. It was found that there were about 1000-200 OA.

本発明はかかる欠点を防ぐため、独立分離の4ルチチア
ンバ一反応方式であって、かつそのプラズマ反応に用い
られる直流または高周波電界は被形成面tζ概略平行に
したこと、さらに反応性気体を被形成面にそって流れる
ように層流を構成して供給させ、反応性気体がチアンツ
ク−内を乱流を作って混合することを防いだ。これらの
処理に加えて、反応性気体の導入口、排気口においてガ
イドを設け、この間の基板の被形成面によシ実質的に作
られた筒状空間のみに選択的にプラズマ反応を発生せし
めることによシ]% チアンバー(反応容器)内の全空間に反応す伝り) 背が拡散し広がることを防いだものである。かかる本発
明の構造のプラズマ気相反応装置とすることによシ、形
成された不純物のそれぞれの半導体層から他の半導体層
への混合を排除し、その混合部を200−300^と約
1/1o−115にするとともに、結晶学的KP型の半
導体層上に連続してショートレンジオーダの結晶性(秩
序性)を有する真性または実質的に真性の半導体層をも
成長し得たことを特徴としている。またP1N型半導体
層を形成してPM接合を設けても、単なるオーム抵抗特
性ではなく、逆方向リークが5VKてIFA以下のダイ
オード特性を有せしめた効果を有した。
In order to avoid such drawbacks, the present invention employs an independently separated four-channel reaction system, and the direct current or high frequency electric field used for the plasma reaction is approximately parallel to the formation surface tζ, and the reactive gas is applied to the formation surface. A laminar flow was configured and supplied so as to flow along the surface, and reactive gases were prevented from creating turbulent flow within the tank and mixing. In addition to these processes, guides are provided at the reactive gas inlet and exhaust port, and a plasma reaction is selectively generated only in the cylindrical space substantially created by the surface of the substrate between these guides. This prevents the back from spreading and spreading, especially when the reaction takes place in the entire space inside the chamber (reaction vessel). By providing the plasma vapor phase reactor having the structure of the present invention, mixing of formed impurities from each semiconductor layer to another semiconductor layer is eliminated, and the mixing portion is reduced to 200-300^ and approximately 1 /1o-115, and it was also possible to grow an intrinsic or substantially intrinsic semiconductor layer having short range order crystallinity (order) continuously on a crystallographic KP type semiconductor layer. It is a feature. Furthermore, even when a P1N type semiconductor layer was formed and a PM junction was provided, it had the effect of providing not just ohmic resistance characteristics but diode characteristics with reverse leakage of 5VK and less than IFA.

かくすることによシ、その接合またその近傍に集中して
いる再結合中心の密度を十分小さくさせることができた
。即ち再結合中心は不純物の混合によりアクセプタ、ド
ナーにならない■価の不純物とV価の不純物が相互作用
して深いトラップレベルを作るが、かかるトラップセン
タ(再結合中心)を混合部の厚さをうずくすることによ
シ少なりシ、また結晶学的忙成長させることにより、′
に性半導体の不対結合手の存在濃度を従来の10〜TL
Ocmより約V100の10〜′クーノ ’No cmにしたことを特徴と17でいる。
By doing so, it was possible to sufficiently reduce the density of recombination centers concentrated at or near the junction. In other words, the recombination center does not become an acceptor or donor due to the mixing of impurities.I-valent impurities and V-valent impurities interact to create a deep trap level, but such trap centers (recombination centers) are By tingling, it is possible to reduce the amount of light, and by growing crystallographically,
The concentration of dangling bonds in a semiconducting semiconductor is reduced from the conventional 10 to TL.
It is 17 in that it is about 10~'Cuno'No cm which is about V100 from Ocm.

以下に本発明の実施例を図面に従って説明する。Embodiments of the present invention will be described below with reference to the drawings.

実施例1 第1図に従って本発明のプラズマ気相反応装置の実施例
をN’Q’+明する。
Example 1 According to FIG. 1, an example of the plasma vapor phase reactor of the present invention will be explained.

この図面けP工接合、N工接合、PN接合、P工IT接
合、P工N工P接合、N工PIN接合またけP工HP工
N■・・PIN接合等の基板上の半導体に異種導電型ま
たは同梱導電型でありながらも形成される半導体の主成
分または化学量論比の異なる半導体層をそれぞれの半導
体層をその前の工程において形成された半導体層の影響
を受けることを防ぐため、前の半導体層を形成した反応
容器に連設した他の独立した反応容器で第9の半導体層
を形成して、前の半導体層上に積層して接合を作るとと
もに、さらに多層に自動かつ連続的に形成するための装
置である。
This drawing shows P-joints, N-junctions, PN junctions, P-IT junctions, P-N-P junctions, N-PIN junctions, P-HP HP-N... Preventing semiconductor layers of different conductivity types or bundled conductivity types but with different main components or stoichiometric ratios from being influenced by semiconductor layers formed in the previous process. Therefore, a ninth semiconductor layer is formed in another independent reaction vessel connected to the reaction vessel in which the previous semiconductor layer was formed, and is laminated on top of the previous semiconductor layer to form a bond. It is also a device for continuous formation.

図面においては特K PIN接合を構成する3つのPl
 工およびN型の半導体層を積層して形成する第1およ
び第2の予備室を有するマルチチアンパー(ここでは3
つの反応容器)方式のプラズマ気相反応装置の装置例を
示す。
In the drawing, the three PIs constituting the special K PIN junction are shown.
A multi-channel amper (in this case, a 3-channel
An example of a plasma gas phase reactor using the two reaction vessels method is shown below.

図面における系I、 II、Mは3つの各反応容器(6
) 、 (’7) 、 (8)を有し、それぞれ独立し
て反応性気体の導入手段0*、0→、α呻と排気手段(
、’J I H。
Systems I, II, and M in the drawings represent three reaction vessels (6
), ('7), and (8), each having independently reactive gas introduction means 0*, 0→, α and exhaust means (
, 'J I H.

に)とを有し、反応性気体が供給系または排気系から逆
流または他の系からの反応性気体の混入を防いでいる。
) to prevent reactive gases from flowing back from the supply system or exhaust system or from mixing with reactive gases from other systems.

仁の装置は入口側には第1の予備室(5)が設けられ、
とびら0りよシ基板ホルダ(ホルダともいうX74)K
基板(4)、(j)を挿着し、この予備室に配置させた
。この被形成面を有する基板は被膜形成を行なわない裏
面を互いに接し、2xlOC!m好ましくは3−5 c
 mの間隙を有して林立させている。この間隙は基板の
反応性気体の流れ方向の長さが10cm、 15cm、
 20cmと長くなるにつれて、3−40 Tn、 4
−56 m、 □ Qmと広げた。さらにこの第1の予
備室(5)を真空ポンプ(35)Kてバルブ(34)を
開けて真空引をした。この後予め真空引がされている反
応容器(6)、 (7) 、 (8) Kゲート弁(4
4)を開けて基板およびホルダを移した。例えば予備室
(5)より容器(6)K移し、さらにゲート弁04)を
閉じることにより移動させたものである。この時反応容
器(6)K保持されていた基板(メは反応容器筒に、ま
た反応容器(〕)K保持されていた基板(2)は反応容
器(8) K%また反応容器(8)K保持されていた基
板は第2の出口側の予備室(9)に同時にゲート弁(4
5)α6)0りを開けて移動させた。
Jin's device has a first preliminary chamber (5) on the entrance side,
Door 0 board holder (also called holder X74) K
Boards (4) and (j) were inserted and placed in this preliminary chamber. The substrates having this surface to be formed are brought into contact with each other with their back surfaces on which no film is formed, and 2xlOC! m preferably 3-5 c
They are grown in a forest with a gap of m. The length of this gap in the flow direction of the reactive gas of the substrate is 10 cm, 15 cm,
As the length increases to 20 cm, 3-40 Tn, 4
-56 m, expanded to □ Qm. Further, this first preliminary chamber (5) was evacuated by using a vacuum pump (35)K and opening a valve (34). After this, the reaction vessels (6), (7), (8) K gate valves (4) which have been evacuated in advance
4) was opened and the substrate and holder were transferred. For example, the container (6)K is moved from the preliminary chamber (5), and the container is further moved by closing the gate valve 04). At this time, the substrate held in the reaction vessel (6) K (Me is in the reaction vessel cylinder, and the reaction vessel ()) The substrate (2) held in K is in the reaction vessel (8) K% Also, the reaction vessel (8) The substrate held in K is simultaneously placed in the preliminary chamber (9) on the second outlet side by the gate valve (4).
5) α6) Opened and moved.

)   2 第2の予備室に移された基板Vよゲート弁(4’i’l
が閉じられた後01)より窒素が導入されて大気圧にさ
れ、(4,3)のとびらより外に出した。
) 2 Gate valve (4'i'l)
After the chamber was closed, nitrogen was introduced from 01) to bring it to atmospheric pressure, and it was let out through the door at (4, 3).

即ちゲート弁の動きはとびら(42)、 (43)が大
気圧で開けられた時はゲート弁(44) 7 (45)
、 (46) 、 (47)は閉じられ、各チアンパー
においてはプラズマ気相反応が行なわれる。また逆にと
びら(42)(43)が閉じられていて予備室(5) 
、 (9)が十分真空引された時は、ゲート弁(44)
 (45) (46) (4つが1H1722 き、各チアンバーの基板、ホルダは隣シのチアンバーに
移動する機構を有している。
In other words, the movement of the gate valve is the door (42), and when (43) is opened at atmospheric pressure, the gate valve (44) 7 (45)
, (46), and (47) are closed, and a plasma gas phase reaction is performed in each chamber. Also, the doors (42) and (43) are closed and the preliminary room (5) is closed.
, When (9) is sufficiently evacuated, the gate valve (44)
(45) (46) (There are four chambers, and each chamber has a mechanism for moving the substrate and holder to the adjacent chamber.

系■における第1の反応容器(6)でのP型半導体層を
形成する場合を以下に記す。
The case of forming a P-type semiconductor layer in the first reaction vessel (6) in system (2) will be described below.

反応系■ (反応容器(6)を含む)は10〜10to
rr好ましくはO,01xltorr例えば0.1tO
rrとした。
Reaction system ■ (including reaction container (6)) is 10 to 10 to
rr preferably O, 01xltorr for example 0.1tO
It was set as rr.

反応性気体は珪化物気体09に対してはシラン(Sin
Hz−uz n2149K 811Q、ジクロールシラ
ン・(Efi邸υ、トリクロールシラン(ETiH[1
,)、四フッ化珪素(81F、)等があるが、取扱いが
容易なシランヲ用いた。価格的にはジクロールシランの
方が安価であシ、これを用いてもよい。
The reactive gas is silane (Sin) for silicide gas 09.
Hz-uz n2149K 811Q, dichlorosilane (Efi υ, trichlorsilane (ETiH[1
, ), silicon tetrafluoride (81F, ), etc., but silane, which is easy to handle, was used. Dichlorosilane is cheaper and may also be used.

本実施例のB i X O/−X (0< X< 1)
を形成するため炭化物気体f2)に対してはメタン(c
9を用いたOCへのような炭化物気体であっても、また
四塩化炭素(001,、)のような塩化炭素であっても
よい。
B i X O/-X (0<X<1) of this example
For carbide gas f2), methane (c
It may also be a carbide gas such as OC using 9 or a carbon chloride such as carbon tetrachloride (001,).

炭化珪素(sizCd、 0< x<1)に対しては、
P型の不純物としてボロンを水素にて2000I’FM
 K希釈されたジボランよシ(ハ)よシ供給した。また
ガリュームをTMG (()a COH;)、)によF
) 10 A−9X10 amの濃度になるように加え
てもよい。
For silicon carbide (sizCd, 0<x<1),
Boron as a P-type impurity with hydrogen at 2000I'FM
K-diluted diborane was supplied. Also, use TMG (()a COH;),) to F
) 10 A-9×10 am may be added.

キャリアガス(39)は反応中tよ水素(H,)を用い
たが、反応開始の前後は窒素(Nj)を液体窒素によシ
利用した。これらの反応性気体はそれぞれの流量計(3
段およびパルプ(3つをへて、反応性気体の導入口07
)Jニジ高周波電源の負電極(6ツをへて反応容器(6
)に供給された。反応性気体は(10)のガイドをへて
筒状空間を構成する基板(1)およびホルダ(14〕内
に導入され、負電極(61)と正電極(51)間を電気
エネルギ例えば13.56MHzの高周波エネルギを加
えて反応せしめ、基板上に反応生成物を被膜形成せしめ
た。
Hydrogen (H, ) was used as the carrier gas (39) during the reaction, but nitrogen (Nj) was used instead of liquid nitrogen before and after the start of the reaction. These reactive gases are separated by their respective flow meters (3
stage and pulp (through the three, reactive gas inlet 07
) Connect the negative electrode (6) of the high frequency power supply to the reaction vessel (6).
) was supplied. The reactive gas passes through the guide (10) and is introduced into the substrate (1) and holder (14) that constitute a cylindrical space, and is transferred between the negative electrode (61) and the positive electrode (51) by applying electrical energy, for example, 13. A reaction was caused by applying high frequency energy of 56 MHz to form a film of the reaction product on the substrate.

基板け100−40060例えば200°a VC赤外
線ヒータ(1ηθ4によシ加熱した。
Substrate 100-40060 was heated, for example, by a 200° a VC infrared heater (1ηθ4).

この赤外線ヒータは赤外線イメージ炉ともいい、棒状を
有するため上方のヒータと下方のヒータとが互いに直交
する方向に配置して、この反応容器内における特に筒状
空間を200±XOa好ましくは±60以内に設置した
。このヒータは上側または下側のみでは反応性気体の流
れ方向に200−120’Oとso’aをも不均一を生
じ、全く実用にならなかった。また互いに直交させるこ
とによシ、基板間の温度分布も±xob以内とすること
ができた。この後、前記したが、この容器に前記した反
応性気体を導入し、さらK 1O−50Wに高周波エネ
ルギα◆を供給してプラズマ反応をおこさせた。
This infrared heater is also called an infrared image furnace, and since it has a rod shape, the upper heater and the lower heater are arranged in directions orthogonal to each other, and the cylindrical space in this reaction vessel is preferably within 200±XOa, preferably within ±60. It was installed in This heater caused non-uniformity of 200-120'O and so'a in the flow direction of the reactive gas when used only on the upper side or the lower side, so it was not practical at all. Furthermore, by making them perpendicular to each other, the temperature distribution between the substrates could be kept within ±xob. Thereafter, as described above, the above-mentioned reactive gas was introduced into this container, and high-frequency energy α◆ was further supplied to K 1O-50W to cause a plasma reaction.

かくしてP型半導体層はB、F1a i HQ= 0.
5%。
Thus, the P-type semiconductor layer has B, F1a i HQ=0.
5%.

OH〆(13i H4+C鴨・0.5の条件にて、この
反応系■て約100大の厚さを有する薄膜として形成さ
せた□ F!g =2−0eVe−:lXl0 間X1
0 (’L6Q’テあツタ〇従来炭化珪素は一般に珪素
のみに比べて大き−な高周波エネルギを必要とする。そ
のため、電界が被形成面に垂直方向の場合、被形成面に
設けられた透明導電膜(工Toまたは酸化スズの600
−800^の電極用桧膜)はスパッタされて、酸化2 
スズが金属スズに変わって透明でなく白濁しゃすい。
A thin film having a thickness of about 100 mm was formed using this reaction system (1) under the conditions of OH〆 (13i H4 + C) and 0.5.
0 ('L6Q' Tatsuta〇Conventional silicon carbide generally requires larger high-frequency energy than silicon alone. Therefore, when the electric field is perpendicular to the surface to be formed, transparent Conductive film (600% of tin oxide or tin oxide)
-800^ cypress film for electrode) is sputtered and oxidized with 2
The tin turns into metallic tin, making it cloudy instead of transparent.

しかし本発明の実施例に示される如く、プラズマ電界を
被形成面に概略平行にすると、この電界による反応生成
物は表面にそって移動するため、スパッタ効果による白
濁化は3O−5ffW加えても見られず、垂直電界の場
合がト5Wが限界だったことに比べて、特性歩留シおよ
び製造歩留りを向上させた。
However, as shown in the embodiments of the present invention, when the plasma electric field is made approximately parallel to the surface to be formed, the reaction products due to this electric field move along the surface, so that clouding due to the sputtering effect can be prevented even when 3O-5ffW is added. Compared to the vertical electric field case where the limit was 5W, the characteristic yield and manufacturing yield were improved.

基板は導体基板(ステンレス、チタン、窒化チタン、そ
の他の金属)、半導体(珪素、炭化珪素、ゲルマニュー
ム)、絶縁体(アルミナ、ガラス、有機物質)または複
合基板(ガラス絶縁基板上に酸化スズ、工To等の導電
膜が単層またはITO上K ElnOLが形成された2
層膜が形成されたもの、絶縁基板上に選択的に導体電極
が形成されたもの、絶縁基板上KPまたはN型の半導体
が形成されたもの)を用いた。本実施例のみならず本発
明のすべてにおいてこれらを総称して基板という。もち
ろんこの基板は可曲性であってもま次固い板であっても
よい。
Substrates are conductor substrates (stainless steel, titanium, titanium nitride, and other metals), semiconductors (silicon, silicon carbide, germanium), insulators (alumina, glass, organic materials), or composite substrates (tin oxide, engineered, etc. on glass insulating substrates). A single layer of conductive film such as To or K ElnOL formed on ITO2
A layer film was formed, a conductor electrode was selectively formed on an insulating substrate, and a KP or N type semiconductor was formed on an insulating substrate). These are collectively referred to as a substrate not only in this embodiment but also in all of the present invention. Of course, this substrate may be a flexible or rigid plate.

かくして1−f5分間グ2ズマ反応をさせて、P型不純
物としゝ7ヲr「ボームが添加された炭化珪素膜を作製
した。さらにこの第1の半導体層上に基板を前記した操
作順序に従って第2の反応容器())K移動し、ここで
真性の半導体層を約6000^の厚さに形成させた。
In this way, a gamma reaction was allowed to occur for 1-f5 minutes to produce a silicon carbide film doped with 70% Bohm as a P-type impurity.Furthermore, a substrate was placed on this first semiconductor layer according to the above-described operation sequence. A second reaction vessel (2) was moved, in which an intrinsic semiconductor layer was formed to a thickness of about 6000^.

すなわち第1図における反応系Hにおいて、半導体の反
応性気体としてシランを(ハ)よυ、また水素等のキャ
リアガスを必要に応じてψ)f?4よシ供給して、一対
を構成する電極(I卯])Kて系■と同様に高周波1:
L澱(トンより13.56MHzの高周波エネルギを供
給した。基板は250″Oにヒータ0多(1埠によシ加
熱した。反応性気体Qま基&(2)の被形成面にそって
上方より下方に流れ、真空ポンプ(3’7)K至る0系
llにおいて◇りの出口側よシみたたて断面図を第2図
シζ示す。
That is, in the reaction system H in FIG. 1, silane is used as a reactive gas for the semiconductor (c) υ, and a carrier gas such as hydrogen is used as necessary ψ)f? 4 and supply a pair of electrodes (I) to the high frequency 1 similar to system ①:
High-frequency energy of 13.56 MHz was supplied from L lees (Ton). The substrate was heated to 250" O with a heater (1 wafer). Reactive gas Q was applied along the surface on which the group & (2) was formed. Figure 2 shows a cross-sectional view of the 0 system 11, which flows from the top to the bottom and reaches the vacuum pump (3'7)K, viewed from the outlet side.

第2図を概説する。Figure 2 is outlined.

第2図において反応容器(1)はのぞき窓←8)電波漏
えい防止用銅網09)、裏f旧でマイクロ波供給用の石
英窓(55)導波管ω9.さらにマ・tクロ波またはミ
リ波用電源Qつを具備して(へる。Ti、板(2)の被
形成面にそって平行に反応性気体い)、東の、(ハ)お
よび高周波θりの電界が配されるように設けである。
In Fig. 2, the reaction vessel (1) has a peephole ←8) copper mesh 09) for preventing radio wave leakage, a quartz window (55) for supplying microwaves on the back side, and a waveguide ω9. Furthermore, it is equipped with Q power supplies for macrowaves or millimeter waves (H, Ti, reactive gas in parallel along the formed surface of the plate (2)), east, (C) and high frequency. It is provided so that an electric field of θ is distributed.

さらに高周波に加えて1GHz以上の周波数例えば2.
45GHzのマイクロ波が供給されている0第2図にお
いて、反応性気体は(66)よシ導入され、石英管導入
口より網状または多孔状の電極(6″Qをへて導出させ
た0反応性銀体の導出口(I11基板(2)、ホルダ(
’74)、排気口Q9、一対の電極(67) (68)
の相関関係については、第3図にさらにその斜視図(前
手分を切断しである)で示している。
Furthermore, in addition to high frequencies, frequencies of 1 GHz or higher, such as 2.
In Figure 2, where a 45 GHz microwave is being supplied, the reactive gas is introduced through the quartz tube (66), and the reactive gas is led out through the quartz tube inlet through a mesh or porous electrode (6''Q). Outlet of silver body (I11 board (2), holder (
'74), exhaust port Q9, pair of electrodes (67) (68)
The correlation is further shown in a perspective view (cut away from the front) in FIG.

即ち、第3図において基板(2)は裏面を互いに合せて
さしこみ式((なったホルダ(’74)K垂直方向(鉛
直方向)に互いに一定の間隙例えば3cmにて平行に配
置されている。ホルダは石英よシなシ、上側に円板状の
ディスクとこれに連結した基板用みぞ(94)を有して
いる。ディスクは4つのサポータ(so) (ad)に
よシ空間に保持され、サポータ(so) (sd)は軸
(’79) (’7ゐの回転に従って2       
   2 回転し、その結果ディスクを3−10回/分の速度で回
転し、反応性気体の均質化を促進させている゛。
That is, in FIG. 3, the substrates (2) are placed in parallel with each other with a constant gap of 3 cm, for example, in the vertical direction (vertical direction) with their back surfaces aligned with each other. The holder is made of quartz and has a disk-shaped disk on the upper side and a substrate groove (94) connected to the disk.The disk is held in the space by four supports (so) (ad). , the supporter (so) (sd) rotates 2 according to the rotation of the axis ('79) ('7゜
2 rotations, thereby rotating the disk at a speed of 3-10 times per minute to promote homogenization of the reactive gases.

反応性気体は導出口01よシ1〜3mmの穴c73)を
へて網状Ml極(穴約ト10mm ) (6りをへて、
下方向にふき出させている。ホルダのガイドe10)に
よシ反応性気体の(80)方向への放出を防ぐため、(
81)の間隙は1cm以下好ましくはSih−5mmと
した。そして反応性気体は基板(2)(2)の被形成面
および基板(2)をたてるためのみぞ(95)を保持す
K 1r4状に流さぜた0石英の側壁(96)はみぞ(
95)よシ外側K 10−20mm 離れて設け、反応
性気体の側壁(96)でのみだれの発生を防ぎ、そのこ
とによシ基板(2)の端部での被膜の膜厚の均一性をよ
シ促進させた。
The reactive gas passes through the outlet port 01, a hole c73 with a diameter of 1 to 3 mm, and a reticular Ml electrode (with a hole diameter of approximately 10 mm).
It's blowing out downwards. To prevent the release of reactive gas in the (80) direction, the holder guide e10) is
81) The gap was 1 cm or less, preferably Sih-5 mm. The reactive gas is then flowed into the formation surface of the substrate (2) (2) and the side wall (96) of 0 quartz that holds the groove (95) for standing up the substrate (2).
95) The outer side K is placed 10-20 mm apart to prevent the reactive gas from sagging on the side wall (96), thereby improving the uniformity of the film thickness of the coating at the edge of the substrate (2). It has been promoted.

また排気系に関しても、(8荀からの反応性気体の流入
を少なく L、(85)を選択的K u、l−させるた
め、ガイド(’7m)と基板下端との間隙を1cm以下
に合せて設けた。即ち(82) (84)のガス流のコ
ンダクタンスを(8り碑5)の約115以下好ましくは
の0−17100にすることにより、筒状空間に選択的
に反応性気体を導き入れた。正電極(68)と基板下端
との距離はガイドの高さを調節して設けた。
Regarding the exhaust system, the gap between the guide (7 m) and the bottom edge of the substrate was adjusted to 1 cm or less in order to reduce the inflow of reactive gas from the That is, by setting the conductance of the gas flow (82) and (84) to about 115 or less, preferably 0-17100, the reactive gas is selectively introduced into the cylindrical space. The distance between the positive electrode (68) and the lower end of the substrate was set by adjusting the height of the guide.

さらに負電極(6’/lと基板上端即ちディスク(/4
)との距離も同様にガイド(’10)Kよシ調節した。
Furthermore, the negative electrode (6'/l) and the upper end of the substrate, that is, the disk (/4
) and the guide ('10) K was adjusted in the same way.

第3図より明らかな如く、電極はその外周辺側を石英の
ガイド(’yO)、上ぶた(93)、ガイド(7υ、下
ぶた(94)によって囲まれておシ、電極とチアンバー
(q芋にステンレスチアンバーンの内!糸と梃・t の寄生溶イを防止に務めた。さらに反応性気体の導入口
(68)の内径と負電極が概略同一の大きさを有し、ま
た排気口00の内径と正電極とが概略同一の大きさを有
するため、高周波放電を行なうと、この筒状空間即ち反
応性気体の被形成面にそって流れて空間を冷え的にプラ
ズマ放電させている。その結果、反応性気体のプラズマ
化率がきわめて大きくなシ、ひいては反応容器(ペルジ
ャー)の内壁に過剰の反応生成物がピンホール発生の原
因となるフレーク状に付着してしまうことを防ぐことが
できた。
As is clear from Fig. 3, the electrode is surrounded on its outer periphery by a quartz guide ('yO), an upper lid (93), a guide (7υ), and a lower lid (94). This was done to prevent parasitic welding between the thread and the lever inside the stainless steel chain burner in the potato.Furthermore, the inner diameter of the reactive gas inlet (68) and the negative electrode are approximately the same size, and the exhaust Since the inner diameter of the opening 00 and the positive electrode have approximately the same size, when high-frequency discharge is performed, the reactive gas flows along this cylindrical space, that is, the surface on which reactive gas is formed, causing a cold plasma discharge in the space. As a result, the plasma conversion rate of the reactive gas is extremely high, and this prevents excessive reaction products from adhering to the inner wall of the reaction vessel (Pelger) in the form of flakes, which can cause pinholes. I was able to do that.

以上の如き第3図の構成に加えて、その番号が対応した
第2図においては、赤外線ランプ吟dが上方向、下方向
に設けられ、基板の均質化を促進させている。
In addition to the structure of FIG. 3 as described above, infrared lamps d are provided in the upper and lower directions in FIG. 2, whose numbers correspond to each other, to promote homogenization of the substrate.

第3図の構成は泥1図における系1.UKおける反応容
器(6) (8)での電極、基板、ホルダ、反応性似体
層出口、排気口においても同様の構成を有せしめた。か
くして第3図において基板および基板ホルダは何らの支
障なく(’7’7)の系Iの方向よシL・I ′)、 
’t ’l (’7E])の方向の系夏の方向に移動さ
せることができた。
The configuration in Figure 3 is system 1 in Figure 1. The electrodes, substrates, holders, reactive analogue layer outlets, and exhaust ports in the reaction vessels (6) and (8) in the UK had similar configurations. Thus, in FIG. 3, the substrate and substrate holder can be moved in the direction of system I ('7'7) without any hindrance (L·I'),
It was possible to move the system in the direction of 't'l ('7E]) in the summer direction.

第2図におけるIGHz以上の周波数のマイクロ波の効
果に関しては、不発門人の出願になる特許願5’/−1
2604フe51.7.19出願)に詳細が示されてい
る。
Regarding the effect of microwaves with a frequency higher than IGHz in Figure 2, patent application 5'/-1 filed by an unsuccessful student
2604 f e51.7.19 application).

図面では2500 において3ヤ秒を高周波電界を20
Wとしシランをs o c c/9加えると得ることが
できた。イ゛52−として従来の平行平板型のN極方式
において0.1〜1鵡りに比べて、同−反応容器庫とす
ると6倍になジ、合計48倍の多量生産が可能となった
。また従来50cmを作つ(′1する空間においては、
20cmX50cmの基板を間隙5cmとし、20配列
同時に可能となシ、V−形成面積は’L  L   ” 実質的K 20X50X20=2XIOamと同時に8
倍にすることができ、電極間距離は従来の4cmよ92
5〜27cm[なったため、反応性気体のイオン化率も
向上し、被膜へ−L娃雇し4彰秒を74/ることができ
るため、結果として64倍の成長速度を実質的に有する
きわめて理想的な多量生産方式であることがわかった。
In the drawing, 3 YA seconds at 2500 Hz is equivalent to 20 yA high frequency electric field.
It could be obtained by adding W and silane at s.o.c.c./9. Compared to the conventional parallel plate N-pole type N-pole method, which requires 0.1 to 1 ounces, using the same reaction container warehouse allows for 6 times as much production, making it possible to produce a total of 48 times as much. . In addition, in the conventional space where 50cm is made ('1),
With a 20cm x 50cm substrate with a gap of 5cm, 20 arrays can be arranged at the same time, and the V-formation area is 'LL''.
The distance between the electrodes can be doubled from the conventional 4cm to 92cm.
5 to 27 cm [As a result, the ionization rate of the reactive gas is also improved, and it is possible to apply 4 liters to the film in 74 seconds, resulting in an extremely ideal growth rate that is substantially 64 times faster. It turned out to be a mass production method.

かくして形成された半導体層は、プラズマ状態のXEt
*が長いため、先広導度も2×1047X10(何4″
、喧伝導#:、3X10″〜lXl0’(cc@−′を
有していた。
The semiconductor layer thus formed is made of XEt in a plasma state.
Since * is long, the tip conductivity is also 2×1047×10 (how many 4″
, had a conduction #:, 3X10''~lXl0'(cc@-'.

またかくして工型半導体層を系■にて約500OAの厚
さに形成させた後、基板は前記した操作に従って系■の
反応容器(8)K移され、N型半導体層が形成された。
After forming a semiconductor layer with a thickness of about 500 OA in System 1, the substrate was transferred to a reaction vessel (8)K in System 2 according to the above-described operations, and an N-type semiconductor layer was formed.

このN型半導体層には、第1図においてフオスヒンをP
 H/s i !(,21,0%としく31)よシまた
シランを(30)よシ、またキャリアガスの水累を(→
よfi81)f、/H,・5oとして供給し系■と同様
にして200Åの厚さKN型の微結晶性または繊維構造
を有する多結晶の半導体1層を形成させたものである。
In this N-type semiconductor layer, phosphine is added to P as shown in FIG.
H/s i! (, 21, 0% 31), add silane (30), add carrier gas water (→
A single layer of a polycrystalline semiconductor having a KN-type microcrystalline or fibrous structure with a thickness of 200 Å was formed in the same manner as in system (2) by supplying yofi81) f, /H, and .5o.

その他反応装置については系■と同様である。Other reactor equipment is the same as for system ①.

かかる工程C後、第2の予備室(9)よシ外にP工N接
合を構成して出された基板上にアルミニューム電極を真
空蒸着法によシ約1μの厚さに作シ、ガラス基板上K 
(ITO+5nOJ表面電極−(P工N半導体)(Al
裏面電極)を構成させた。
After this step C, an aluminum electrode is formed to a thickness of about 1 μm by vacuum evaporation on the substrate which is taken out of the second preparatory chamber (9) to form a P-N junction. On glass substrate
(ITO + 5nOJ surface electrode - (P-N semiconductor) (Al
A back electrode) was constructed.

その光電変換装置としての特性は7桐豪平均8%をlo
cm’の基板でAMPαoomw/am) Kて真性効
率特性として有し、ハイブリッド型にした15cmX4
0cmの基板においても、6−J7$i真性効率で得る
ことができた。この効率の向上は光が入射する(III
のP工接合がきわめて簡約に構成され)またアモルファ
ス半導体またはセミアモルファス半導体等の非単結晶半
導体においても、P型半導体層上に工型半導体層を成長
積層させたことによるもので、また開放電圧は0.88
−0.9vであったが、短絡電流は2 C□22mIy
’cm’と大きく、またFFも0.フH078と大きく
、PIN型の半導体層内部における再結合中心の密度が
従来の方法に比べ]、/10−1150 Kなったこと
による電流増加が大きな特性改良につながったものと推
だされる。
Its characteristics as a photoelectric conversion device are 8% lo
cm' substrate has AMPαoomw/am) K as an intrinsic efficiency characteristic, and is a hybrid type 15cm×4
Even on a 0 cm substrate, an intrinsic efficiency of 6-J7$i could be obtained. This efficiency improvement is due to the incident light (III
In non-single-crystal semiconductors such as amorphous or semi-amorphous semiconductors, this is due to the fact that a p-type semiconductor layer is grown and laminated on a p-type semiconductor layer, and the open-circuit voltage is 0.88
-0.9v, but the short circuit current was 2C□22mIy
It is large at 'cm' and the FF is 0. The density of recombination centers inside the PIN type semiconductor layer is /10-1150 K compared to the conventional method, which is considered to be the reason for the large improvement in characteristics.

かくの如く本発明のプラズマ反応装置は形成される4!
:導体において生産性を30−70倍も向上させ、また
特性も従来の5−896の変換効率に比べ30%も向上
させるきわめて独f;jJ的なものである0 実施例2 この実施例は実施例1の変形であ)、第2図に対応した
図面を第4図に示しである。その他は第1図〜第3図と
同様である。
The plasma reactor of the present invention is thus formed 4!
:This is a very unique method that improves the productivity of conductors by 30-70 times and also improves the characteristics by 30% compared to the conventional 5-896 conversion efficiency.Example 2 This example is This is a modification of Embodiment 1), and a drawing corresponding to FIG. 2 is shown in FIG. Other details are the same as in FIGS. 1 to 3.

第4図は工型半導体層を形成する1’5p−2反応容器
のたて断面[ア1であシ、図面において反応性気体やQ
p′I)PDは導入口(66)をへて導出口θ櫓よシ横
方向に噴き出されている。また排出口も?、])をへて
(/ a)よジロータリーポンプ(3’/)に至ってい
る。
Figure 4 shows a vertical cross section of a 1'5p-2 reaction vessel in which a semiconductor layer is formed.
p'I) PD is ejected laterally from the inlet (66) to the outlet θ tower. Also, the outlet? , ]) and then (/a) to the di-rotary pump (3'/).

基板(2)は鉛直方向に立てて林立させ、ホルダ(’7
4)により空間に保持されている。反応性気体はガイド
(’70)(’71)により4:/湧1jL:D筒状空
間に選択的に流れるようにしている。高周波W、vP、
(Iiは負電極(6η正電極c7りを有し、赤外糾2ン
プは(]り、θうと上下に設けられ、均熱化を促進させ
た。
Stand the board (2) vertically and place it in the holder ('7
4) is held in space by The reactive gas is made to flow selectively into the cylindrical space 4:/1jL:D by guides ('70) ('71). High frequency W, vP,
(Ii has a negative electrode (6η) and a positive electrode (c7), and infrared heating lamps are provided above and below (), θ) to promote heat uniformity.

この実施例においては、基板(2)ホルダ(7穀の系■
〜■への移動が容易でちるというQ、′f注を有する。
In this embodiment, the substrate (2) holder (7 types of
It has Q, 'f Note that it is easy to move to ~■.

しかし反応性気体が温度の上昇気流によシ上方に多く流
れ、基板の上側が浮くなシやすい。このため基板を(四
〜e21)の方向に配置させることが必要になるが、こ
の作業が構造上困難であるという欠点を有していた。ま
た反応性気体の飛翔距離が基板(2)の横方向であシ、
長いため反応性気体の導入口側と排出口側とで得られた
電気11・1性にバラツキが発生してしまい、多量生産
には実施例1と同様すぐれたものであったが、高品質の
特性を大面積に均質に得るという点では欠点を有してい
た。
However, a large amount of the reactive gas flows upward due to the rising temperature, and the upper side of the substrate tends to float. For this reason, it is necessary to arrange the substrate in the direction (4 to e21), but this has the disadvantage of being structurally difficult. In addition, if the flying distance of the reactive gas is in the lateral direction of the substrate (2),
Because of the long length, there were variations in the electrical 11.1 characteristics obtained between the reactive gas inlet and outlet sides, and although it was excellent for mass production as in Example 1, it was not suitable for high quality. It has a drawback in that it cannot uniformly obtain the same characteristics over a large area.

実施例3 第5図は本発明の他の実施例を示す。Example 3 FIG. 5 shows another embodiment of the invention.

第5図(4)は実施例1の第3図に対応して図面の概要
を示したものである。第5図(4)において反応性気体
の導入口(66)よル0呻、負電極(6′Qをへて排気
口Q1)、正電極(6日)、排気系(74)K至るが、
基板(2)はテーパ状を有し、基板の導入口側よシー排
気口側に向ってせまくなシ、その形成される膜の均一化
をさらに促進させたものである。
FIG. 5(4) shows an outline of the drawing corresponding to FIG. 3 of the first embodiment. In Figure 5 (4), the reactive gas inlet (66) leads to the negative electrode (6'Q to the exhaust port Q1), the positive electrode (6th), and the exhaust system (74) K. ,
The substrate (2) has a tapered shape, and does not become narrower from the inlet side to the sea outlet side of the substrate, thereby further promoting uniformity of the formed film.

(A)においてはフレークが被形成面に剥土付着しやす
いため、(9)においては反応性気体の導出す11晶 口を下方向よシ璽口を上方向に設けることも可能である
In (A), the flakes tend to stick to the surface on which they are formed, so in (9), it is also possible to provide the 11 crystal opening from which the reactive gas is drawn out in the downward direction and the crystal opening in the upward direction.

かくすると、フレークが被形成面に付くことがなく、即
ちピンホールによる製造歩留シも向上し、加えて被膜の
膜質も反応性気体の流れ方向において均質な結果を得た
。しかし第1図の製造装RK比べてその生産性は約V2
になってしまった。
In this way, flakes were not attached to the surface to be formed, that is, the production yield due to pinholes was improved, and in addition, the film quality of the film was homogeneous in the flow direction of the reactive gas. However, the productivity is about V2 compared to the manufacturing equipment RK shown in Figure 1.
It has become.

以上の本発明の実施例においては、P工N接合を1つ有
するものとした。しかしP工N工P型のフォトトランジ
スタ、P工II’工N・・・@P工Nのタンデム構造の
光電変換装置等多くの応用もその半導体層の数に従って
反応容器をさらに連結すればよく、本発明の技術思想に
おいて、これらも含まれることはいうまでもない。
In the embodiment of the present invention described above, one P-N junction is provided. However, for many applications such as P-type N-type phototransistors, P-type II'-N...@P-N tandem structure photoelectric conversion devices, it is sufficient to further connect reaction vessels according to the number of semiconductor layers. , it goes without saying that these are also included in the technical idea of the present invention.

本発明において形成される非単結晶手導体被膜中の結晶
構造がアモルファスであれ多結晶であれ、その構造には
制限を受けない。本発明は形成された複数の積層された
半導体被膜がP型、N型または1型を少なくともPI、
 PMまたはN工接合をひとつ有する半導体であること
が重要である。またこの半導体としての導電特性のリー
ク特性の軽減のため、その接合面においてそれぞれを混
合させない高品質な被膜を多量生産することが大きな特
徴である。
Whether the crystal structure in the non-single-crystal conductive film formed in the present invention is amorphous or polycrystalline, there is no restriction on the structure. The present invention provides that the formed plurality of laminated semiconductor films are P type, N type or type 1, at least PI,
It is important that the semiconductor has one PM or N-type junction. In addition, in order to reduce the leakage characteristics of the conductive properties of this semiconductor, a major feature is to mass-produce a high-quality coating that does not mix each other at the bonding surface.

さらにこの珪素または炭素の不対結合手を水素によ#)
81−H%O−E Kて中和するのではなく秒 5i−01,($−01とハロゲン化物特に塩化Y気体
を用い゛て実施してもよいことはいうまでもなく、この
濃度け10原子チ以下、例えば2−5原子チが好ましか
った。
Furthermore, this dangling bond of silicon or carbon is replaced with hydrogen)
It goes without saying that instead of neutralizing with 81-H% O-E K, it may be carried out using 5i-01, ($-01) and a halide, especially Y chloride gas. Less than 10 atoms, for example 2-5 atoms, were preferred.

形成させる半導体の種類に関しては、実施例1に示した
が、■族の81、()e、 81XO7−x(0(!(
1)、El 1! G @ r−r+ (0’−X’ 
1) % 81X 8 n 7−4 (0(X (1)
のみでKなく、これ以外にGaAs、 ()aAIAg
、 BP、 Ods等の化合物半導体であってもよいこ
とはいうまでもない。
Regarding the types of semiconductors to be formed, as shown in Example 1, 81, ()e, 81XO7-x(0(!(
1), El 1! G @ r-r+ (0'-X'
1) % 81X 8 n 7-4 (0(X (1)
Not only K, but also GaAs, ()aAIAg
It goes without saying that compound semiconductors such as , BP, Ods, etc. may also be used.

本発明で形成された炭化珪素被膜に対しフォトエッチ技
術を用いて選択的KPまたはN型の不純物を混入または
拡散してPM接合を部分的に作シ、この接合を利用して
トランジスタ、ダPXN接合型の可視光レーザ、発光素
子または光電変換素子を作ってもよい。特に先入射光側
のエネルギバンドljを大きくしたヘテロ接合構造を有
するいわゆるv−N (wよりm To NhIJIJ
ovt)と各反応室にて導電型のみではなく生成物を異
ならせてそれぞれ独立して作製して積層させることが可
能になシ、工業的にきわめて重要なものであると信する
A selective KP or N-type impurity is mixed or diffused into the silicon carbide film formed by the present invention using photoetching technology to partially form a PM junction, and this junction can be used to create a transistor or a PXN. A junction-type visible light laser, light emitting device, or photoelectric conversion device may also be made. In particular, the so-called v-N (m from w
ovt) and in each reaction chamber, not only the conductivity type but also the product can be made independently and stacked, which I believe is extremely important industrially.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は本発明を実施するための半導体膜形成
用製造装置の概略を示す。 第3図は第2図の装置の一部の斜視図を示す。 第4図は第2図に対応した本発明の他の実施例である。 第5図は本発明の第3図に対応した他の実施例である。 45゛許出願人
1 and 2 schematically show a manufacturing apparatus for forming a semiconductor film for carrying out the present invention. FIG. 3 shows a perspective view of a portion of the apparatus of FIG. FIG. 4 shows another embodiment of the present invention corresponding to FIG. FIG. 5 shows another embodiment corresponding to FIG. 3 of the present invention. 45゛Applicant

Claims (1)

【特許請求の範囲】[Claims] 1.1気圧以下の減圧状態に保持された反応系における
基板上の被形成面上に、P型、1型およびN型の導電型
の非単結晶半導体層を積層して接合を構成する半導体を
形成せしめるため、P型半導体層を形成させるための反
応容器と、工型半導体層を形成させるための反応容器と
、N型半導体層を形成させるための反応容器とを具備し
、前記それぞれの反応容器には反応性気体の導入系と反
応生成物を真空排気するための排気系とを有し、前記反
応容器を互いに連設するとともに、前記反応容器の一方
の側および他方の側に第1および第2の予備室を連設し
、前記反応容器よび予備室の連設部には前記それぞれの
反応容器に導入される反応性気体がプラズマ気相反応中
に互いに混入することを防ぐゲート弁が設けられたプラ
ズマ気相反応装置において、被形成面を有する基板が互
いに概略平行に所定の間隙を有して配設せしめるととも
に、前記基板の被形成面方向に加熱源を設けたことを特
徴とするプラズマ気相反応装置。 2、特許請求の範囲第1項において、加熱源は反応容器
の上方および下方向よシ赤外線ランプにより設けられる
とともに、基板は重力方向に配設せしめたことを特徴と
するプラズマ気相反応装置。
A semiconductor in which a junction is formed by laminating non-single crystal semiconductor layers of P type, 1 type and N type conductivity on a surface to be formed on a substrate in a reaction system maintained at a reduced pressure of 1.1 atmospheres or less. In order to form a P-type semiconductor layer, a reaction vessel for forming a P-type semiconductor layer, a reaction vessel for forming a processed semiconductor layer, and a reaction vessel for forming an N-type semiconductor layer are provided. The reaction vessel has a reactive gas introduction system and an exhaust system for evacuating the reaction product, and the reaction vessels are connected to each other, and gas pipes are provided on one side and the other side of the reaction vessel. A first and a second preparatory chamber are arranged in series, and a gate is provided in the connection part of the reaction vessel and the preparatory chamber to prevent the reactive gases introduced into the respective reaction vessels from mixing with each other during the plasma gas phase reaction. In a plasma vapor phase reactor equipped with a valve, substrates having surfaces to be formed are arranged approximately parallel to each other with a predetermined gap, and a heating source is provided in the direction of the surface to be formed of the substrates. Characteristic plasma gas phase reactor. 2. A plasma vapor phase reactor according to claim 1, characterized in that the heating source is provided by an infrared lamp in the upper and lower directions of the reaction vessel, and the substrate is disposed in the direction of gravity.
JP57163730A 1982-09-20 1982-09-20 Plasma vapor reactor Granted JPS5952835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57163730A JPS5952835A (en) 1982-09-20 1982-09-20 Plasma vapor reactor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57163730A JPS5952835A (en) 1982-09-20 1982-09-20 Plasma vapor reactor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP63292203A Division JPH01157520A (en) 1988-11-18 1988-11-18 Plasma vapor reaction

Publications (2)

Publication Number Publication Date
JPS5952835A true JPS5952835A (en) 1984-03-27
JPH0436449B2 JPH0436449B2 (en) 1992-06-16

Family

ID=15779570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57163730A Granted JPS5952835A (en) 1982-09-20 1982-09-20 Plasma vapor reactor

Country Status (1)

Country Link
JP (1) JPS5952835A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60111419A (en) * 1983-10-27 1985-06-17 ア−ルシ−エ− コ−ポレ−ション Method of coating amorphous semiconductor material layer from gas in positive column of glow discharge
US4680451A (en) * 1985-07-29 1987-07-14 A. G. Associates Apparatus using high intensity CW lamps for improved heat treating of semiconductor wafers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5143718U (en) * 1974-09-27 1976-03-31
JPS5578524A (en) * 1978-12-10 1980-06-13 Shunpei Yamazaki Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5143718U (en) * 1974-09-27 1976-03-31
JPS5578524A (en) * 1978-12-10 1980-06-13 Shunpei Yamazaki Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60111419A (en) * 1983-10-27 1985-06-17 ア−ルシ−エ− コ−ポレ−ション Method of coating amorphous semiconductor material layer from gas in positive column of glow discharge
JPH0533526B2 (en) * 1983-10-27 1993-05-19 Rca Corp
US4680451A (en) * 1985-07-29 1987-07-14 A. G. Associates Apparatus using high intensity CW lamps for improved heat treating of semiconductor wafers

Also Published As

Publication number Publication date
JPH0436449B2 (en) 1992-06-16

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