JPH0436449B2 - - Google Patents

Info

Publication number
JPH0436449B2
JPH0436449B2 JP57163730A JP16373082A JPH0436449B2 JP H0436449 B2 JPH0436449 B2 JP H0436449B2 JP 57163730 A JP57163730 A JP 57163730A JP 16373082 A JP16373082 A JP 16373082A JP H0436449 B2 JPH0436449 B2 JP H0436449B2
Authority
JP
Japan
Prior art keywords
substrate
reaction
plasma
reactive gas
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57163730A
Other languages
Japanese (ja)
Other versions
JPS5952835A (en
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP57163730A priority Critical patent/JPS5952835A/en
Publication of JPS5952835A publication Critical patent/JPS5952835A/en
Publication of JPH0436449B2 publication Critical patent/JPH0436449B2/ja
Granted legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/54Apparatus specially adapted for continuous coating

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  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 本発明は基板上にP型、I型およびN型の導電
型を有する非単結晶半導体を層状に積層して形成
するに際し、それぞれの半導体層をそれぞれに対
応したプラズマ気相反応用反応容器で形成せし
め、かつそれぞれの反応容器を互いに連結して設
けることにより、外気(大気)にふれさせること
なく半導体層を形成せしめるプラズマ気相反応装
置に関する。
DETAILED DESCRIPTION OF THE INVENTION When forming non-single crystal semiconductors having P-type, I-type, and N-type conductivity on a substrate, each semiconductor layer is exposed to a plasma corresponding to each layer. The present invention relates to a plasma vapor phase reaction apparatus that is formed of gas phase application reaction vessels and that is capable of forming a semiconductor layer without being exposed to outside air (atmosphere) by connecting the reaction vessels to each other.

本発明は水素またはハロゲン元素が添加された
非単結晶半導体層、好ましくは珪素、ゲルマニユ
ーム、炭化珪素(SiCのみではなく、本発明にお
いてはSixC1-x0<x<1の総称を意味する)、珪
化ゲルマニユーム(SixGe1-x0<x<1)珪化
スズ(SixSn1-x0<x<1)であつて、この被膜
中に活性状態の水素またはハロゲン元素を充填す
ることにより、再結合中心密度の小さなPIおよ
びN型の導電型を有する半導体層を複数層形成
し、その積層境界にて接合例えばPN接合、PI接
合、NI接合またはPIN接合を形成するとともに、
それぞれの半導体層に他の隣接する半導体層から
の不純物が混入して接合特性を劣化させることな
く形成するとともに、またそれぞれに半導体層を
形成する工程間に大気特に酸素にふれさせて、半
導体の一部が酸化されることにより、層間絶縁物
が形成されることのないようにした連続生産を行
なうためのプラズマ気相反応用製造装置に関す
る。
The present invention is directed to a non-single crystal semiconductor layer to which hydrogen or a halogen element is added, preferably silicon, germanium, or silicon carbide (not only SiC, but in the present invention means the general term SixC 1-x 0<x<1). , germanium silicide (SixGe 1-x 0<x<1) and tin silicide (SixSn 1-x 0<x<1), and by filling this film with hydrogen or halogen elements in an active state, recombination can be achieved. Forming a plurality of semiconductor layers having conductivity types of PI and N type with a small center density, forming a junction such as a PN junction, a PI junction, an NI junction, or a PIN junction at the lamination boundary, and
Each semiconductor layer is formed without contaminating impurities from other adjacent semiconductor layers and deteriorating the junction characteristics, and the semiconductor layer is exposed to air, particularly oxygen, between the steps of forming each semiconductor layer. The present invention relates to a plasma gas phase applied manufacturing apparatus for continuous production in which interlayer insulators are not formed due to partial oxidation.

さらに本発明は、かかる多数の反応容器を連結
したマルチチアンパー方式のプラズマ反応装置に
おいて、一度に多数の基板を同時にその被膜成長
速度を大きくしたいわゆる多量生産方式に関す
る。
Furthermore, the present invention relates to a so-called mass production system in which a large number of substrates are simultaneously grown at a high film growth rate in a multi-chamber type plasma reactor in which a large number of reaction vessels are connected.

このため、反応性気体が反応容器内のすべてに
分散してしまうことを防ぎ、基板の被形成面を利
用して、筒状の空間に被形成面を1つの側に有す
る基板を裏面を互いに密接して、一定の距離例え
ば2〜6cm代表的には3〜4cm離して平行に配列
し、この基板が林立した筒状空間においてのみプ
ラズマ放電を行なわしめ、加えて反応性気体を選
択的に導びき、結果として反応性気体の収集効率
を従来の1〜3%よりその20〜60倍の40〜70%に
まで高めたことを特徴としている。
For this reason, the reactive gas is prevented from being dispersed throughout the reaction vessel, and by using the formation surface of the substrate, the substrates having the formation surface on one side are placed in a cylindrical space with their back surfaces mutually placed. The substrates are arranged in parallel at a certain distance, for example, 2 to 6 cm, typically 3 to 4 cm, and plasma discharge is performed only in the cylindrical space in which the substrates are arranged. As a result, the collection efficiency of reactive gases has been increased from 1 to 3% in the conventional method to 40 to 70%, which is 20 to 60 times higher.

本発明はかくの如くに反応性気体を基板が配置
されている筒状空間に林立した筒状空間に選択的
に導入せしめ、その領域に主として選択的にプラ
ズマ放電させるとともに、反応性気体をその空間
に主として選択的に流入せしめるべきガイドを設
けたことを特徴としている。さらに本発明におい
ては、かかる条件を満しながらも互いに横方向に
連結したマルチアンバー間を基板が移動するに際
し何らの支障にならないように、電極、反応性ガ
スの導入口および排気口を設け、さらに加熱赤外
線を設けたことを特徴としている。
In this way, the present invention selectively introduces a reactive gas into the cylindrical space that stands in the cylindrical space in which the substrate is arranged, selectively discharges plasma primarily in that region, and at the same time, the reactive gas is selectively introduced into the cylindrical space where the substrate is arranged. It is characterized by the provision of a guide that allows the flow to flow mainly selectively into the space. Furthermore, in the present invention, electrodes, a reactive gas inlet, and an exhaust port are provided so as to satisfy these conditions and not cause any hindrance to the movement of the substrate between the multi-umbers connected to each other in the horizontal direction. It is also characterized by the provision of heating infrared rays.

かくの如くにマルチチアンバー方式を基本条件
としているため、それぞれの反応容器内での被膜
の特性の向上に加えて、チアンバー内壁に不要の
反応性成物が付着することを防ぎ、逆に加えて供
給した反応性気体の被膜になる割合即ち集収効率
を高めるため、チムニー(煙突)状に反応性気体
を基板の配置されている筒状空間に設け、基板の
被形成面が実質的にチムニーの内壁を構成せしめ
たことを特徴とするプラズマ気相反応装置に関す
る。
Since the multi-chamber method is used as a basic condition, in addition to improving the properties of the coating within each reaction vessel, it also prevents unnecessary reactive products from adhering to the inner walls of the chamber, and conversely In order to increase the rate of formation of a film, that is, the collection efficiency of the supplied reactive gas, the reactive gas is provided in a chimney shape in the cylindrical space where the substrate is placed, so that the surface of the substrate to be formed is essentially a chimney. The present invention relates to a plasma gas phase reactor characterized in that the inner wall of the present invention comprises a plasma vapor phase reactor.

また本発明は、反応容器を積層する半導体層の
数だけ連設したプラズマ反応用製造装置に関す
る。
The present invention also relates to a plasma reaction manufacturing apparatus in which reaction vessels are successively arranged in equal numbers to the number of semiconductor layers to be laminated.

従来非単結晶半導体例えばアモルフアス珪素の
プラズマ気相反応において、その製造装置の放電
方式は13.56MHz等の高周波を一対の面状の平板
電極を平行平板型電極方式として設け、その一方
の電極上に被形成面を有する基板を配置させ、基
板の一主面側のみ選択的に被膜成長をさせたもの
であつた。さらにかかる方法においては、反応性
気体の導入に関しても、電極の他方より被形成面
に垂直方向にふき出す方式、また反応容器内に単
に反応性気体のガスを導入し、反応容器全体に反
応性気体を充満させ、特に反応性気体に一方方向
へのガス流を構成させることなく供給する方式が
知られている。しかしこの従来より知られている
これらの方式においては、被膜の成長速度が0.1
〜2Å/秒と小さい。特に反応性気体を反応容器
内全体に充満させる方式においては、0.1〜0.4
Å/秒ときわめて小さく、加えて反応生成物がフ
レーク状にチアンバー内壁に付着し、それらが基
板上に落下してピンホールの発生を誘発してしま
つた。
Conventionally, in the plasma vapor phase reaction of non-single crystal semiconductors such as amorphous silicon, the discharge method of the manufacturing equipment is to provide a pair of planar flat plate electrodes as a parallel plate type electrode system to transmit a high frequency such as 13.56 MHz, and to A substrate having a surface to be formed was placed, and a film was selectively grown only on one principal surface of the substrate. Furthermore, in this method, regarding the introduction of the reactive gas, there is a method in which the reactive gas is blown out from the other side of the electrode in a direction perpendicular to the surface to be formed, and a method in which the reactive gas is simply introduced into the reaction container, and the reactive gas is spread throughout the reaction container. It is known to fill with gas, in particular to supply reactive gases without forming a unidirectional gas flow. However, in these conventionally known methods, the film growth rate is 0.1
It is small at ~2 Å/sec. In particular, in a method in which the entire reaction vessel is filled with reactive gas, 0.1 to 0.4
In addition, reaction products adhered to the inner wall of the chamber in the form of flakes and fell onto the substrate, causing pinholes.

また基板を電極間に1まいのみ電極と平行に配
置し、その一主面上のみに半導体層を形成する。
このため量産性が全く十分でなく、その代表的な
応用例である太陽電池を作製した時、その製造原
価は10cm□の基板の大きさにて5000円をこえ、さ
らにその内の4000円以上は設備償却費という全く
非常識な現状であつた。
Further, the substrate is arranged parallel to the electrodes only once between the electrodes, and a semiconductor layer is formed only on one principal surface of the substrate.
For this reason, mass production is not sufficient at all, and when producing a solar cell, which is a typical application example, the manufacturing cost exceeds 5,000 yen for a 10 cm square substrate, and within that amount, it costs more than 4,000 yen. The current situation was completely absurd, with equipment depreciation costs.

このため10cm□の基板の大きさでその10〜30倍
の生産性を同じ大きさの反応容器にて作製するた
めの製造装置が強く求められていた。
For this reason, there is a strong need for a manufacturing device that can produce substrates with a substrate size of 10 cm square with 10 to 30 times the productivity in a reaction vessel of the same size.

本発明はかかる目的を満たすためなされたもの
である。
The present invention has been made to meet this objective.

半導体装置は単に真性の半導体のみではなくP
型、N型の半導体層をその設計事項に従つて自由
に重ね合わせて接合を有せしめ得ることがその工
学的応用を広げるものである。
Semiconductor devices are not just intrinsic semiconductors;
The fact that type and N type semiconductor layers can be freely stacked and bonded according to the design matters expands its engineering applications.

このため、かかる異種導電型の半導体層を同一
反応容器で作ることは、その生産性が向上して
も、それぞれの導電型用の不純物が互いに半導体
層内でスパツタ効果により混合してしまう。その
ためPN、PI、NIまたはPIN接合を少なくとも1
つ有する半導体層を複数層積層するに際し、その
界面で接合を十分構成させようとした時、それぞ
れの導電型用の反応容器を前記したように独立分
離せしめることがきわめて重要である。
For this reason, if semiconductor layers of different conductivity types are formed in the same reaction vessel, even if the productivity is improved, impurities for each conductivity type will mix with each other within the semiconductor layer due to the sputter effect. Therefore, at least one PN, PI, NI or PIN junction
When stacking a plurality of semiconductor layers, it is extremely important to separate the reaction vessels for each conductivity type independently, as described above, in order to form a sufficient junction at the interface.

本発明はかかる分離独立方式に加えて、さらに
その不純物の混合を排除させ、接合特性の向上を
計つたものである。すなわち例えば1つのPIN接
合を積層して形成させようとする時、第1の半導
体層としてのP型半導体層を形成させた場合、そ
の半導体層の形成の際同時にこの不純物の吸着が
反応容器の内壁また基板ホルダー表面におきる。
本発明においてはこれら基板上の被形成面以外の
壁面、表面からの不純物の再放出を防ぎ、また供
給系、排気系からの一度吸着した反応性気体の第
2の半導体層の形成に際し、離脱混入することを
防ぐため、反応容器のみではなく、反応性気体の
供給系、排気系もそれぞれ独立に各反応容器に対
応して設けられている。また基板ホルダーに関し
ても、基板のみが実質的に反応生成物の付着被膜
化がおきるように、基板の被形成面側のみプラズ
マ化された反応性気体が導びかれるように設けて
いる。
In addition to such a separate and independent method, the present invention aims to improve bonding characteristics by eliminating the mixing of impurities. That is, for example, when trying to form one PIN junction by stacking a P-type semiconductor layer as the first semiconductor layer, the adsorption of impurities in the reaction vessel occurs at the same time as the semiconductor layer is formed. Occurs on the inner wall or the surface of the substrate holder.
In the present invention, impurities are prevented from being re-released from walls and surfaces other than the surface on which they are formed on the substrate, and reactive gases once adsorbed from the supply system and exhaust system are released when forming the second semiconductor layer. In order to prevent contamination, not only reaction vessels but also reactive gas supply systems and exhaust systems are provided independently for each reaction vessel. The substrate holder is also provided in such a way that the plasma-converted reactive gas is guided only to the surface of the substrate on which the reaction product is to be formed, so that only the substrate is substantially coated with reaction products.

本発明にかかる欠点を防ぐため、反応性気体の
導入口、排気口においてガイドを設け、この間の
基板の被形成面により実質的に作られた筒状空間
のみに選択的にプラズマ反応を発生せしめること
によりチアンバー(反応容器)内の全空間に反応
生成物が拡散し広がることを防いだものである。
かかる本発明の構造のプラズマ気相反応装置とす
ることにより、形成された不純物のそれぞれの半
導体層から他の半導体層への混合を排除し、その
混合部を200〜300Åと約1/10〜1/5にするととも
に、結晶学的にP型の半導体層上に連続してシヨ
ートレンジオーダの結晶性(秩序性)を有する真
性または実質的に真性の半導体層をも成長し得た
ことを特徴としている。またP、N型半導体層を
形成してPN接合を設けても、単なるオーム抵抗
特性ではなく、逆方向リークが5Vにて1μA以下
のダイオード特性を有せしめた効果を有した。
In order to prevent the drawbacks of the present invention, guides are provided at the reactive gas inlet and outlet, and plasma reaction is selectively generated only in the cylindrical space substantially created by the formation surface of the substrate between these guides. This prevents the reaction product from diffusing and spreading throughout the entire space within the chamber (reaction vessel).
By providing a plasma vapor phase reactor having such a structure according to the present invention, mixing of formed impurities from each semiconductor layer to another semiconductor layer can be eliminated, and the mixing area can be reduced to 200 to 300 Å, approximately 1/10 to 1/10. In addition to reducing the size to 1/5, it was also possible to grow an intrinsic or substantially intrinsic semiconductor layer having crystallinity (order) in the short range order continuously on a crystallographically P-type semiconductor layer. It is characterized by Furthermore, even when P- and N-type semiconductor layers were formed to provide a PN junction, it had the effect of providing diode characteristics with reverse leakage of 1 μA or less at 5 V, rather than mere ohmic resistance characteristics.

かくすることにより、その接合またその近傍に
集中している再結合中心の密度を十分小さくさせ
ることができた。即ち再結合中心は不純物の混合
によりアクセプタ、ドナーにならない価の不純
物と価の不純物が相互作用して深いトラツプレ
ベルを作るが、かかるトラツプセンタ(再結合中
心)を混合部の厚さをうすくすることにより少な
くし、また結晶学的に成長させることにより真性
半導体の不対結合手の存在濃度を従来の1018
1019cm-3より約1/100の1016〜1017cm-3にしたこと
を特徴としている。
By doing so, it was possible to sufficiently reduce the density of recombination centers concentrated at or near the junction. In other words, the recombination center is formed by mixing impurities, and the valent impurity that does not become an acceptor or donor interacts with the valent impurity to create a deep trap level. By reducing the concentration of dangling bonds in an intrinsic semiconductor by crystallographic growth, the concentration of dangling bonds in an intrinsic semiconductor can be reduced from the conventional
It is characterized by having a value of 10 16 to 10 17 cm -3 , which is about 1/100 of 10 19 cm -3 .

以下に本発明の実施例を図面に従つて説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

実施例 1 第1図に従つて本発明のプラズマ気相反応装置
の実施例を説明する。
Example 1 An example of the plasma vapor phase reactor of the present invention will be described with reference to FIG.

この図面はPI接合、NI接合、PN接合、PIN接
合、PINIP接合、NIPIN接合またはPINPIN…
…PIN接合等の基板上の半導体に異種導電型また
は同種導電型でありながらも形成される半導体の
主成分または化学量論比の異なる半導体層をそれ
ぞれの半導体層をその前の工程において形成され
た半導体層の影響を受けることを防ぐため、前の
半導体層を形成した反応容器に連設した他の独立
した反応容器で第2の半導体層を形成して、前の
半導体層上に積層して接合を作るとともに、さら
に多層に自動かつ連続的に形成するための装置で
ある。
This drawing is PI junction, NI junction, PN junction, PIN junction, PINIP junction, NIPIN junction or PINPIN…
...Semiconductor layers of different conductivity types or the same conductivity type but with different main components or stoichiometric ratios are formed on a semiconductor on a substrate such as a PIN junction, and each semiconductor layer is formed in a previous process. In order to prevent the second semiconductor layer from being affected by the semiconductor layer, the second semiconductor layer is formed in another independent reaction vessel connected to the reaction vessel in which the previous semiconductor layer was formed, and then stacked on top of the previous semiconductor layer. This is a device for automatically and continuously forming multiple layers.

図面においては特にPIN接合を構成する3つの
P、IおよびN型の半導体層を積層して形成する
第1および第2の予備室を有するマルチチアンパ
ー(ここでは3つの反応容器)方式のプラズマ気
相反応装置の装置例を示す。
In the drawings, a multi-chamber (here, three reaction vessels) type plasma is shown, which has first and second preliminary chambers formed by laminating three P, I, and N type semiconductor layers constituting a PIN junction. An example of a gas phase reactor is shown.

図面における系、、は3つの各反応容器
6,7,8を有し、それぞれ独立して反応性気体
の導入手段17,18,19と排気手段20,2
1,22とを有し、反応性気体が供給系または排
気系から逆流または他の系からの反応性気体の混
入を防いでいる。
The system in the drawing has three reaction vessels 6, 7, 8, each independently equipped with reactive gas introduction means 17, 18, 19 and exhaust means 20, 2.
1 and 22 to prevent reactive gas from flowing back from the supply system or exhaust system or from mixing with reactive gas from other systems.

この装置は入口側には第1の予備室5が設けら
れ、とびら42より基板ホルダ(ホルダともい
う)74に基板4,4′を挿着し、この予備室に
配置させた。この被形成面を有する基板は被膜形
成を行なわない裏面を互いに接し、2〜10cm好ま
しくは3〜5cmの間隙を有して林立させている。
この間隙は基板の反応性気体の流れ方向の長さが
10cm、15cm、20cmと長くなるにつれて、3〜4
cm、4〜5cm、5〜6cmと広げた。さらにこの第
1の予備室5を真空ポンプ35にてバルブ34を
開けて真空引をした。この後予め真空引がされて
いる反応容器6,7,8にゲート弁44を開けて
基板およびホルダを移した。例えば予備室5より
容器6に移し、さらにゲート弁44を閉じること
により移動させたものである。この時反応容器6
に保持されていた基板1は反応容器7に、また反
応容器7に保持されていた基板2は反応容器8
に、また反応容器8に保持されていた基板は第2
の出口側の予備室9に同時にゲート弁45,4
6,47を開けて移動させた。基板及びホルダを
移動させる手段は、種々ある公知のもののなかか
ら適宜採用できる。第2の予備室に移された基板
はゲート弁47が閉じられた後41より窒素が導
入されて大気圧にされ、43のとびらより外に出
した。
This apparatus is provided with a first preliminary chamber 5 on the entrance side, and substrates 4 and 4' are inserted into a substrate holder (also referred to as holder) 74 through a door 42 and placed in this preliminary chamber. The substrates having the surfaces on which the film is to be formed are arranged in a row with the back surfaces on which no film is to be formed in contact with each other with a gap of 2 to 10 cm, preferably 3 to 5 cm.
The length of this gap in the flow direction of the reactive gas on the substrate is
3 to 4 as the length increases to 10 cm, 15 cm, and 20 cm.
cm, 4-5 cm, and 5-6 cm. Furthermore, this first preliminary chamber 5 was evacuated using a vacuum pump 35 by opening a valve 34. Thereafter, the gate valve 44 was opened and the substrate and holder were transferred to the reaction vessels 6, 7, and 8, which had been evacuated in advance. For example, the sample is transferred from the preliminary chamber 5 to the container 6, and further transferred by closing the gate valve 44. At this time, reaction vessel 6
The substrate 1 held in the reaction vessel 7 is moved to the reaction vessel 7, and the substrate 2 held in the reaction vessel 7 is moved to the reaction vessel 8.
In addition, the substrate held in the reaction vessel 8 is transferred to the second
At the same time, gate valves 45 and 4 are installed in the preliminary chamber 9 on the outlet side of the
6,47 was opened and moved. The means for moving the substrate and the holder can be appropriately selected from among various known means. After the gate valve 47 was closed, the substrate transferred to the second preliminary chamber was brought to atmospheric pressure by introducing nitrogen through 41, and was taken out through the door 43.

即ちゲート弁の動きはとびら42,43が大気
圧で開けられた時はゲート弁44,45,46,
47は閉じられ、各チアンバーにおいてはプラズ
マ気相反応が行なわれる。また逆にとびら42,
43が閉じられていて予備室5,9が十分真空引
された時は、ゲート弁44,45,46,47が
開き、各チアンバーの基板、、ホルダは隣りのチ
アンバーに移動する機構を有している。
That is, the movement of the gate valves is as follows: when the doors 42, 43 are opened at atmospheric pressure, the gate valves 44, 45, 46,
47 is closed and a plasma gas phase reaction takes place in each chamber. On the contrary, door 42,
43 is closed and the preliminary chambers 5, 9 are sufficiently evacuated, the gate valves 44, 45, 46, 47 are opened, and the substrate and holder of each chamber has a mechanism to move to the adjacent chamber. ing.

さらに反応容器内に筒状空間を構成させ、その
筒状空間内に基板を設置してプラズマ反応により
基板上に被膜を形成するものであり、第1の反応
容器で被膜形成後は基板を配設しているホルダが
第2の反応容器に移動する構造となつている。第
2の反応容器では第1の反応容器と同様ホルダの
上下をガイドによりとり囲み筒状空間を構成させ
た。そのため反応が筒状空間内で行われると、第
1の反応室内で基板上に形成した第1の膜と同様
の膜がホルダにも付着することになり、そのまま
第2の反応室にホルダを移動させてさらに第2の
膜形成を行うとホルダにも同様に第2の膜が形成
されることになる。
Furthermore, a cylindrical space is formed in the reaction vessel, a substrate is placed in the cylindrical space, and a film is formed on the substrate by plasma reaction. After the film is formed in the first reaction vessel, the substrate is placed. The structure is such that the installed holder can be moved to the second reaction vessel. In the second reaction vessel, as in the first reaction vessel, the upper and lower sides of the holder were surrounded by guides to form a cylindrical space. Therefore, when the reaction is carried out in the cylindrical space, a film similar to the first film formed on the substrate in the first reaction chamber will also adhere to the holder, and the holder will be transferred to the second reaction chamber. If the holder is moved and a second film is further formed, the second film will be formed on the holder as well.

従つてホルダには基板上に膜形成を行う時と同
じ様な雰囲気で膜形成が行われることになる。
Therefore, film formation is performed on the holder in the same atmosphere as when film formation is performed on the substrate.

よつて本願発明の装置においてはホルダの内壁
には基板と同じように膜が形成されているため、
ホルダ内が膜形成面と同じような雰囲気となり例
えホルダの内壁から第1の膜が離脱したとしても
膜形成面でも同様なことが生じており、膜自体の
特性に影響を与える程度ではないため良質の膜を
形成することができる。その結果良質の半導体装
置を作成することができます。さらにプラズマが
筒状空間より外部にもれないため反応容器内壁に
膜形成がありません。そのため反応容器内の掃除
が不要となる。
Therefore, in the device of the present invention, since a film is formed on the inner wall of the holder in the same way as the substrate,
Even if the inside of the holder has the same atmosphere as the film formation surface and the first film detaches from the inner wall of the holder, the same thing will occur on the film formation surface and will not affect the properties of the film itself. A high quality film can be formed. As a result, high quality semiconductor devices can be created. Furthermore, since the plasma does not leak outside the cylindrical space, there is no film formation on the inner wall of the reaction vessel. Therefore, cleaning inside the reaction container becomes unnecessary.

系における第1の反応容器6でのP型半導体
層を形成する場合を以下に記す。
The case of forming a P-type semiconductor layer in the first reaction vessel 6 in the system will be described below.

反応系(反応容器6を含む)は10-3〜10torr
好ましくは0.01〜1torr例えば0.1torrとした。
The reaction system (including reaction vessel 6) is 10 -3 to 10 torr
Preferably it is 0.01 to 1 torr, for example 0.1 torr.

反応性気体は珪化物気体24に対してはシラン
(SinH2o+2n1特にSiH4)、ジクロールシラン
(SiH2Cl2)、トリクロールシラン(SiHCl2)、四
フツ化珪素(SiF4)等があるが、取扱いが容易な
シランを用いた。価格的にはジクロールシランの
方が安価であり、これを用いてもよい。
For the silicide gas 24, reactive gases include silane (SinH 2o+2 n1, especially SiH 4 ), dichlorosilane (SiH 2 Cl 2 ), trichlorosilane (SiHCl 2 ), and silicon tetrafluoride (SiF 4 ). Silane, which is easy to handle, was used. Dichlorosilane is cheaper and may be used.

本実施例のSixC-x(0<x<1)を形成するた
め炭化物気体23に対してはメタン(CH4)を用
いた。CF4のような炭化物気体であつても、また
四塩化炭素(CCl4)のような塩化炭素であつて
もよい。
Methane (CH 4 ) was used for the carbide gas 23 to form SixC -x (0<x<1) in this example. It may be a carbide gas such as CF 4 or a carbon chloride such as carbon tetrachloride (CCl 4 ).

炭化珪素(SixC1-x0<x<1)に対しては、
P型の不純物としてボロンを水素にて2000PPM
に希釈されたジボランより25より供給した。ま
たガリユームをTMG(Ga(CH33)により1019
9×1021cm-3の濃度になるように加えてもよい。
For silicon carbide (SixC 1-x 0<x<1),
2000PPM of boron with hydrogen as a P-type impurity
diborane diluted to 25%. In addition, galiyum was treated with TMG (Ga(CH 3 ) 3 ) at 10 19 ~
It may be added to a concentration of 9×10 21 cm −3 .

キヤリアガス39は反応中は水素(H2)を用
いたが、反応開始の前後は窒素(N2)を液体窒
素により利用した。これらの反応性気体はそれぞ
れの流量計33およびバルブ32をヘて、反応性
気体の導入口17より高周波電源の負電極61を
へて反応容器6に供給された。反応性気体は70
のガイドをへて筒状空間を構成する基板1および
ホルダ74内に導入され、負電極61と正電極5
1間を電気エネルギ例えば13.56MHzの高周波エ
ネルギを加えて反応せしめ、基板上に反応生成物
を被膜形成せしめた。
As the carrier gas 39, hydrogen (H 2 ) was used during the reaction, but nitrogen (N 2 ) was used in the form of liquid nitrogen before and after the start of the reaction. These reactive gases were supplied to the reaction vessel 6 through the respective flowmeters 33 and valves 32, through the reactive gas inlet 17, and through the negative electrode 61 of the high frequency power source. Reactive gas is 70
The negative electrode 61 and the positive electrode 5 are introduced into the substrate 1 and the holder 74 forming a cylindrical space.
Electrical energy, for example, high frequency energy of 13.56 MHz, was applied between 1 and 1 to cause a reaction, and a reaction product was formed as a film on the substrate.

基板は100〜400℃例えば200℃に赤外線ヒータ
11,11′により加熱した。
The substrate was heated to 100-400°C, for example 200°C, by infrared heaters 11, 11'.

この赤外線ヒータは赤外線イメージ炉ともい
い、棒状を有するため上方のヒータと下方のヒー
タとが互いに直交する方向に配置して、この反応
容器内における特に筒状空間を200±10℃好まし
くは±5C以内に設置した。このヒータは上側ま
たは下側のみでは反応性気体の流れ方向に200〜
120℃と80℃をも不均一を生じ、全く実用になら
なかつた。また互いに直交させることにより、基
板間の温度分布も±10℃以内とすることができ
た。この後、前記したが、この容器に前記した反
応性気体を導入し、さらに10〜50Wに高周波エネ
ルギ14を供給してプラズマ反応をおこさせた。
This infrared heater is also called an infrared image furnace, and since it has a rod shape, the upper heater and the lower heater are arranged perpendicularly to each other, and the cylindrical space in the reaction vessel is heated to 200±10°C, preferably ±5°C. It was installed within. This heater only has a 200~200°
Temperatures of 120°C and 80°C also caused non-uniformity and were not practical at all. Furthermore, by making the substrates orthogonal to each other, the temperature distribution between the substrates could be kept within ±10°C. Thereafter, as described above, the above-described reactive gas was introduced into the container, and high-frequency energy 14 of 10 to 50 W was further supplied to cause a plasma reaction.

かくしてP型半導体層はB2H6/SiH4=0.5%、
CH4/(SiH4+CH4)=0.5の条件にて、この反応
系で約100Åの厚さを有する薄膜として形成さ
せた。Eg=2.0eV,σ=1×10-4〜3×10-3(Ω
cm)-1であつた。
Thus, the P-type semiconductor layer has B 2 H 6 /SiH 4 =0.5%,
A thin film having a thickness of about 100 Å was formed using this reaction system under the conditions of CH 4 /(SiH 4 +CH 4 )=0.5. Eg=2.0eV, σ=1×10 -4 ~3×10 -3
cm) -1 .

従来炭化珪素は一般に珪素のみに比べて大きな
高周波エネルギを必要とする。そのため、電界が
被形成面に垂直方向の場合、被形成面に設けられ
た透明導電膜(ITOまたは酸化スズの600〜800Å
の電極用被膜)はスパツタされて、酸化スズが金
属スズに変わつて透明でなく白濁しやすい。
Conventional silicon carbide generally requires greater high frequency energy than silicon alone. Therefore, when the electric field is perpendicular to the surface to be formed, a transparent conductive film (ITO or tin oxide with a thickness of 600 to 800 Å
(electrode coatings) are sputtered, and the tin oxide turns into metallic tin, making them less transparent and more likely to become cloudy.

そのためにはプラズマ電界を被形成面に概略平
行にすると良く、この電界による反応生成物は表
面にそつて移動するため、スパツタ効果による白
濁化は30〜50W加えても見られず、垂直電界の場
合が2〜5Wが限界だつたことに比べて、特性歩
留りおよび製造歩留りを向上させた。
To achieve this, it is best to make the plasma electric field approximately parallel to the surface to be formed, and since the reaction products caused by this electric field move along the surface, clouding due to the sputter effect is not seen even when 30 to 50 W is applied, and the vertical electric field Compared to the case where the limit was 2 to 5 W, the characteristic yield and manufacturing yield were improved.

基板は導体基板(ステンレス、チタン、窒化チ
タン、その他の金属)、半導体(珪素、炭化珪素、
グルマニユーム)、絶縁体(アルミナ、ガラス、
有機物質)または複合基板(ガラス絶縁基板上に
酸化スズ、ITO等の導電膜が単層またはITO上に
SnO2が形成された2層膜が形成されたもの、絶
縁基板上に選択的に導体電極が形成されたもの、
絶縁基板上にPまたはN型の半導体が形成された
もの)を用いた。本実施例のみならず本発明のす
べてにおいてこれらを総称して基板という。もち
ろんこの基板は可曲性であつてもまた固い板であ
つてもよい。
Substrates include conductor substrates (stainless steel, titanium, titanium nitride, and other metals), semiconductors (silicon, silicon carbide,
gurmanium), insulators (alumina, glass,
Organic materials) or composite substrates (conductive films such as tin oxide or ITO on a glass insulating substrate or a single layer on ITO)
One in which a two-layer film with SnO 2 is formed, one in which conductive electrodes are selectively formed on an insulating substrate,
A P- or N-type semiconductor formed on an insulating substrate was used. These are collectively referred to as a substrate not only in this embodiment but also in all of the present invention. Of course, this substrate may be flexible or a rigid plate.

かくして1〜5分間プラズマ反応をさせて、P
型不純物としてホウ等またはガリユームが添加さ
れた炭化珪素膜を作成した。さらにこの第1の半
導体層上に基板を前記した操作順序に従つて第2
の反応容器7に移動し、ここで真性の半導体層を
約5000Åの厚さに形成させた。
In this way, a plasma reaction is performed for 1 to 5 minutes, and P
A silicon carbide film to which boron or gallium was added as a type impurity was created. Further, a substrate is placed on the first semiconductor layer and a second semiconductor layer is placed on top of the first semiconductor layer.
was moved to a reaction vessel 7, where an intrinsic semiconductor layer was formed to a thickness of about 5000 Å.

すなわち第1図における反応系において、半
導体の反応性気体としてシランを28より、また
水素等のキヤリアガスを必要に応じて27,26
より供給して、一対を構成する電極18,21に
て系と同様に高周波電源15より13.56MHzの
高周波エネルギを供給した。基板は250℃にヒー
タ12,12により加熱した。反応性気体は基板
2の被形成面にそつて上方より下方に流れ、真空
ポンプ37に至る。系において43の出口側よ
りみたたて断面図を第2図に示す。
That is, in the reaction system shown in FIG. 1, silane is used as a reactive gas for the semiconductor at 28, and a carrier gas such as hydrogen is used at 27 and 26 as necessary.
Similarly to the system, high frequency energy of 13.56 MHz was supplied from the high frequency power supply 15 to the electrodes 18 and 21 forming the pair. The substrate was heated to 250° C. by heaters 12, 12. The reactive gas flows from above to below along the surface of the substrate 2 to be formed, and reaches the vacuum pump 37 . A sectional view of the system viewed from the outlet side of 43 is shown in FIG.

第2図を概説する。 Figure 2 is outlined.

第2図において反応容器7はのぞき窓48電波
漏えい防止用銅網49、裏側にマイクロ波供給用
の石英窓55導波管54、さらにマイクロ波また
はミリ波用電源56を具備している。基板2の被
形成面にそつて平行に反応性気体26,27,2
8および高周波15の電界が配されるように設け
てある。
In FIG. 2, the reaction vessel 7 is equipped with a viewing window 48, a copper mesh 49 for preventing leakage of radio waves, a quartz window 55 for supplying microwaves on the back side, a waveguide 54, and a power supply 56 for microwaves or millimeter waves. Reactive gases 26, 27, 2 are applied parallel to the formation surface of the substrate 2.
8 and a high frequency electric field 15 are arranged.

さらに高周波に加えて1GHz以上の周波数例え
ば2.45GHzのマイクロ波が供給されている。
Furthermore, in addition to high frequencies, microwaves with a frequency of 1 GHz or higher, for example 2.45 GHz, are supplied.

第2図において、反応性気体は66より導入さ
れ、石英管導入口より網状または多孔状の電極6
7をへて導出させた。反応性気体の導出口18、
基板2、ホルダ74、排気口21、一対の電極6
7,68の相関関係については、第3図にさらに
その斜視図(前半分を切断してある)で示してい
る。
In FIG. 2, the reactive gas is introduced from the quartz tube inlet into the mesh or porous electrode 6.
7 and derived it. reactive gas outlet 18;
Substrate 2, holder 74, exhaust port 21, pair of electrodes 6
The correlation between numbers 7 and 68 is further shown in a perspective view (with the front half cut away) in FIG.

さらに好ましい例を示すと、第3図において基
板2は裏面を互いに合せてさしこみ式になつたホ
ルダ74に垂直方向(鉛直方向)を互いに一定の
間隙例えば3cmにて平行に配置されていると良
い。ホルダは石英よりなり、上側に円板状のデイ
スクとこれに連結した基板用みぞ95を有してい
る。デイスクは4つのサポータ80,80′によ
り空間に保持され、サポータ80,80′は軸7
9,79′の回転に従つて回転し、その結果デイ
スクを3〜10回/分の速度で回転し、反応性気体
の均質化を促進させている。
To show a more preferable example, in FIG. 3, it is preferable that the substrates 2 are arranged parallel to each other in the vertical direction (vertical direction) with a fixed gap of 3 cm, for example, in a holder 74 which is an insertion type with their back sides aligned with each other. . The holder is made of quartz and has a disk-shaped disk on the upper side and a substrate groove 95 connected to the disk. The disk is held in space by four supports 80, 80', which are connected to the shaft 7.
9,79' rotations, thereby rotating the disk at a rate of 3 to 10 times per minute to promote homogenization of the reactive gases.

反応性気体は導出口18より1〜3mmの穴73
をへて網状電極(穴約5〜10mm)67をへて、下
方向にふき出させている。ホルダのガイド70に
より反応性気体の82方向への放出を防ぐため、
81の間隙は1cm以下好ましくは2〜5mmとし
た。そして反応性気体は基板2,2の被形成面お
よび基板2をたてるためのみぞ95を保持するた
めの壁96とによつて、筒状に構成し、即ち煙突
状に設けられた中空を83,85の方向に層状に
流させると良い。石英の側壁96はみぞ95より
外側に10〜20mm離れて設け、反応性気体の側壁9
6でのみだれの発生を防ぎ、そのことにより基体
2の端部での被膜の膜厚の均一性をより促進させ
た。
The reactive gas is passed through a hole 73 with a diameter of 1 to 3 mm from the outlet 18.
It passes through a mesh electrode (hole approximately 5 to 10 mm) 67 and is blown out downward. In order to prevent the reactive gas from being released in 82 directions by the guide 70 of the holder,
The gap between 81 and 81 was 1 cm or less, preferably 2 to 5 mm. The reactive gas is formed into a cylindrical shape by the formation surfaces of the substrates 2, 2 and the wall 96 for holding the groove 95 for raising the substrate 2, that is, a chimney-shaped hollow. It is preferable to flow it in layers in the directions of 83 and 85. The quartz side wall 96 is placed 10 to 20 mm away from the groove 95, and the reactive gas side wall 9
The occurrence of sagging in the film 6 was prevented, thereby further promoting the uniformity of the film thickness at the end of the substrate 2.

また排気系に関しても、84からの反応性気体
の流入を少なくし、85を選択的に優先させるた
め、ガイド71と基板下端との間隙を1cm以下に
合せて設けた。即ち82,84のガス流のコンダ
クタンスを83,85の約1/5以下好ましくは1/3
0〜1/100にすることにより、筒状空間に選択的に
反応性気体を導き入れた。正電極68と基板下端
との距離はガイドの高さを調節して設けた。
Regarding the exhaust system, in order to reduce the inflow of reactive gas from 84 and selectively give priority to 85, the gap between guide 71 and the bottom end of the substrate was set to 1 cm or less. In other words, the conductance of the gas flow of 82, 84 should be about 1/5 or less, preferably 1/3 of that of 83, 85.
By setting the ratio to 0 to 1/100, reactive gas was selectively introduced into the cylindrical space. The distance between the positive electrode 68 and the lower end of the substrate was determined by adjusting the height of the guide.

さらに負電極67と基板上端即ちデイスク74
との距離も同様にガイド70により調節した。
Furthermore, the negative electrode 67 and the upper end of the substrate, that is, the disk 74
Similarly, the distance between the guide 70 and the guide 70 was adjusted.

第3図より明らかな如く、電極はその外周辺側
を石英のガイド70、上ぶた93、ガイド71、
下ぶた94によつて囲まれており、電極とチアン
バー(特にステンレスチアンバー)の内壁との寄
生放電の防止に務めた。さらに反応性気体の導入
口18の内径と負電極が概略同一の大きさを有
し、また排気口21の内径と正電極とが概略同一
の大きさを有するため、高周波放電を行なうと、
この筒状空間即ち反応性気体の被形成面にそつて
流れて空間を優先的にプラズマ放電させている。
その結果、反応性気体のプラズマ化率がきわめて
大きくなり、ひいては反応容器(ベルジヤー)の
内壁に過剰の反応生成物がピンホール発生の原因
となるフレーク状に付着してしまうことを防ぐこ
とができた。
As is clear from FIG. 3, the electrode has a quartz guide 70, an upper lid 93, a guide 71,
It is surrounded by a lower lid 94, which serves to prevent parasitic discharge between the electrode and the inner wall of the chamber (particularly the stainless steel chamber). Furthermore, since the inner diameter of the reactive gas inlet 18 and the negative electrode have approximately the same size, and the inner diameter of the exhaust port 21 and the positive electrode have approximately the same size, when high-frequency discharge is performed,
It flows along this cylindrical space, that is, the surface on which the reactive gas is formed, preferentially causing plasma discharge in the space.
As a result, the plasma conversion rate of the reactive gas becomes extremely high, and it is possible to prevent excessive reaction products from adhering to the inner wall of the reaction vessel (belgear) in the form of flakes, which can cause pinholes. Ta.

以上の如き第3図の構成に加えて、その番号が
対応した第2図においては、赤外線ランプ12,
12′が上方向、下方向に設け、基板の均質化を
促進させると良い。
In addition to the configuration of FIG. 3 as described above, in FIG. 2 with corresponding numbers, infrared lamps 12,
12' are preferably provided in the upper and lower directions to promote homogenization of the substrate.

第3図の構成は第1図における系,におけ
る反応容器6,8での電極、基板、ホルダ、反応
性気体導出口、排気口においても同様の構成を有
せしめた。かくして第3図において基板および基
板ホルダは何らの支障なく77の系の方向より
到り、また78の方向の系の方向に移動させる
ことができた。
The structure shown in FIG. 3 is similar to that of the electrodes, substrates, holders, reactive gas outlets, and exhaust ports in the reaction vessels 6 and 8 in the system shown in FIG. Thus, in FIG. 3, the substrate and substrate holder were able to arrive from the system direction 77 and move in the system direction 78 without any problem.

図面では250℃において3Å/秒の成長速度を
高周波電界を20Wとしシランを30c.c./分加えると
得ることができた。結果として従来の平行平板型
の電極方式において0.1〜1Å/秒に比べて、同
一反応容器において、例えば前者が10cm□1まい
であるのに対し、10cm□8まいを被膜の成長速度
が従来を0.5Å/秒とすると6倍になり、合計48
倍の多量生産が可能となつた。また従来50cmを作
製する空間においては、20cm×50cmの基板を間隙
5cmとし、20配列同時に可能となり、被形成面積
は実質的に20×50×20=2×104cm2と同様に8倍
にすることができ、電極間距離は従来の4cmより
25〜27cmになつたため、反応性気体のイオン化率
も向上し、被膜成長速度も4Å/秒を得ることが
できるため、結果として64倍の成長速度を実質的
に有するきわめて理想的な多量生産方式であるこ
とがわかつた。
In the drawing, a growth rate of 3 Å/sec at 250°C could be obtained by using a high frequency electric field of 20 W and adding silane at 30 c.c./min. As a result, compared to 0.1 to 1 Å/sec in the conventional parallel plate type electrode system, the film growth rate in the same reaction vessel is 10 cm □ 8 Å/sec compared to 10 cm □ 1 Å/sec in the former case. If it is 0.5 Å/sec, it will be 6 times more, totaling 48
It has become possible to produce double the amount. In addition, in the conventional space for fabricating 50 cm substrates, 20 cm × 50 cm substrates can be arranged at the same time with a gap of 5 cm, and 20 arrays can be arranged at the same time, and the area to be formed is essentially 8 times as large as 20 × 50 × 20 = 2 × 10 4 cm 2 . The distance between the electrodes is shorter than the conventional 4 cm.
Since the length is 25 to 27 cm, the ionization rate of the reactive gas is also improved, and the film growth rate is 4 Å/sec. As a result, the growth rate is 64 times faster, making it an extremely ideal mass production method. It turns out that it is.

かくして形成された半導体層は、プラズマ状態
の距離が長いため、光伝導度も2×10-4〜7×
10-3(Ωcm)-1、暗伝導度3×10-7〜1×10-9(Ω
cm)-1を有していた。
Since the semiconductor layer thus formed has a long plasma state distance, its photoconductivity also ranges from 2×10 -4 to 7×
10 -3 (Ωcm) -1 , dark conductivity 3×10 -7 to 1×10 -9
cm) -1 .

またかくして型半導体層を系にて約5000Å
の厚さに形成させた後、基板は前記した操作に従
つて系の反応容器8に移され、N型半導体層が
形成された。このN型半導体層には、第1図にお
いてフオスヒンをPH3/SiH4=1.0%とし31よ
りまたシランを30より、またキヤリアガスの水
素を29よりSiH4/H2=50として供給し系と
同様にして200Åの厚さにN型の微結晶性または
繊維構造を有する多結晶の半導体層を形成させた
ものである。その他反応装置については系と同
様である。
In this way, the type semiconductor layer is approximately 5000 Å thick in the system.
After forming the substrate to a thickness of , the substrate was transferred to the reaction vessel 8 of the system according to the operations described above, and an N-type semiconductor layer was formed. To this N-type semiconductor layer, as shown in FIG. 1, phosphin was supplied from 31 at PH 3 /SiH 4 =1.0%, silane was supplied from 30, and carrier gas hydrogen was supplied from 29 at SiH 4 /H 2 =50 to form a system. Similarly, an N-type microcrystalline or polycrystalline semiconductor layer having a fiber structure was formed to a thickness of 200 Å. Other reaction equipment is the same as the system.

かかる工程の後、第2の予備室9より外にPIN
接合を構成して出された基板上にアルミニユーム
電極を真空蒸着法により約1μの厚さに作り、カ
ラス基板上に(ITO+SnO2)表面電極−(PIN半
導体)(A1裏面電極)を構成させた。
After this process, enter the PIN from the second preliminary room 9.
An aluminum electrode with a thickness of about 1 μm was made by vacuum evaporation on the substrate that had been formed by forming the bond, and an (ITO + SnO 2 ) surface electrode - (PIN semiconductor) (A1 back electrode) was formed on the glass substrate. .

その光電変換装置としての特性は7〜9%平均
8%を10cm□の基板でAM1(100mW/cm2)にて
真性効率特性として有し、ハイブリツド型にした
15cm×40cmの基板においても、6〜7%を真性効
率で得ることができた。この効率の向上は光が入
射する側のPI接合がきわめて面的に構成され、
またアモルフアス半導体またはセミアモルフアス
半導体等の非単結晶半導体においても、P型半導
体層上にI型半導体層を成長積層させたことによ
るもので、また開放電圧は0.88〜0.9Vであつた
が、短絡電流は20〜22mA/cm2と大きく、また
FFも0.70〜0.78と大きく、PIN型の半導体層内部
における再結合中心の密度が従来の方法に比べ1/
10〜1/50になつたことによる電流増加が大きな特
性改良につながつたものと推定される。
Its properties as a photoelectric conversion device are 7 to 9%, with an average of 8% as an intrinsic efficiency characteristic at AM1 (100mW/cm 2 ) on a 10cm□ substrate, making it a hybrid type.
Even on a 15 cm x 40 cm substrate, we were able to obtain an intrinsic efficiency of 6 to 7%. This improvement in efficiency is due to the extremely planar structure of the PI junction on the side where light enters.
Also, in non-single crystal semiconductors such as amorphous semiconductors or semi-amorphous semiconductors, an I-type semiconductor layer is grown and laminated on a P-type semiconductor layer, and the open circuit voltage is 0.88 to 0.9V. The short circuit current is large at 20-22mA/ cm2 , and
FF is also large at 0.70 to 0.78, and the density of recombination centers inside the PIN type semiconductor layer is 1/1 compared to the conventional method.
It is estimated that the increase in current due to the reduction in current by 10 to 1/50 has led to a significant improvement in characteristics.

かくの如く本発明のプラズマ反応装置は形成さ
れる半導体において生産性を30〜70倍も向上さ
せ、また特性も従来の5〜7%の変換効率に比べ
30%も向上させるきわめて独創的なものである。
As described above, the plasma reactor of the present invention improves the productivity of semiconductors formed by 30 to 70 times, and also has improved characteristics compared to the conventional conversion efficiency of 5 to 7%.
This is an extremely original product that improves performance by 30%.

実施例 2 この実施例は実施例1の変形であり、第2図に
対応した図面を第4図に示してある。その他は第
1図〜第3図と同様である。
Embodiment 2 This embodiment is a modification of Embodiment 1, and a drawing corresponding to FIG. 2 is shown in FIG. 4. Other details are the same as in FIGS. 1 to 3.

第4図はI型半導体層を形成するプラズマ反応
容器のたて断面図であり、図面において反応性気
体26,27,28は導入口66をへて導出口1
8より横方向に噴き出されている。また排出口も
21をへて76よりロータリーポンプ37に至つ
ている。基板2は鉛直方向に立てて林立させ、ホ
ルダ74により空間に保持されている。反応性気
体はガイド70,71により横型の筒状空間に選
択的に流れるようにしている。高周波電源15は
角電極67正電極72を有し、赤外線ランプ1
2,12′と上下に設けられ、均熱化を促進させ
た。
FIG. 4 is a vertical sectional view of a plasma reaction vessel in which an I-type semiconductor layer is formed.
It is ejected laterally from 8. Further, the discharge port also passes through 21 and reaches the rotary pump 37 from 76. The substrates 2 are arranged vertically in a row and are held in space by a holder 74. Guides 70 and 71 allow the reactive gas to flow selectively into the horizontal cylindrical space. The high frequency power source 15 has a square electrode 67 and a positive electrode 72, and the infrared lamp 1
2 and 12' were installed above and below to promote uniform heating.

この実施例においては、基板2ホルダ74の系
〜への移動が容易であるという特性を有す
る。しかし反応性気体が温度の上昇気流により上
方に多く流れ、基板の上側が厚くなりやすい。こ
のため基板を18〜21の方向に配置させること
が必要になるが、この作業が構造上困難であると
いう欠点を有していた。また反応性気体の飛翔距
離が基板2の横方向であり、長いため反応性気体
の導入口側と排出口側とで得られた電気特性にバ
ラツキが発生してしまい、多量生産には実施例1
と同様にすぐれたものであつたが、高品質の特性
を大面積に均質に得るという点では欠点を有して
いた。
This embodiment has the characteristic that the substrate 2 holder 74 can be easily moved to the system. However, a large amount of reactive gas flows upward due to the rising temperature, and the upper side of the substrate tends to become thicker. For this reason, it is necessary to arrange the substrate in the direction of 18 to 21, but this has the drawback of being structurally difficult. In addition, since the flight distance of the reactive gas is long in the lateral direction of the substrate 2, variations occur in the electrical characteristics obtained on the reactive gas inlet side and outlet side. 1
However, it had a drawback in that it could not uniformly obtain high-quality characteristics over a large area.

参考例 第5図は参考例を示す。Reference example FIG. 5 shows a reference example.

第5図Aは実施例1の第3図に対応して図面の
概要を示したものである。第5図Aにおいて反応
性気体の導入口66より18、負電極67をへて
排気口21、正電極68、排気系74に至るが、
基板2はテーパ状を有し、基板の導入口側より排
気口側に向つてせまくなり、その形成される膜の
均一化をさらに促進させたものである。
FIG. 5A shows an outline of the drawing corresponding to FIG. 3 of the first embodiment. In FIG. 5A, the reactive gas flows from the inlet 66 through the negative electrode 67 to the exhaust port 21, the positive electrode 68, and the exhaust system 74.
The substrate 2 has a tapered shape and becomes narrower from the inlet side to the exhaust port side of the substrate, further promoting uniformity of the formed film.

(A)においてはフレークが被形成面に弱干付着し
やすいため、(B)においては反応性気体の導出口を
下方向より排気口を上方向に設けることも可能で
ある。
In (A), the flakes tend to adhere slightly to the surface on which they are formed, so in (B) it is also possible to provide the exhaust port for the reactive gas upward rather than the outlet for the reactive gas in the downward direction.

かくすると、フレークが被形成面に付くことが
なく、即ちピンホールによる製造歩留りも向上
し、加えて被膜の膜質も反応性気体の流れ方向に
おいて均質な結果を得た。しかし第1図の製造装
置に比べてその生産性は約1/2になつてしまつた。
In this way, flakes were not attached to the surface to be formed, that is, the manufacturing yield due to pinholes was improved, and in addition, the film quality of the film was homogeneous in the flow direction of the reactive gas. However, the productivity was about half that of the manufacturing equipment shown in Figure 1.

以上の本発明の実施例においては、PIN接合を
1つ有するものとした。しかしPINIP型のフオト
トランジスタ、PINPIN……PINのタンデム構造
の光電変換装置等多くの応用もその半導体層の数
に従つて反応容器をさらに連結すればよく、本発
明の技術思想において、これらも含まれることは
いうまでもない。
In the embodiments of the present invention described above, one PIN junction is provided. However, for many applications such as PINIP type phototransistors, PINPIN...PIN tandem structure photoelectric conversion devices, it is sufficient to further connect reaction vessels according to the number of semiconductor layers, and the technical concept of the present invention does not include these. Needless to say, it can be done.

本発明において形成される非単結晶半導体被膜
中の結晶構造がアモルフアスであれ多結晶であ
れ、その構造には制限を受けない。本発明は形成
された複数の積層された半導体被膜がP型、N型
またはI型を少なくともPI、PNまたはNI接合を
ひとつ有する半導体であることが重要である。ま
たこの半導体としての導電特性のリーク特性の軽
減のため、その接合面においてそれぞれを混合さ
せない高品質な被膜を多量生産することが大きな
特徴である。
Regardless of whether the crystal structure in the non-single crystal semiconductor film formed in the present invention is amorphous or polycrystalline, there is no restriction on the structure. In the present invention, it is important that the plurality of stacked semiconductor films formed are P-type, N-type or I-type semiconductors having at least one PI, PN or NI junction. In addition, in order to reduce the leakage characteristics of the conductive properties of this semiconductor, a major feature is to mass-produce a high-quality coating that does not mix each other at the bonding surface.

さらにこの珪素または炭素の不対結合手を水素
によりSi−H、C−Hにて中和するのではなくSi
−C1、C−C1とハロゲン化物特に塩化物気体を
用いて実施してもよいことはいうまでもなく、こ
の濃度は10原子%以下、例えば2〜5原子%が好
ましかつた。
Furthermore, instead of neutralizing the dangling bonds of silicon or carbon with hydrogen by Si-H or C-H,
It goes without saying that the reaction may be carried out using -C1, C-C1 and a halide gas, particularly a chloride gas, and the concentration thereof is preferably 10 atomic % or less, for example 2 to 5 atomic %.

形成させる半導体の種類に関しては、実施例1
に示したが、族のSi、Ge、SixC1-x(0<x<
1)、SixGe1-x(0<x<1)、SixSn1-x(0<x
<1)のみでになく、これ以外にGaAs,
GaAlAs,BP,Cds等の化合物半導体であつても
よいことはいうまでもない。
Regarding the type of semiconductor to be formed, see Example 1.
However, in the group Si, Ge, SixC 1-x (0<x<
1), SixGe 1-x (0<x<1), SixSn 1-x (0<x
<1) In addition to this, GaAs,
Needless to say, it may be a compound semiconductor such as GaAlAs, BP, or Cds.

本発明で形成された炭化珪素被膜に対しフオト
エツチ技術を用いて選択的にPまたはN型の不純
物を混入または拡散してPN接合を部分的に作
り、この接合を利用してトランジスタ、ダイオー
ド、W−N−W(WIDE−NALLOW−WIDE)構
造のPIN接合型の可視光レーザ、発光素子または
光電変換素子を作つてもよい。特に光入射光側の
エネルギバンド巾を大きくしたヘテロ接合構造を
有するいわゆるW−N(WIDE TO NALLOW)
とを各反応室にて導電型のみではなく生成物を異
ならせてそれぞれ独立して作製して積層させるこ
とが可能になり、工業的にきわめて重要なもので
あると信ずる。
P- or N-type impurities are selectively mixed or diffused into the silicon carbide film formed according to the present invention using photo-etch technology to partially create PN junctions, and this junction can be used to create transistors, diodes, W A PIN junction type visible light laser, light emitting element, or photoelectric conversion element having a -N-W (WIDE-NALLOW-WIDE) structure may be made. The so-called W-N (WIDE TO NALLOW) has a heterojunction structure with a particularly large energy band width on the incident light side.
We believe that this is extremely important industrially, as it makes it possible to independently produce and laminate products with different conductivity types as well as different products in each reaction chamber.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は本発明を実施するための半導
体膜形成用製造装置の概略を示す。第3図は第2
図の装置の一部の斜視図を示す。第4図は第2図
に対応した本発明の他の実施例である。第5図は
本発明の第3図に対応した参考例である。
1 and 2 schematically show a manufacturing apparatus for forming a semiconductor film for carrying out the present invention. Figure 3 is the second
Figure 3 shows a perspective view of a portion of the illustrated apparatus; FIG. 4 shows another embodiment of the present invention corresponding to FIG. FIG. 5 is a reference example corresponding to FIG. 3 of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 第1のプラズマ反応を行うための第1の反応
室と、第2のプラズマ反応を行うための第2の反
応室とがゲート弁を介して連設されており、基板
を内部に配置するためのホルダーと、該ホルダー
が反応室間を移動するための手段とを有し、各反
応室内にはそれぞれ反応室に固定された一対のガ
イドが対向して備えられていて、前記ホルダーは
ホルダー内に配設された基板の2方向を除いて完
全に周囲を取り囲んでおり、かつ各反応室内にお
いてプラズマ反応を行わしめる際に、前記一対の
ガイドが基板の前記2方向から基板を囲むことに
よりホルダーとガイドによつて得られるプラズマ
が漏れない程度の閉じた空間に基板が配置され、
該閉じた空間内においてプラズマ反応が発生する
ことを特徴とするプラズマ気相反応装置。
1 A first reaction chamber for performing a first plasma reaction and a second reaction chamber for performing a second plasma reaction are connected via a gate valve, and a substrate is placed inside. and a means for moving the holder between reaction chambers, each reaction chamber is provided with a pair of opposing guides fixed to the reaction chamber, and the holder is configured to move between reaction chambers. The pair of guides completely surrounds the substrate in all but two directions, and when performing a plasma reaction in each reaction chamber, the pair of guides surrounds the substrate from the two directions. The substrate is placed in a closed space that does not allow the plasma obtained by the holder and guide to leak.
A plasma vapor phase reaction device characterized in that a plasma reaction occurs within the closed space.
JP57163730A 1982-09-20 1982-09-20 Plasma vapor reactor Granted JPS5952835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57163730A JPS5952835A (en) 1982-09-20 1982-09-20 Plasma vapor reactor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57163730A JPS5952835A (en) 1982-09-20 1982-09-20 Plasma vapor reactor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP63292203A Division JPH01157520A (en) 1988-11-18 1988-11-18 Plasma vapor reaction

Publications (2)

Publication Number Publication Date
JPS5952835A JPS5952835A (en) 1984-03-27
JPH0436449B2 true JPH0436449B2 (en) 1992-06-16

Family

ID=15779570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57163730A Granted JPS5952835A (en) 1982-09-20 1982-09-20 Plasma vapor reactor

Country Status (1)

Country Link
JP (1) JPS5952835A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481230A (en) * 1983-10-27 1984-11-06 Rca Corporation Method of depositing a semiconductor layer from a glow discharge
US4680451A (en) * 1985-07-29 1987-07-14 A. G. Associates Apparatus using high intensity CW lamps for improved heat treating of semiconductor wafers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5143718U (en) * 1974-09-27 1976-03-31
JPS5578524A (en) * 1978-12-10 1980-06-13 Shunpei Yamazaki Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5143718U (en) * 1974-09-27 1976-03-31
JPS5578524A (en) * 1978-12-10 1980-06-13 Shunpei Yamazaki Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS5952835A (en) 1984-03-27

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