JPS5916329A - Plasma vapor reaction device - Google Patents

Plasma vapor reaction device

Info

Publication number
JPS5916329A
JPS5916329A JP57126049A JP12604982A JPS5916329A JP S5916329 A JPS5916329 A JP S5916329A JP 57126049 A JP57126049 A JP 57126049A JP 12604982 A JP12604982 A JP 12604982A JP S5916329 A JPS5916329 A JP S5916329A
Authority
JP
Japan
Prior art keywords
reaction vessel
reaction
semiconductor layer
substrate
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57126049A
Other languages
Japanese (ja)
Other versions
JPH0522375B2 (en
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP57126049A priority Critical patent/JPS5916329A/en
Publication of JPS5916329A publication Critical patent/JPS5916329A/en
Publication of JPH0522375B2 publication Critical patent/JPH0522375B2/ja
Granted legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/517Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using a combination of discharges covered by two or more of groups C23C16/503 - C23C16/515
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To form junctions at lamination boundaries and then perform continuous production without forming layer insulators by a method wherein the supply is performed by orienting the direction of flow of reactive gas in parallel with the surface to be formed, and a waveguide connected to a reaction vessel for supplying microwave energy is provided. CONSTITUTION:As semiconductor reactive gas, silane is supplied from the port 28, and carrier gas such as hydrogen from the ports 27 and 26 according to necessity, and thus high frequency energy is supplied by a high frequency power source 15 by means of electrodes which compose a pair. A substrate is heated by a heater 12. The reactive gas flows along the surface to be formed of the substrate 2 from upward to downward, and then reaches a vacuum pump 37. A reaction vessel 7 possesses a peep window 8, a copper net for preventing electric wave leakage 49, and a quartz pipe for microwave supply 55, the wave guide 54, and a microwave power source 56 on the back side. They are so provided that electric fields of the reactive gasses 26, 27, 28 and the high frequency 15 are arranged in parallel along the surface to be formed of the substrate 2. In addition to the high frequency, microwave of frequency of 1GHz or more is supplied.

Description

【発明の詳細な説明】 本発明は基板上VcP型、1型およびN型の導電型を有
する非単結晶半導体を層状に積層して形成するに際し、
それぞれの半導体層をそれぞれに対応したプラズマ気相
反応用反応容器で形成せしめ、かつそれぞれの反応容器
を互いに連結して設けることにより、外気(大気)Kふ
れさせることなく半導体層を形成せしめるプラズマ気相
反応装置に関する。
DETAILED DESCRIPTION OF THE INVENTION When forming non-single crystal semiconductors having conductivity types of VcP type, 1 type and N type on a substrate by laminating them in layers, the present invention provides the following steps:
By forming each semiconductor layer in a corresponding plasma vapor phase application reaction vessel, and by connecting the reaction vessels to each other, a plasma vapor phase system that allows semiconductor layers to be formed without exposure to outside air (atmosphere) can be achieved. Relating to a reactor.

本発明は水素またはノーロゲン元素が添加された非単結
晶半導体層、好ましくは珪素、ゲルマニューム、炭化珪
素(EIiOのみではなく、本発明においては81xO
,−、lO< x≦1の総称を童味する)、珪化ゲルマ
ニューム(SiXGJ−a O<X/ 1)珪化スズ(
SixSn、−、IO<x/l)であって、この被膜中
に活性状態の水素またはハロゲン元素を充填することに
より、再結合中心密度の小さなP工およびN型の導電型
を有する半導体層を複数層形成し、その積層境界にて接
合例えばPN接合、P工接合、N工接合、PIN接合を
形成するとともに、それぞれの半導体層に他の隣接する
半導体層からの不純物が混入して接合特性を劣化させる
ことなく形成するとともニ、マたそれぞれに半導体層を
形成する工程間に大気特に酸素にふれさせて、半導体の
一部が酸化されることにより、層間絶縁物が形成される
ことのないようにした連続生産を行なうためのプラズマ
気相反応用製造装置に関する。
The present invention is directed to a non-single crystal semiconductor layer doped with hydrogen or a norogen element, preferably silicon, germanium, silicon carbide (not only EIiO but also 81xO in the present invention).
, -, lO< x≦1), germanium silicide (SiXGJ-a O<X/ 1) tin silicide (
By filling this film with hydrogen or a halogen element in an active state, a semiconductor layer having conductivity types of P type and N type with a small density of recombination centers can be formed. A plurality of layers are formed, and a junction such as a PN junction, a P-type junction, an N-type junction, or a PIN junction is formed at the lamination boundary, and impurities from other adjacent semiconductor layers are mixed into each semiconductor layer, causing the junction characteristics to deteriorate. It is possible to form an interlayer insulator without deteriorating the semiconductor layer by exposing it to the atmosphere, especially oxygen, during the process of forming the semiconductor layer on each of the two layers, which oxidizes a part of the semiconductor. The present invention relates to a plasma gas phase application manufacturing apparatus for continuous production that eliminates the need for production.

本発明は形成される半導体被膜がスパッタ(損傷)され
ることなく、さらに非単結晶半導体といえども基板上よ
シ結晶学的に成長(GROWTH)させるため、被形成
面に平行に反応性気体およびプラズマ発生用の電界を供
給せしめることを特徴としている。さらに本発明は反応
容器にマイクロ波(IGHz以上)を供給し、反応性気
体のプラズマ化率を高周波のみの0.1〜1%より20
〜70チに大きくすることにより、被膜の成長速度を5
〜8倍にすることで量産性の向上を計ることを特徴とし
ている。
In the present invention, the semiconductor film to be formed is not sputtered (damaged), and even non-single crystal semiconductors can be crystallographically grown (GROWTH) on the substrate. and supplying an electric field for plasma generation. Furthermore, the present invention supplies microwaves (IGHz or higher) to the reaction vessel to increase the plasma conversion rate of the reactive gas by 20% compared to 0.1 to 1% using only high frequency waves.
By increasing the size to ~70 cm, the growth rate of the film was increased by 5
It is characterized by improving mass productivity by increasing the capacity by ~8 times.

本発明はかかる不純物のtit人を防ぐため、P型半導
体層を形成させるための反応容器と、工型半導体J偏を
形成させるための反応容器と、N型半導体層を形成させ
るための反応容器とを有し、それぞれの反応容器を基板
上に41層させて形成する半導体層の積層順序に従って
、第1の予備室に連設して基板上((第1の半導体〕〈
を形成させるための反応容器を、さらにこの容器に連設
して第1の半導体層上に第2の半導体層を形成させるた
めの反応容器を連設し、以後同様にして反応容器を積層
する半導体層の数だけ連設したプラズマ反応用製造装置
に関する。
In order to prevent the formation of such impurities, the present invention provides a reaction vessel for forming a P-type semiconductor layer, a reaction vessel for forming a J-type semiconductor layer, and a reaction vessel for forming an N-type semiconductor layer. According to the stacking order of the semiconductor layers formed by forming 41 layers on the substrate, each reaction vessel is connected to the first preliminary chamber on the substrate ((first semiconductor)
A reaction vessel for forming a second semiconductor layer on the first semiconductor layer is further connected to the reaction vessel for forming a second semiconductor layer on the first semiconductor layer, and thereafter reaction vessels are stacked in the same manner. The present invention relates to a plasma reaction manufacturing apparatus that is connected in series to the number of semiconductor layers.

従来非単結晶半導体例えばアモルファス珪素のプラズマ
気相反応において、その製造装置の放電方式は13.5
6MHz等の高周波を平行平板型電極に供給し、その一
方の電極上に被形成面を有する基板を配置させたもので
あった0さらに応答器内に単に反応性気体のガス流を構
成させることなく供給する方式が知られている。しかし
この従来より知られている方式においては、被膜の成長
速度が1〜2A/秒と小さい。また基板を電極間に1ま
いのみ配置し、その−主面上のみに半導体層を形成する
0このため量産性が十分でなく、その代表的な応用例で
ある太陽電池を作製した時、その製造原価は1oan’
の基板の大きさK”[5000円をこえ、さらにその内
の4000円以上は設備償却費という全く非常識な現状
であった。
Conventionally, in the plasma vapor phase reaction of non-single crystal semiconductors such as amorphous silicon, the discharge method of the manufacturing equipment is 13.5
A high frequency such as 6 MHz is supplied to parallel plate electrodes, and a substrate having a surface to be formed is placed on one of the electrodes.Furthermore, a gas flow of reactive gas is simply formed in the responder. A method is known in which the amount of water is supplied without any damage. However, in this conventionally known method, the growth rate of the film is as low as 1 to 2 A/sec. In addition, the substrate is placed only once between the electrodes, and the semiconductor layer is formed only on the main surface of the substrate.For this reason, mass production is not sufficient, and when producing a solar cell, which is a typical application example. Manufacturing cost is 1oan'
The size of the board exceeded 5,000 yen, and more than 4,000 yen of that amount was equipment depreciation costs, which was completely absurd.

このため10 c m’の基板の大きさでその10〜3
0倍の生産性を同じ大きさの反応容器にて作製するため
の製造装置が強く求められていた。
Therefore, with a substrate size of 10 cm', 10 to 3
There is a strong need for a manufacturing device that can produce products with 0 times higher productivity using the same size reactor.

本発明はかかる目的を満たすためなされたものである。The present invention has been made to meet this objective.

半導体層rは単に真性の半導体のみではカくP型、N型
の半導体層を重ね合わせて接合を有することがその工学
的応用を広げるものであるOしかしかかる異種導電型の
半導体層を同一反応容器で作ることは、その生産性が向
上しても、それぞれの導電型用の不純物が互いに半導体
層内でスパッタ効果によシ混合してしまう。そのためP
N、P工、N工またはP工N接合を少なくとも1つ有す
る半導体層を複数層積層するに際し、その界面で接合を
十分構成させようとした時、それぞれの導電型用の反応
容器を前記したように独立分離せしめることがきわめて
重要である。
The semiconductor layer r cannot be formed by simply using an intrinsic semiconductor, but by superimposing P-type and N-type semiconductor layers and forming a junction, its engineering applications are expanded. Even if manufacturing in a container improves productivity, impurities for each conductivity type will mix with each other within the semiconductor layer due to the sputtering effect. Therefore P
When stacking a plurality of semiconductor layers having at least one N, P-type, N-type, or P-type N junction, when trying to form a sufficient junction at the interface, a reaction vessel for each conductivity type is prepared as described above. Therefore, it is extremely important to allow independent separation.

本発明はかかる分離独立方式に加えて、さらにその不純
物の混合を排除させ、接合特性の向上を計ったものであ
る。すなわち例えば1つのP工N接合を積層して形成さ
せようとする時、第1の半導体層としてのP型半導体層
を形成させfC場合、その半導体層の形成の際同時にこ
の不純物の吸着がおきる。本発明においてはこれら反応
容器の内壁からの再放出、また供給系、排気系からの一
度吸着した反応性気体の第2の半導体層の形成に際し離
脱し混入することを防ぐため、反応容器のみではなく、
反応性気体の供給系、排気系もそれぞれ独立に各反応容
器に対応して設けられ工いる。
In addition to such a separate and independent method, the present invention aims to improve the bonding characteristics by eliminating the mixing of impurities. That is, for example, when trying to form one P-N junction by laminating a P-type semiconductor layer as the first semiconductor layer, adsorption of this impurity occurs at the same time as the semiconductor layer is formed. . In the present invention, in order to prevent re-release from the inner wall of the reaction vessel, and to prevent the reactive gas once adsorbed from the supply system and exhaust system from separating and mixing when forming the second semiconductor layer, it is necessary to use only the reaction vessel. Without,
A reactive gas supply system and an exhaust system are also provided independently for each reaction vessel.

しかしさらにその不純物の混合のでライ17検討をすす
めた結果、これだけでは不十分であシ、さらに形成され
た第1の半導体層それ自体も不純物の混入源となり得る
ことが明らかになった。
However, as a result of further investigation into Lie 17 regarding the mixing of impurities, it became clear that this alone was not sufficient and that the formed first semiconductor layer itself could also be a source of impurity mixing.

そのためその上面に第2の半導体層を形成させようとす
る時、との下地に対し第2の半導体層を成長させ、下地
半導体層を反応性気体がすψi’Zするように被形成面
上に供給されてスパッタ効果を極力さけるととがきわめ
て重要であることが判明した。
Therefore, when a second semiconductor layer is to be formed on the upper surface, the second semiconductor layer is grown on the base layer, and the second semiconductor layer is grown on the surface to be formed so that the reactive gas flows through the base semiconductor layer. It has been found that it is extremely important to avoid sputtering effects as much as possible.

即ち被形成面に対し高周波電界が垂直に加えられた場合
、この電界によりプラズマ化された反応性気体が下地に
強く衝突する。このため第2の半導体層を積層している
時同時にその界面ではお互いが混合し合ってしまった。
That is, when a high frequency electric field is applied perpendicularly to the surface to be formed, the reactive gas turned into plasma by this electric field strongly collides with the base. For this reason, when the second semiconductor layers were being stacked, they mixed with each other at the interface.

その結果従来より知られた平行平板型電極の一方の電極
面に平行に被形成面を配向させる(すなわち電界は基板
表面に垂直)と、βとえ不純物の混合を独立反応容器方
式Kr排除しても十分でなくそのお互いの混合部は約1
000〜200OAもあることが判明した。
As a result, when the surface to be formed is oriented parallel to one electrode surface of the conventionally known parallel plate electrode (that is, the electric field is perpendicular to the substrate surface), the mixture of β and other impurities can be eliminated using the independent reaction vessel method. However, the mixing part is about 1
It turned out that there are also 000-200OA.

本発明はかかる欠点を防ぐため、独立分離反応方式であ
って、かつそのプラズマ反応に用いられる直流ま次は高
周波電界は被形成面に平行にしたこと、さらに反応性気
体を被形成面にそって流れるように供給させ、これらの
電流を加えることによシ、不純物の混合を排除し、その
混合部を200〜300A+!:約1/1o〜115に
するとことを特徴としている。
In order to avoid such drawbacks, the present invention uses an independent separation reaction method, and the DC and high frequency electric fields used for the plasma reaction are parallel to the surface to be formed, and the reactive gas is directed parallel to the surface to be formed. By applying these currents, the mixing of impurities is eliminated, and the mixing part is heated to 200 to 300 A+! : It is characterized in that it is approximately 1/1 o to 115 o.

かくすることにょセ、その接合またその近傍に集中して
いる再結合中心の密度を十分小さくさせることができた
。即ち再結合中心は不純物の混合によシアク七ブタ、ド
ナーにならない1価の不純物とv価の不純物が相互作用
して深いトラップレベルを作るが、かかるトラップセン
タ(再結合中心〕を混合部の厚さをうずくする仁とによ
ル少なくシ、また結晶学的に成長させることによシ赫半
導体の不対結合手の存在濃度を従来の10〜No am
よル約1/100の10″〜10″′am−’にしたこ
とを特徴としている。
In this way, it was possible to sufficiently reduce the density of recombination centers concentrated at or near the junction. In other words, the recombination center is formed by mixing impurities, and monovalent impurities that do not become donors interact with v-valent impurities to create a deep trap level. The concentration of dangling bonds in the semiconductor can be reduced from 10 to 100% by crystallographic growth.
It is characterized by having a diameter of about 1/100 of 10'' to 10'''am-'.

4  1” t971乙 また本発明はさらに反応性気体がY流1死z高周波(1
00KHg−>50MHz例えば13.56MEZ)K
拗で、そのイオン化率が1−以下であシ、大部分の反応
性気体は十分プラズマ化されない。
4 1" t971B Furthermore, the present invention further provides a method in which the reactive gas is
00KHg->50MHz e.g. 13.56MEZ)K
Since the ionization rate is less than 1, most of the reactive gas is not sufficiently converted into plasma.

それは例えばSi −H,5i−F、 C−、!(、N
−HXGθ−Hの結合を有する反応性気体(Eti)%
、Si焉、 ]I(、、、N馬Ge)9等において水素
の結合を切断するのに必要な周波数を供給しないことが
原因であることが判明した。即ち直流または品周波電淀
、tよ重い原子量の元素に対し運動エネルギ金供拾する
が、水素等の橙い元素に対し運動エネルギを十分供給し
ていない。このため本発明においてQよ、供給周波数を
Eli−H等の共振周波数゛またはそれに近いIGHz
以上のマイクロ波を供給し、プラズマイオン化率を40
〜′70%にまで高めることを特徴としている。この結
果、重い元素には共振周波数よセ十分低いため運動エネ
ルギを与えないため、被形成面上のスパッタ効果もなく
、またプラズマ化率が高いため、半嗜体被膜の成長速度
が3〜5倍にまで高めることができるという大きな特徴
を有していた〇 またマイクロ波エネルギのケ村に関しては、本発明人の
出願になる特許願(特願昭53−15288’7  E
l53.12. No出願)が知られている。
For example, Si-H, 5i-F, C-,! (,N
-HXGθ-H bond-bearing reactive gas (Eti)%
It has been found that the cause is that the frequency necessary to break hydrogen bonds is not supplied in ,Si, ]I(,,,NmaGe)9, etc. That is, direct current or high-frequency electric current supplies kinetic energy to elements with atomic weights heavier than t, but does not supply sufficient kinetic energy to orange elements such as hydrogen. Therefore, in the present invention, Q, the supply frequency is set to the resonance frequency of Eli-H, etc. or IGHz close to it.
Supplying microwaves with a plasma ionization rate of 40
It is characterized by increasing the temperature up to ~'70%. As a result, since the resonant frequency is sufficiently lower than the heavy element, kinetic energy is not applied to the heavy element, so there is no sputtering effect on the surface to be formed, and since the plasma conversion rate is high, the growth rate of the semi-dielectric film is 3 to 5. It had the great feature of being able to increase the energy by up to twice as much. Also, regarding microwave energy, a patent application filed by the present inventor (Japanese Patent Application No. 53-15288'7 E)
l53.12. (No application) is known.

しかしかかる方法においてはマイクロ波を反応容器の前
方に配置しているため、この前方において反応容器の内
壁に反応生成物が付着してしまう量が大きかった。この
ため本発明においては、反応容器内にランダムにマイク
ロ波の電優が供給されるように、容器自体に石英または
アルミナの窓を介し導波管を連続して設けたものである
。かくすることによシ、反応容器内に全体にマイクロ波
が供給され、そこでの反応性気体の活性化、イオン化を
促し、そのすぐ近くにぺ 配置された被膜の基板上に被¥形成をさせることができ
た。そのため供給反応性気体の被形成面上に形成される
半導体層に有効利用される半導体元素の量は従来1〜3
%であったものを、本発明においては20〜40% K
まで高めることができた。
However, in this method, since the microwave is placed in front of the reaction vessel, a large amount of reaction products adhere to the inner wall of the reaction vessel at this front. For this reason, in the present invention, a waveguide is continuously provided in the reaction container itself through a window made of quartz or alumina so that microwaves are supplied randomly into the reaction container. In this way, microwaves are supplied throughout the reaction vessel, promoting activation and ionization of the reactive gas therein, and forming a film on the substrate of the film disposed in the immediate vicinity. I was able to do that. Therefore, the amount of semiconductor element effectively used in the semiconductor layer formed on the surface on which the supplied reactive gas is formed is conventionally 1 to 3.
%, in the present invention it is 20-40% K
I was able to raise it to

以下に本発明の実施例を図面に従って説明する。Embodiments of the present invention will be described below with reference to the drawings.

実施例1 第1図に従って本発明のプラズマ気相反応装置の実施例
を説明する。
Example 1 An example of the plasma vapor phase reactor of the present invention will be described with reference to FIG.

この図面はP工接合、N工接合、PN接合、P工N接合
、P工N工P接合、N工P工N接合またはP工NPIN
・、@−PIN接合等の基板上の半導体に異種導電型ま
たは同種導電型の半導体層をそれぞれの半導体層をその
前に形成された半導体層の影響を受けることを防ぐため
、前の半導体層を形成した反応容器に連設した他の独立
した反応容器で第2の半導体層を形成して、前の半導体
層上に積層して接合を作るとともに、さらに多層に自動
かつ連続的に形成するための装置である。
This drawing is for P-work joint, N-work joint, PN joint, P-work N joint, P-work N-work P joint, N-work P-work N joint, or P-work NPIN.
・In order to prevent each semiconductor layer from being influenced by the semiconductor layer formed before it, a semiconductor layer of a different conductivity type or the same conductivity type is added to a semiconductor on a substrate such as an @-PIN junction. A second semiconductor layer is formed in another independent reaction vessel connected to the reaction vessel in which the second semiconductor layer was formed, and is laminated on the previous semiconductor layer to form a bond, and further layers are automatically and continuously formed. It is a device for

図面においては特KP工N接合を3つの半導体層を積層
して形成するプラズマ気相反応装置の装置例を示す。
The drawings show an example of a plasma vapor phase reactor in which a special KP N-junction is formed by laminating three semiconductor layers.

図面における3つの各反応容器(6)、(7)、(Eり
はそれぞれ独立して反応性気体の導入手段αi、(1e
、ct→と排気手段(イ)〃、に)とを有し、反応性気
体が供給系またけ排気系から逆流または混入することを
も防いでいる。
Each of the three reaction vessels (6), (7), and
, ct→ and exhaust means (a), ni) to prevent reactive gases from flowing backward or mixing from the supply system or the exhaust system.

この装置は入口側には第1の予備室(5)が設けられ、
とびら02)よυボート (図示せず〕上に基板(4)
、(4)を挿着し、この予備室に配置させた。
This device has a first preliminary chamber (5) on the entrance side,
Door 02) Board (4) on top of the boat (not shown)
, (4) were inserted and placed in this preliminary chamber.

さらにこの予備室(5)を真空ポンプ(35)Vcて真
空引をした。この被形成面を有する基板は裏面を互いに
接し、3〜5cmの間隙を有して林立させている。この
後予め真空引がされている反応容器(6)、())メ8
)にゲート弁(44)を開けて基板、ボートをプラズマ
反応容器(6)に移し、さらにゲート弁(44)を閉じ
ることによ)移動させたものである。
Furthermore, this preliminary chamber (5) was evacuated using a vacuum pump (35) Vc. The substrates having the formation surfaces are arranged in a row with their back surfaces in contact with each other with a gap of 3 to 5 cm. After this, the reaction vessels (6), ()), which have been evacuated in advance, are
), the gate valve (44) was opened, the substrates and the boat were transferred to the plasma reaction vessel (6), and then the gate valve (44) was closed).

この時反応容器(6)の基板(1)は反応容器(1)に
、また反応容器(7)の基板(1)は反応容器(8) 
K 、また反応容器(8)の基板は第2の出口側の予備
室(9)K同時にゲート弁(45) (46) (4″
Qを開けて移動される。
At this time, the substrate (1) of the reaction vessel (6) is attached to the reaction vessel (1), and the substrate (1) of the reaction vessel (7) is attached to the reaction vessel (8).
K, and the substrate of the reaction vessel (8) is connected to the second outlet side preliminary chamber (9) K at the same time as the gate valve (45) (46) (4″
Q is opened and moved.

ツノ 第2の予備室に移された基板はゲート弁07)が閉られ
た後(41)よシ窒素が導入されて大気圧にされ、(4
つのとびらよシ外に出される。
After the gate valve 07) is closed, nitrogen is introduced into the substrate transferred to the second preliminary chamber (41), and the pressure is brought to atmospheric pressure (41).
One door is taken outside.

即ちゲート弁の動きはとびら(42)、 (43)が大
気圧で開けられた時はゲート弁(44) 、 (45)
 、 (46) 、σηは閉じられ、また逆にとびら(
42) (43)が閉じられていて予備室(5)、(9
)が十分真空引された時はゲート弁(4す(45) (
46) (t′1)が開く機構を有してい7   2 
  2 る0 系IKおける第1の反応容器(6)でのP型半導ましく
は0.01〜’1torrとした。
In other words, the movement of the gate valve is the gate valve (44), (45) when the door (42) and (43) are opened at atmospheric pressure.
, (46), ση is closed, and conversely, the door (
42) (43) is closed and the preliminary room (5), (9
) is sufficiently evacuated, the gate valve (4s (45) (
46) (t'1) has an opening mechanism 7 2
The P-type semiconductor in the first reaction vessel (6) in the 2 Ru0 system IK was set to 0.01 to '1 torr.

反応性気体は珪化物気体(ハ)に対してはシラン(si
 n L、、1% K S i B、) %ジクロール
シラン(El IHLOQトリクロールシラン(SiH
Cl、)、四フッ化珪素(stlS)等があるが、取扱
いが容易なシランを用いた。価格的にはジクロールシラ
ンの方が安価であυ、これを用いてもよい0 本実施例の5iXOr−JO<X(1)を形成するため
炭化物気体α1に対してはメタン(O)Q、エタン(C
刃、プロパン<ah〜のような炭化水素であつても、ま
た四塩化炭素(aaQのような塩化炭素であってもよい
The reactive gas is silane (si) for silicide gas (c).
n L,, 1% K S i B,) % dichlorosilane (El IHLOQ trichlorosilane (SiH
Cl, ), silicon tetrafluoride (stlS), etc., but silane, which is easy to handle, was used. In terms of price, dichlorosilane is cheaper υ, and it may be used.0 In order to form 5iXOr-JO<X(1) in this example, methane (O)Q , ethane (C
The blade may be a hydrocarbon such as propane<ah~ or a carbon chloride such as carbon tetrachloride (aaQ).

炭化珪素に対しては、P型の不純物としてボロンをジボ
ランによシ、またガリュームをTMG(Ga (a瘍)
 KよI) 10〜9X10 cmの濃度に々るように
加えた。本実施例ではTMGを用い、GaをP型用不純
物とし1、また01−を8 i x O1−Jl (0
< xt 1)用K(ハ)より供給した。
For silicon carbide, boron is replaced with diborane as a P-type impurity, and gallium is replaced with TMG (Ga (a tumor)).
K and I) were added to a concentration of 10-9 x 10 cm. In this example, TMG is used, Ga is used as a P-type impurity, 1, and 01- is 8 i x O1-Jl (0
< xt 1) Supplied from K (c).

した。これらの反応性気体はそれぞれの流量用G53)
およびバルブ(3りをへて反応容器(6)K供給させた
。反応系は最初容器の内壁表面に付着した酸素等を30
0〜500°Oに加熱して除去した。
did. These reactive gases have their respective flow rates G53)
and a valve (3) to supply K to the reaction vessel (6).The reaction system initially removed oxygen etc. attached to the inner wall surface of the vessel at
It was removed by heating to 0-500°O.

基板を100〜400°C例えば200°Cにヒータ0
1)Kよシ加熱した。この後との容器に前記した反応性
気体を導入し、所定の圧力例えばO,1torrとし、
さらに10〜50Wに高周波エネルギαl(供給してプ
ラズマ反応をおこさせた。
Heat the substrate to 100 to 400°C, for example 200°C, using a heater of 0.
1) Heat in K. After this, the above-mentioned reactive gas is introduced into the container, and the predetermined pressure is set to O, 1 torr, for example.
Further, high frequency energy αl (10 to 50 W) was supplied to cause a plasma reaction.

このP型半導体層はこの反応系Iで形成されるが、約1
0OAの厚さを有する薄膜であるが、炭化珪素は一般に
珪素のみに比べて大きな高周波エネルギを必要とする。
This P-type semiconductor layer is formed by this reaction system I, and about 1
Although a thin film with a thickness of 0 OA, silicon carbide generally requires more radio frequency energy than silicon alone.

しかしこの場合その被形成面である透明導電膜はきわめ
てスノシツタされやすく、酸化スズが14スズに変わっ
て透明でなく白濁しやすい。
However, in this case, the transparent conductive film, which is the surface on which it is formed, is extremely easily smeared, and the tin oxide is replaced by 14 tin, making it apt to become cloudy instead of transparent.

しかしこの実施例に示される示く、プラズマ電界を被形
成面に平行にすると、この電界による反応生成物は表面
にそって移動するため、スパッタ効果による白濁化は3
0〜50W加えても見られず、垂直電界の場合が2〜5
Wが限界だったことに比べて製造歩留シを向上させた○
基板は導体基板(ステンレス、チタン、窒化チタン、そ
の他の金属)、半導体(珪素、炭化珪素、ゲルマニュー
ム)、絶縁体(アルミナ、ガラス、有機物質)または複
合基板(ガラス絶縁基板上に酸化スズ、工TO等の導電
膜が単層またはITO上KSnOLが形成された2層膜
が形成されたもの、絶縁基板上に選択的に導体電極が形
成されたもの、絶縁基板上Kl’またはN型の半導体が
形成されたもの)を用いた。本実施例のみならず本発明
のすべてにおいてこれらを総称して基板という。もちろ
んこの基板は可曲性であってもまた固い板であってもよ
い。
However, as shown in this example, when the plasma electric field is made parallel to the surface to be formed, the reaction products due to this electric field move along the surface, so the clouding due to the sputtering effect is reduced by 3.
It is not seen even when 0 to 50 W is applied, and 2 to 5 in the case of vertical electric field.
Improved manufacturing yield compared to W, which was at its limit○
Substrates are conductor substrates (stainless steel, titanium, titanium nitride, and other metals), semiconductors (silicon, silicon carbide, germanium), insulators (alumina, glass, organic materials), or composite substrates (tin oxide, engineered, etc. on glass insulating substrates). Those with a single layer of conductive film such as TO or a double layer of KSnOL on ITO, those with conductive electrodes selectively formed on an insulating substrate, and Kl' or N-type semiconductors on an insulating substrate. was formed). These are collectively referred to as a substrate not only in this embodiment but also in all of the present invention. Of course, this substrate may be flexible or a rigid plate.

以下の実施例においてはガラス基板上に透明導電膜が形
成された基板上KP型型半体体層約’100A)、工型
半導体層(約5000A)、N型半導体層(約20 O
A)を形成する部会を詳述する。
In the following examples, a transparent conductive film is formed on a glass substrate, and a KP-type half body layer (approximately 100A), a semiconductor layer (approx.
The subcommittees forming A) will be explained in detail.

第1図に示した反応系におhて、プラズマグ日−放電法
を用い特KP型半導体層は広いKgとするため、炭化珪
素半導体を形成し、その他に珪素膜を形成したものであ
る。基板(1)はポート (例えば石英)(2)K対し
て林立させた。
In the reaction system shown in FIG. 1, a silicon carbide semiconductor was formed and a silicon film was formed in addition to a silicon carbide semiconductor layer in order to make the special KP type semiconductor layer have a wide Kg using the plasma-magnetic discharge method. The substrate (1) is lined with ports (eg quartz) (2) K.

基板は200μ〜2mmの厚さの1ocm’を本実施例
においては用いた。この基板を反応容器(6)K封じた
。この反応容器は1〜20MHK、特K 13.56M
Hzの高周波発生源αゆの高周波エネルギを1対を成す
電極aの、に6 Kよシ反応性気体を励起、反応または
加熱できるよう収している。この電極07)は反応性気
体@、(ハ)戸の導入口を、また電極(イ)は排出口を
兼ねている。さらにその外側に抵抗加メf 熱または赤外線イメーグKKよるヒータ0])を設置し
ている0排気はノ(ルプ(34)を経て、真空ポンプ(
30)を経てなされる。反応性気体は電極0りの下方の
1mHの開穴が多数あけられて電極の穴よシ噴出し基板
(1)の被形成面と平行方向の電界を有する高周波誘導
エネルギによυプラズマ化される。
In this example, a substrate having a thickness of 200 μm to 2 mm and a thickness of 1 ocm was used. This substrate was sealed in a reaction container (6)K. This reaction container is 1~20MHK, special K 13.56M
High frequency energy from a high frequency source α of Hz is stored in a pair of electrodes a to a temperature of 6 K so as to excite, react or heat a reactive gas. This electrode 07) serves as an inlet for the reactive gas @(c), and the electrode (a) also serves as an outlet. Furthermore, a heater (heater by heat or infrared imaging KK) is installed on the outside of the exhaust.
30). A large number of 1 mH holes are made below the electrode, and the reactive gas is ejected through the holes of the electrode and turned into υ plasma by high-frequency induction energy with an electric field parallel to the formation surface of the substrate (1). Ru.

かくして1〜5分間プラズマ反応をさせて、P型不純物
としてガリュームが添加された炭化珪素膜を作製した。
In this manner, a plasma reaction was performed for 1 to 5 minutes to produce a silicon carbide film to which gallium was added as a P-type impurity.

さらにこの第1の半導体層上に基板を前記した操作順序
に従って第2の反応容器(1)K移動し、ここで真性の
半導体層を約500OAの厚さに形成させた。
Further, the substrate was transferred onto the first semiconductor layer to a second reaction vessel (1) K according to the above-described operating sequence, and an intrinsic semiconductor layer was formed therein to a thickness of about 500 OA.

すなわち第1図における反応系Hにおいて、半導体の反
応性気体としてシランを(ハ)より、また水素等のギヤ
リアガスを必要に応じて@(ハ)よシ供給して、一対を
構成する電極(Ill HKて系■と同様に高周波電源
αυよシ13.56MH2の高周波エネルギを供給した
。基板は250°CKヒータ(ロ)r(よシ加熱した。
That is, in the reaction system H in FIG. Similarly to the HK system (2), high frequency energy of 13.56 MH2 was supplied from a high frequency power source αυ.The substrate was heated to 250° by a CK heater (2).

反応性気体は基板(2)の被形成面にそって上方よシ下
方に流れ、真空ポンプ(3″QK至る。系■において0
3)の出口側よシみたたて断面図を第2図に示す。
The reactive gas flows upward and downward along the formation surface of the substrate (2), reaching the vacuum pump (3″QK).
Fig. 2 shows a vertical cross-sectional view of 3) from the outlet side.

第2図を概説する。Figure 2 is outlined.

第2図において反応容器(7)はのぞき窓(4B)電波
漏えい防止用銅網(49)、裏側にマイクロ波供給用の
石英窓(55)導波管(54)マイクロ波電源(56)
を具備している。基板(2)の被形成面にそって平行に
反応性気体(ハ)、@索および高周波0啼の電界が配さ
れるように設は工ある。
In Figure 2, the reaction vessel (7) has a viewing window (4B), a copper mesh for preventing radio wave leakage (49), a quartz window for microwave supply on the back side (55), a waveguide (54), and a microwave power source (56).
Equipped with: The arrangement is such that a reactive gas (c), a wire, and a high frequency electric field are arranged parallel to the surface of the substrate (2) to be formed.

さらに高周波匠加えてhOHz以上の周波数例えば2.
45GHzのマイクロ波が供給されている。
Furthermore, in addition to high frequency waves, frequencies higher than hOHZ, such as 2.
45GHz microwave is supplied.

被膜の成長速度は第3図に示しであるが、マイクロ波エ
ネルギと高周波エネルギとを加えた場合は(61)、マ
イクロ波エネルギのみでは(6狙訣高周波エネルギのみ
の場合には(6りが得られた。また基板に単に抵抗加熱
のみしたのでは珪素半導体被膜は成長しないことがわか
った。
The growth rate of the film is shown in Figure 3. When microwave energy and high-frequency energy are added (61), when microwave energy alone is used (6 points), when high-frequency energy is used alone (61) It was also found that a silicon semiconductor film did not grow if the substrate was simply subjected to resistance heating.

加えて図面よシ明らかな如く、マイクロ波エネルギによ
る励起はその成長速度を州加させるのに効果がきわめて
ちることがわかった。
In addition, as is clear from the drawings, excitation by microwave energy was found to be extremely effective in increasing the growth rate.

図面で250°Oにおいて1. OA/秒を(66)で
得たが、マイクロ波のみ200W加えた場合(65)が
、またそれに品周波電界を1OW加えると(64)が得
1られその成長速度は7倍になっていることがわかった
。このため従来に比べてマイクロ波を併用すると多量生
産性がきわめてすぐれ、またマイクロ波は500W以上
加えても被膜のスノ(ツタ効果がみられず、例えばガラ
ス表面部KI層のみを作っておくと2〜1ox1o−’
 (介c m)’の先広導度(AM工にて)また1 0
−’ 〜10−’ (Ac m)’の喧伝導度を得、き
わめて理想的な1層を作ることができ念。
1. At 250°O in the drawing. OA/sec was obtained from (66), but when only microwaves were applied at 200 W, (65) and when a product frequency electric field was added at 1 OW, (64) was obtained, and the growth rate was 7 times as high. I understand. For this reason, compared to conventional methods, when microwaves are used in combination, mass productivity is extremely high, and even when microwaves are applied at 500 W or more, no ivy effect is observed on the coating. 2~1ox1o-'
(intervention cm)''s leading conductivity (at AM engineering) and 1 0
I am confident that I was able to obtain a conductivity of ~10-' (Ac m)' and create an extremely ideal layer.

tiこの実施例においては、P型用不純物を多く再放出
しにくいガリュームを用いたこと、また特に本発明が基
板表面をスパッタさせないため、その界面は従来の10
00〜200OAの厚さではなく、100〜20OAの
厚さしかなかった0これはP層の不純物を10“°CC
10し、1層中のドーピングがlXl0  am Kな
るまでの才として工MA(イオン マイク=−fロープ
 アナライザ)によって調べた結果である。
In this example, gallium, which contains many P-type impurities and is difficult to re-emit, was used, and in particular, since the present invention does not sputter the substrate surface, the interface was different from the conventional 10
Instead of having a thickness of 00-200OA, it was only 100-20OA thick.
10, and this is the result of an investigation using an MA (ion microphone = -f rope analyzer) to determine the doping in one layer until it reaches lXl0 am K.

またかくして工型半導体層を系■にて約500OAの厚
さに形成させた後、基板は前記した操作に従って系■の
反応容器(8)に移され、N型半導体層が形成された0
このN型半導体層には、第1図においてフオスヒンをP
■/日ta、 1.0% トシ(31)よシまたシラン
を(30)より、またキャリアガスを(イ)よシ供給し
、系Iと同様にして200Aの厚さKN型半導体層を形
成させたものでちる0かくして第2の4渚−t(9)よ
シ外KP工N接合を構成して出された基板上にアルミニ
ューム電極を真空蒸着法によシ約1μの厚さに作シ、ガ
ラス基板上に(工TO+日句裏面電極(PIN半導体)
(A1裏面電極)を構成させた。
Furthermore, after forming the N-type semiconductor layer to a thickness of about 500 OA in System (1), the substrate was transferred to the reaction vessel (8) of System (2) according to the operations described above, and an N-type semiconductor layer was formed thereon.
In this N-type semiconductor layer, phosphine is added to P as shown in FIG.
■/day ta, 1.0% Toshi (31), silane (30) and carrier gas (A) were supplied, and a KN type semiconductor layer with a thickness of 200A was formed in the same manner as in System I. Thus, after forming the second 4-t(9) outer KP-N junction, aluminum electrodes were formed on the resulting substrate by vacuum evaporation to a thickness of approximately 1 μm. Made on a glass substrate (TO + back electrode (PIN semiconductor))
(A1 back electrode) was constructed.

その光電変換装置としての特性は10〜12%平均11
チをAM工(100mW/c rn) Kて有し、ノ1
イブリッド型にした10cmにおいても8〜9%ヲ真性
効率で得ることができた。この効率の向上は乙が入射す
る側のP工接合がきわめて本8幼に構成され、捷だアモ
ルファス半導体等の非単結晶半導体においても、P型半
導体層上に工型半導体層を成長積層させたことによるも
ので、また開放電圧は0.88〜0.9vであったが、
短絡電流は20〜22 mA/c mLと大きく、まi
FFも0.70〜0.18と犬きく、PIN型の半導体
層内部における再結合中心の密度が従来の方法に比べ1
/10〜1150になったことによる電流増加が大きな
特性改良につながったものと推定される。
Its characteristics as a photoelectric conversion device are 10 to 12% on average 11
It has AM process (100mW/crn) K, No. 1
Even in the 10 cm hybrid type, it was possible to obtain an intrinsic efficiency of 8 to 9%. This improvement in efficiency is due to the fact that the P-type semiconductor layer on the P-type semiconductor layer is grown and stacked on the P-type semiconductor layer, even in non-single-crystal semiconductors such as thin amorphous semiconductors. This was due to the fact that the open circuit voltage was 0.88 to 0.9v,
The short circuit current is large at 20-22 mA/c mL, and
The FF is also very high at 0.70 to 0.18, and the density of recombination centers inside the PIN type semiconductor layer is 1% compared to the conventional method.
It is presumed that the increase in current due to the change in current from /10 to 1150 led to a large improvement in characteristics.

かくの如く本発明のプラズマ反応装置は形成される半導
体において生産性を10〜30倍も向よさせ、また特性
も従来の5〜8チの変換効率に比べ30チも向上させる
きわめて独創的なものである。
As described above, the plasma reactor of the present invention is an extremely original device that improves the productivity of formed semiconductors by 10 to 30 times, and also improves the conversion efficiency by 30 times compared to the conventional 5 to 8 inches. It is something.

P工NP工Nl111・・P工Nのタンデム構造の光電
変換装置等多くの応用も本発明においては可能である0 本発明において形成される非単結晶半導体被膜中の結晶
構造がアモルファスであれ多結晶であれ、その構造には
制限を受けない。本発明は形成された複数の積層された
半導体被膜がP型、N型または1型を少なくともP工、
PNまたはN工接合をひとつ有する半導体であるととが
重要である。またとの半導体としての導電特性のリーク
特性の軽減のため、その接合面においてそれぞれを混合
させないことが大きな特徴である。
Many applications such as a photoelectric conversion device with a tandem structure of P/NP/N111...P/N are also possible in the present invention. Even if the crystal structure in the non-single crystal semiconductor film formed in the present invention is amorphous, it Even if it is a crystal, there are no restrictions on its structure. The present invention provides that the plurality of laminated semiconductor films formed are at least P-type, N-type or 1-type.
It is important that the semiconductor has one PN or N-type junction. In order to reduce the leakage characteristics of conductive properties as a semiconductor, a major feature is that they are not mixed at the junction surface.

さらにこの珪素または炭素の不対結合手を水素によ#)
S i−H,O−HKて中和するのではなく81−01
.0−01とノ10ゲン化物特に塩化性気体を用いて実
施してもよいことはいうまでもなくこの濃度は10モル
チ以下、例えば2〜5モルチが好ましかった。
Furthermore, this dangling bond of silicon or carbon is replaced with hydrogen)
81-01 instead of neutralizing with S i-H, O-HK
.. It goes without saying that the reaction may be carried out using 0-01 and 10 genides, especially chlorinated gases, and the concentration is preferably 10 molar or less, for example 2 to 5 molar.

形成させる半導体の種類に関しては、実施例IK示した
が、■族の81、Ge、Elix(3,−、(0<xt
 1)、51xae、、 (6<+c、<1) 、5i
XSn、−JOイX”)のみではなく、これ以外K G
aAa、 GaAlAs、 BP、 Ode等の化合物
半導体であってもよいことはいうまでもない0 本発明で形成された炭化珪素被膜に対しフォトエッチ技
術を用いて選択的にPまたはN型の不純物を混入または
拡散してPN接合を部分的に作シ、との接合を利用して
トランジスタ、ダ作ってもよい。特に光入射元側のエネ
ルギノ(ンド巾を大きくしたベテロ接合構造を有するい
わゆるW−N QFi’T)E TONALLOW)と
各反応室にて導電型のみではなく生成物を異ならせてそ
れぞれ独立して作製して積層させることが可能になシ、
工業的にきわめて重要なものであると信する。
Regarding the type of semiconductor to be formed, Example IK is shown, but 81, Ge, Elix (3, -, (0<xt
1), 51xae, (6<+c, <1), 5i
Not only XSn, -JOi
It goes without saying that compound semiconductors such as aAa, GaAlAs, BP, and Ode may also be used. P or N type impurities are selectively added to the silicon carbide film formed by the present invention using photoetching technology. It is also possible to partially create a PN junction by mixing or diffusing it, or to create a transistor by using the junction. In particular, in the energy source side of the light incidence side (so-called W-N QFi'T)E TONALLOW which has a beterojunction structure with a large bond width) and in each reaction chamber, not only the conductivity type but also the product is different, and each It is now possible to fabricate and laminate
We believe that it is extremely important industrially.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明を実施するための半導体膜形成
用製造装置の概略を示す。 第3図は第1図の製造装置によって得られた珪素半導体
被膜の特性である。 37 砲2図 私3 目
1 and 2 schematically show a manufacturing apparatus for forming a semiconductor film for carrying out the present invention. FIG. 3 shows the characteristics of the silicon semiconductor film obtained by the manufacturing apparatus shown in FIG. 37 Gun 2 Figure I 3rd

Claims (1)

【特許請求の範囲】[Claims] ■、1気圧以下の減圧状態に保持された反応系における
基板上の被形成面上K、P型)1型およびN型の導電型
の非単結晶半導体層を積層して接合を構成する半導体を
形成せしめるため、P型半導体層を形成させるための反
応容器と、■型半導体層を形成させるための反応容器と
、N型半導体層を形成させるだめの反応容器とを具備し
、前記それぞれの反応容器には反応性気体の導入系と反
応生成物を真空排気するための排気系とを有し、前記反
応容器を互いに連設するとともに、前記反応容器の一方
の側および他方の側に第1および第2の予備室を連設し
、前記反応室および予備室の連設部には前記それぞれの
反応容器に導入される反応性気体がプラズマ気相反応中
に互いに混入することを防ぐゲート弁が設けられたプラ
ズマ気相反応装置において、反応性気体の流れ方向は前
記被形成面に平行に配向して供給されるとともに、マイ
クロ波エネルギ供給用の前記反応容器に連結した導波管
を具備することを特徴とするプラズマ気相反応装置。
■, A semiconductor in which a junction is formed by laminating non-single crystal semiconductor layers of type 1 and type N (K, P type) on the formation surface of the substrate in a reaction system maintained at a reduced pressure of 1 atmosphere or less. , a reaction vessel for forming a P-type semiconductor layer, a reaction vessel for forming a ■-type semiconductor layer, and a reaction vessel for forming an N-type semiconductor layer are provided. The reaction vessel has a reactive gas introduction system and an exhaust system for evacuating the reaction product, and the reaction vessels are connected to each other, and gas pipes are provided on one side and the other side of the reaction vessel. A first and a second preparatory chamber are arranged in series, and a gate is provided in the continuous part of the reaction chamber and the preparatory chamber to prevent the reactive gases introduced into the respective reaction vessels from mixing with each other during the plasma gas phase reaction. In a plasma gas phase reactor equipped with a valve, the flow direction of the reactive gas is oriented parallel to the formation surface, and a waveguide connected to the reaction vessel for supplying microwave energy is provided. A plasma gas phase reaction device comprising:
JP57126049A 1982-07-19 1982-07-19 Plasma vapor reaction device Granted JPS5916329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57126049A JPS5916329A (en) 1982-07-19 1982-07-19 Plasma vapor reaction device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57126049A JPS5916329A (en) 1982-07-19 1982-07-19 Plasma vapor reaction device

Publications (2)

Publication Number Publication Date
JPS5916329A true JPS5916329A (en) 1984-01-27
JPH0522375B2 JPH0522375B2 (en) 1993-03-29

Family

ID=14925378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57126049A Granted JPS5916329A (en) 1982-07-19 1982-07-19 Plasma vapor reaction device

Country Status (1)

Country Link
JP (1) JPS5916329A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0620971A (en) * 1992-06-30 1994-01-28 Canon Inc Method of forming deposit film and optical electromotive element and method of continuously manufacturing optical electromotive element
US5326404A (en) * 1991-12-19 1994-07-05 Sony Corporation Plasma processing apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578524A (en) * 1978-12-10 1980-06-13 Shunpei Yamazaki Manufacture of semiconductor device
JPS5628637A (en) * 1979-08-16 1981-03-20 Shunpei Yamazaki Film making method
JPS5772317A (en) * 1980-10-24 1982-05-06 Semiconductor Energy Lab Co Ltd Manufacture of covering film

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578524A (en) * 1978-12-10 1980-06-13 Shunpei Yamazaki Manufacture of semiconductor device
JPS5628637A (en) * 1979-08-16 1981-03-20 Shunpei Yamazaki Film making method
JPS5772317A (en) * 1980-10-24 1982-05-06 Semiconductor Energy Lab Co Ltd Manufacture of covering film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5326404A (en) * 1991-12-19 1994-07-05 Sony Corporation Plasma processing apparatus
JPH0620971A (en) * 1992-06-30 1994-01-28 Canon Inc Method of forming deposit film and optical electromotive element and method of continuously manufacturing optical electromotive element

Also Published As

Publication number Publication date
JPH0522375B2 (en) 1993-03-29

Similar Documents

Publication Publication Date Title
JPS6029295B2 (en) Non-single crystal film formation method
US6946404B2 (en) Method for passivating a semiconductor substrate
JPH07263734A (en) Photovoltaic device
JPS6043819A (en) Method for vapor-phase reaction
US6103138A (en) Silicon-system thin film, photovoltaic device, method for forming silicon-system thin film, and method for producing photovoltaic device
JPS5916329A (en) Plasma vapor reaction device
JPS5916328A (en) Plasma vapor reaction device
JPS5825226A (en) Plasma cvd unit
Chae et al. Ultrafast deposition of microcrystalline Si by thermal plasma chemical vapor deposition
JP7400389B2 (en) Silicon carbide polycrystalline film, silicon carbide polycrystalline film manufacturing method, and silicon carbide polycrystalline film forming apparatus
JPS5952833A (en) Plasma vapor reactor
JPH03183125A (en) Method for plasma vapor-phase reaction
JPH0436448B2 (en)
JP2805611B2 (en) Coating method
CN112955413B (en) Method for producing coated glass substrates
JP2802747B2 (en) Plasma processing method
JPS5952835A (en) Plasma vapor reactor
JPH01157520A (en) Plasma vapor reaction
JPH06267870A (en) Method and device for forming deposit film
JPH0732141B2 (en) Carbon film production method
JP3062470B2 (en) Coating method
JPH08274036A (en) Formation of vapor phase reaction film
JPH0499313A (en) Amorphous silicon thin film and its manufacture
JPH0344148B2 (en)
JPH0532473B2 (en)