JPS5952750U - Filter for multiplex demodulation integrated circuit - Google Patents
Filter for multiplex demodulation integrated circuitInfo
- Publication number
- JPS5952750U JPS5952750U JP14721582U JP14721582U JPS5952750U JP S5952750 U JPS5952750 U JP S5952750U JP 14721582 U JP14721582 U JP 14721582U JP 14721582 U JP14721582 U JP 14721582U JP S5952750 U JPS5952750 U JP S5952750U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- filter
- demodulation integrated
- switched capacitor
- multiplex demodulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るＰＬＬによるステレオ・マルチプ
レックス復調回路路ＩＣとスイッチド・キ ゛ヤパ
シタ・フィルタとのブロック図である。
２・・・・・・位相比較器、５・・・・・・電圧制御発
振器、６・・・・・・１７２分周器、７・・・・・・１
／２分周器、８・・・・・・スイッチング復調器、９・
・・・・・第１のスイッチド・キャパシタ・フィルタ、
１０・・・・・・第２のスイッチド・キャパシタ・フィ
ルタ、１１・・・・・・第３のスイッチド・キャパシタ
・フィルタ、１２・・・・・・第４のスイツチド・キャ
パシタ・フィルタ、１３・・・・・・第５のスイッチド
φキャパシタ・フィルタ、１５・・・・・・ＰＬＬによ
るステレオ会マルチプレックス復調集積回路。FIG. 1 is a block diagram of a PLL-based stereo multiplex demodulation circuit IC and a switched capacitor filter according to the present invention. 2...Phase comparator, 5...Voltage controlled oscillator, 6...172 frequency divider, 7...1
/2 frequency divider, 8...Switching demodulator, 9.
...first switched capacitor filter,
10... Second switched capacitor filter, 11... Third switched capacitor filter, 12... Fourth switched capacitor filter, 13...Fifth switched φ capacitor filter, 15...Stereo multiplex demodulation integrated circuit using PLL.
Claims (1)
るステレオ・マルチプレックス復調集積回路の前段及び
後段に用いるフィルタにおいて、該復調集積回路の前段
に直列に設けられたアンチバーディ−ノイズを取除く第
１のスイッチド・キャパシタ・フィルタと、該復調集積
回路の後段に直列に設けられた前記副搬送波の３３ＫＨ
ｚの信号を取除く第２、第３のスイッチド・キャパシタ
・フィルタとｌ ９ＫＨｚのパイロット信号を取除り第
４、第５のスイッチド・キャパシタ・フィルタとからな
り、該スイッチド・キャパシタ・フィルタ群は該フェー
ズ・ロックド・ループによるステレオ・マルチプレック
ス復調集積回路に用いられている電圧制御発振器の出力
信号の発振周波数をサンプリング周波数として用いるこ
とを特徴とするフェーズ・ロックド・ループによるステ
レオ会マルチプレックス復調集積回路用フィルタ。In a filter used in the front and rear stages of a stereo multiplex demodulation integrated circuit that generates subcarriers using a phase-locked loop, a first filter for removing antibirdie noise provided in series in the front stage of the demodulation integrated circuit 33KH of the subcarrier provided in series after the demodulation integrated circuit.
It consists of second and third switched capacitor filters that remove the z signal, and fourth and fifth switched capacitor filters that remove the 9 KHz pilot signal, and the switched capacitor filter The filter group uses the oscillation frequency of the output signal of the voltage controlled oscillator used in the phase-locked loop stereo multiplex demodulation integrated circuit as the sampling frequency. Filter for plex demodulation integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14721582U JPS5952750U (en) | 1982-09-30 | 1982-09-30 | Filter for multiplex demodulation integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14721582U JPS5952750U (en) | 1982-09-30 | 1982-09-30 | Filter for multiplex demodulation integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5952750U true JPS5952750U (en) | 1984-04-06 |
Family
ID=30327443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14721582U Pending JPS5952750U (en) | 1982-09-30 | 1982-09-30 | Filter for multiplex demodulation integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5952750U (en) |
-
1982
- 1982-09-30 JP JP14721582U patent/JPS5952750U/en active Pending
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