JPS5951556A - Encasing vessel for semiconductor device - Google Patents
Encasing vessel for semiconductor deviceInfo
- Publication number
- JPS5951556A JPS5951556A JP16256282A JP16256282A JPS5951556A JP S5951556 A JPS5951556 A JP S5951556A JP 16256282 A JP16256282 A JP 16256282A JP 16256282 A JP16256282 A JP 16256282A JP S5951556 A JPS5951556 A JP S5951556A
- Authority
- JP
- Japan
- Prior art keywords
- thermocouple
- storage container
- temperature
- metal
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体収納容器に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor storage container.
従来例の構成とその問題点
半導体装置は近年、ますます高密度・窩集債化して来て
おり、その機能も複雑化している。Conventional configurations and their problems In recent years, semiconductor devices have become increasingly dense and complex, and their functions have also become more complex.
また、トランジスタ当りの消費電力は減少しているもの
の、葛密度化の進展が著るしく、ペレ・ソト当りでは逆
に増大の傾向にある。今後さらにその傾向は大きくなる
ものと思われ、熱管理が重要１課順となってくる。Furthermore, although the power consumption per transistor is decreasing, there is a remarkable progress in increasing the density of transistors, and on the contrary, the power consumption per transistor tends to increase. This trend is expected to grow even more in the future, with heat management becoming the most important subject.
以下に従来の収納容器についてセラミック・パッケージ
の例で説明する。第１図において１はセラミックパッケ
ージ本体、２は半導体素子、３は金属細線、４はリード
、６はキャンプ、６は」ｔ、１ＩＪ−桐である。このよ
うなセラミック・パッケージは例えば第１図中点線で示
した如く薄い＋ラミックシート上に所定の配線を印刷し
たのち重さね合わせて焼成し作られる。このようなパッ
ケージではチップ温度の上シ１．．パッケージ温度の上
？１が測定できない。さらに、プリント基板等に実装し
た場合は温度上昇が測定できない。A conventional storage container will be explained below using an example of a ceramic package. In FIG. 1, 1 is a ceramic package body, 2 is a semiconductor element, 3 is a thin metal wire, 4 is a lead, 6 is a camp, 6 is "t, 1IJ-paulownia." Such a ceramic package is produced, for example, by printing predetermined wiring on thin lamic sheets as shown by the dotted line in FIG. 1, and then stacking them together and firing them. In such a package, the temperature of the chip increases.1. ．． Above package temperature? 1 cannot be measured. Furthermore, when mounted on a printed circuit board or the like, temperature rise cannot be measured.
発明の「１的
本発明は上記従来例の問題点に鑑み、検査時又実装後の
収納容器の温度上昇を容易に測定しうる収納容器をυ１
１供することを目的とする○発明の構成
本発明は半導体素子載置部の略直下に熱−電気変換素子
を形成した構造を持つ収納容器により温度管理を容易な
らしめたものである。In view of the problems of the prior art described above, the present invention provides a storage container υ1 that can easily measure the temperature rise of the storage container during inspection or after mounting.
1. Structure of the Invention The present invention facilitates temperature control using a storage container having a structure in which a thermo-electrical conversion element is formed substantially directly below a semiconductor element mounting portion.
実施例の説明
第２図は本発明の一実施例としてセラミック・パッケー
ジに熱電灯を内蔵した構造を示し、従来例と共通の構成
安素の番号は第１図と同じにしである。４．４′はリー
ド、了は金属Ａ、８は金属Ｂで熱電対を形成し、ＡとＢ
なる異種金属の接触による電位差の温度変化を検出しよ
うとするものであり、金属７をリード４′に金属８をリ
ード４に接続しておけば外部からの測定を容易に行うこ
とができる。この場合、金属７，８は予かじめ、パッケ
ージ製造前に印刷形成しておけば良い。DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows a structure in which a thermoelectric lamp is built into a ceramic package as an embodiment of the present invention, and the numbers of constituent ammonium elements common to the conventional example are the same as in FIG. 1. 4. Form a thermocouple with 4' as lead, metal A as the end, and metal B as 8, and connect A and B.
The purpose is to detect the temperature change in potential difference due to contact between different metals, and by connecting the metal 7 to the lead 4' and the metal 8 to the lead 4, external measurement can be easily performed. In this case, the metals 7 and 8 may be printed in advance before manufacturing the package.
第２図は無電対の例で説明したが、熱電対のがわりに所
定の温度係数を有する抵抗体を印刷し、１１（抗性の温
度依存性を検出しても良い。また、セラミック・パッケ
ージではなく、厚嘆・薄膜混成集積回路基板でも同様の
構造とすることはできる。Although Fig. 2 has been explained using an example of a non-electrocouple, it is also possible to print a resistor having a predetermined temperature coefficient instead of a thermocouple and detect the temperature dependence of resistance. Instead, a similar structure can be achieved with a thick/thin film hybrid integrated circuit board.
発明の効果
本発明によれば、温度上昇測定用の無電対又は抵抗体が
収納容器と一体化されているため、検査時に容易に温度
測定ができ、熱管理ができるため今後の超ＬＳＩ用の収
納容器として回連のもので、ある。Effects of the Invention According to the present invention, since the electroless couple or resistor for measuring temperature rise is integrated with the storage container, temperature can be easily measured during inspection and heat management can be performed, which will be useful for future VLSIs. It is a reusable container used as a storage container.
第１図は従来のセラミックパッケージ概略断面図、第２
図は本発明の一実施例のセラミックパッケージの概１洛
１断面図である。
１ ・・・・パッケージ本体、４−・・・リード、５・
・・・・・キャップ、６・・・・・・封＋ｈ ’ｊＡ、
７・・・・・金属Ａ、ｓ・・・・・金属Ｂ。Figure 1 is a schematic cross-sectional view of a conventional ceramic package;
The figure is a roughly sectional view of a ceramic package according to an embodiment of the present invention. 1...Package body, 4-...Lead, 5-...
...Cap, 6...Seal+h'jA,
7...Metal A, s...Metal B.
Claims (4)
換素子を取付けたことを特徴とする半導体収納容器。(1) A semiconductor storage container characterized in that a thermo-electrical conversion element is attached substantially directly below an area in which a semiconductor element is placed.
とする特許請求の範囲第１項記載の半導体収納容器。(2) The semiconductor storage container according to claim 1, wherein the thermo-electric conversion element is a thermocouple.
気抵抗体であることを特徴とする特許請求の範囲第１項
記載の半導体収納容器。(3) The semiconductor storage container according to claim 1, wherein the thermo-electric conversion element is an electric resistor having a predetermined temperature coefficient.
素子を埋設したことを特徴とする特許請求の範囲第１項
記載の半導体収納容器。(4) The semiconductor storage container according to claim 1, characterized in that a thermo-electric conversion element is embedded in the intermediate layer of the multilayer ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16256282A JPS5951556A (en) | 1982-09-17 | 1982-09-17 | Encasing vessel for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16256282A JPS5951556A (en) | 1982-09-17 | 1982-09-17 | Encasing vessel for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5951556A true JPS5951556A (en) | 1984-03-26 |
Family
ID=15756943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16256282A Pending JPS5951556A (en) | 1982-09-17 | 1982-09-17 | Encasing vessel for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5951556A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2664745A1 (en) * | 1990-07-12 | 1992-01-17 | Landis & Gyr Betriebs Ag | Thermoelectric converter and method for manufacturing it |
| JP2014011385A (en) * | 2012-07-02 | 2014-01-20 | Nec Access Technica Ltd | Electronic device, electronic apparatus, and manufacturing method of electronic device |
-
1982
- 1982-09-17 JP JP16256282A patent/JPS5951556A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2664745A1 (en) * | 1990-07-12 | 1992-01-17 | Landis & Gyr Betriebs Ag | Thermoelectric converter and method for manufacturing it |
| JP2014011385A (en) * | 2012-07-02 | 2014-01-20 | Nec Access Technica Ltd | Electronic device, electronic apparatus, and manufacturing method of electronic device |
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