JPS5951540A - Voltage contrast image display apparatus - Google Patents

Voltage contrast image display apparatus

Info

Publication number
JPS5951540A
JPS5951540A JP58137534A JP13753483A JPS5951540A JP S5951540 A JPS5951540 A JP S5951540A JP 58137534 A JP58137534 A JP 58137534A JP 13753483 A JP13753483 A JP 13753483A JP S5951540 A JPS5951540 A JP S5951540A
Authority
JP
Japan
Prior art keywords
signal
sample
voltage
wiring
selection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58137534A
Other languages
Japanese (ja)
Inventor
Satoru Fukuhara
戸所秀男
Hideo Todokoro
福原悟
Yoshio Hokotani
鉾谷義雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58137534A priority Critical patent/JPS5951540A/en
Publication of JPS5951540A publication Critical patent/JPS5951540A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To obtain an apparatus for displaying a voltage contrast image under the condition that a protection film is covered through the use of a low speed energy as the primary beam by respectively providing specific deflection oscillator, a circuit for applying voltage to sample and a signal selection circuit. CONSTITUTION:A voltage is applied to the specified Al wiring of semiconductor of a sample 8. When the sample is irradiated with slowly accelerated primary beams 1, the secondary electrons are generated from the surface of sample 8. The secondary electron signal generated also includes an general SEM data and a voltage contrast data applied to the Al wiring. This signal is detected by a detector 5 and amplified and is then inputted to a signal selection circuit 6. When a rectangular wave is applied to the Al wiring, a signal having equal positive and negative values is generated as an output. The signal selection circuit 6 selects either one signal and performs switching by the synchronous signal of X-scanning sent from the deflection oscillator 4. An output is inputted as an intensity modulated signal of CRT 9 and is displayed on the CRT screen as an SEM image.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、電圧コントラストの像表示装置の改良に関す
る。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improvements in voltage contrast image display devices.

〔発明の背景〕[Background of the invention]

LSI等の半導体素子の非破壊検査装置として、SEM
の利用は最近増々多くなってきた。そして低加速(〜2
kV)の1次電子ビームを利用すると、絶縁膜で被われ
たLSI表面を前処理なしで、チャージアップ現象が生
じない像として観察できる。この1[はLSIに保護膜
を塗布した最終段階での形状の検葭が可能であることを
示している。。
SEM is used as a non-destructive testing device for semiconductor devices such as LSI.
The use of has been increasing recently. and low acceleration (~2
By using a primary electron beam (kV), it is possible to observe an LSI surface covered with an insulating film as an image without a charge-up phenomenon without any pretreatment. This 1 indicates that it is possible to inspect the shape of the LSI at the final stage after applying the protective film. .

また、更にSEMでは、外部からLSIに電圧を印加し
、LSI内部における電圧の情報をSEM像として表示
する電圧コントラスト像が可能である。例えば、ストロ
ボSEMの開発や、エネルギーアナライザーを用いたS
EMの開発により、電圧コントラストの情報を得て、L
SI内部のパルス的な解析や、AI!配線の断線個所の
観察等により、動的検査が可能となりつつある。しかし
ながら、一般的に行なわれているこれらの開発は、1次
ビームのエネルギーが数10 KeVと高いものや、L
SI上に保護膜が被われていない状態での開発が大部分
をしめている。
Further, in the SEM, a voltage contrast image is possible in which a voltage is applied to the LSI from the outside and information on the voltage inside the LSI is displayed as a SEM image. For example, the development of strobe SEM and S
With the development of EM, information on voltage contrast has been obtained, and L
Pulse analysis inside SI and AI! Dynamic inspection is becoming possible by observing broken wires. However, these developments that are generally carried out are based on primary beams with a high energy of several tens of KeV or L
Most of the development is done without a protective film covering the SI.

〔発明の目的〕[Purpose of the invention]

本発明は、かかる点に着目してなされたものであり、1
次ビームとして低速(〜2kV)のエネルギーを用い、
保護膜が被われた状態での電圧コントラストの像を表示
する電圧コントラストの像表示装置を提供することを目
的とするものである。
The present invention has been made focusing on these points, and has the following features:
Using low-velocity (~2kV) energy as the secondary beam,
It is an object of the present invention to provide a voltage contrast image display device that displays a voltage contrast image covered with a protective film.

〔発明の概要〕[Summary of the invention]

保護膜下にある物質、例えばAJ配線上の電圧の情報は
保護膜を通す事により、どの様になるか非常に重要な問
題であり、その解明のために行った我々の実験結果の1
つを模式的に第1図(a) 、 (b)に示す。図の(
a)に示す様に、保砕膜で被われたAj5配線上の一点
に1次ビーム■ を停止して照射し、AI!配線に印加
する電圧v、ヲ矩形波で変化させる。そして、保護膜か
ら発生した2次電子I3をつかまえてホトマル(P、M
)で増幅し出力電圧vo とする。この時のvdとV。
It is a very important question how the voltage information on substances under the protective film, such as AJ wiring, changes when the protective film passes through it.
One is schematically shown in FIGS. 1(a) and (b). (
As shown in a), the primary beam ■ is stopped and irradiated to one point on the Aj5 wiring covered with the crushing film, and the AI! The voltage v applied to the wiring is changed using a rectangular wave. Then, the secondary electrons I3 generated from the protective film are captured and photomuled (P, M
) to obtain the output voltage vo. Vd and V at this time.

の関係を実験結果より図示すると図の(b)の様になる
。これらの実験から、AI!配線に印加した?1.を圧
は保護膜を通すことにより微分されて出力されることが
わかった。
The relationship is shown in figure (b) based on the experimental results. From these experiments, AI! Did you apply it to the wiring? 1. It was found that the pressure is differentiated and output by passing through the protective membrane.

つまり保護膜は一種のコンデンサーの働きをしているこ
とになる。この事は保護膜下にあるAJ配線に直流的な
電圧を印加しても保護膜を通しては検出することができ
ず、交流的な電圧を印加する必要性があることを示して
いる。
In other words, the protective film acts as a kind of capacitor. This shows that even if a DC voltage is applied to the AJ wiring under the protective film, it cannot be detected through the protective film, and that it is necessary to apply an AC voltage.

〔発明の実施例〕[Embodiments of the invention]

以上の実験結果にかんがみ、保護膜下における電圧コン
トラストの情報を常時、安定に表示する本発明の方式を
以下の実施例を参照して詳細に説明する。
In view of the above experimental results, the method of the present invention for constantly and stably displaying voltage contrast information under a protective film will be described in detail with reference to the following examples.

第2図には本装置のブロックダイヤグラムを示す。偏向
発振器4からの信号はCRT9と偵向器3を同期してX
−Yに走査する。また、偏向発振器4から、X−走査の
同期信号だけを取りだして試料印加電圧回路7に入力、
する。試料印加電圧回路7はX−走査と同期した所定の
矩形波電圧を発生し、試料8の半導体の所定のAJ配線
にその電圧を印加する。その試料上を低加41次ビーム
(〜2KeV)lで照射すると、試料8面一ヒから2次
電子2が発生する。発生した2次電子信号は一般的なS
EMの情報とAI!配線に印加した電圧コントラストの
情報をも含んでいる。この二つの情報を含んだ2次電子
信号は検出器5で検出され増幅を受け、信号選択回路6
に入力される。電圧コントラストの情報は前に記述した
ように、保護膜の働きで、保護膜下にあるAI!配線の
印加電圧が微分されて出力されることがわかっている。
FIG. 2 shows a block diagram of this device. The signal from the deflection oscillator 4 synchronizes the CRT 9 and the reconnaissance device 3
- Scan to Y. Further, only the X-scan synchronization signal is taken out from the deflection oscillator 4 and inputted to the sample application voltage circuit 7.
do. The sample application voltage circuit 7 generates a predetermined rectangular wave voltage in synchronization with the X-scan, and applies the voltage to a predetermined AJ wiring of the semiconductor of the sample 8. When the sample is irradiated with a low-power 41st-order beam (~2 KeV), secondary electrons 2 are generated from all 8 surfaces of the sample. The generated secondary electron signal is a general S
EM information and AI! It also includes information on the voltage contrast applied to the wiring. The secondary electronic signal containing these two pieces of information is detected by the detector 5 and amplified, and then the signal selection circuit 6
is input. As described above, the voltage contrast information is due to the function of the protective film, and the AI! It is known that the voltage applied to the wiring is differentiated and output.

したがって、AJ配線に矩形波を印加すると、出力とし
て、正と負の等しい値をもつ信号が発生する。
Therefore, when a rectangular wave is applied to the AJ wiring, a signal having equal positive and negative values is generated as an output.

故にどちらか一方の信号を輝度変調信号として用いる必
要が生じる。信号選択回路6はこの正と負のどちらか一
方の信号を選択する回路で、偏向発振器4からのX−走
査の同期信号によってスイッチングを行なっている。し
たがって、信号選択回路6はX−偏向の奇数番目、ある
いは偶数番目のどちらかの時だけ信号を出力し、逆の揚
台は強制的にO電位にする回路である。信号選択回路6
からの出力はCRT9の輝度変調信号として入力し、C
RT面上にはSEM像として表示される。
Therefore, it becomes necessary to use one of the signals as the brightness modulation signal. The signal selection circuit 6 is a circuit that selects either the positive or negative signal, and performs switching based on the X-scan synchronization signal from the deflection oscillator 4. Therefore, the signal selection circuit 6 is a circuit that outputs a signal only when the X-deflection is odd-numbered or even-numbered, and the opposite platform is forcibly set to O potential. Signal selection circuit 6
The output from CRT9 is input as a brightness modulation signal, and
It is displayed as a SEM image on the RT plane.

第3図に各部の波形例を示す。AはX偏向の鋸歯状波を
示し、Bはそれと同期した試料に印加される矩形波を示
す。Cは発生した2次電子信号を示すものである。電圧
を印加したAI!配線の部分だけに電圧コントラスト成
分が重畳されて表示される。DはCRTの輝度変調信号
で、信号選択回路6により偶数番目のX偏向時は信号が
0になっている。
FIG. 3 shows examples of waveforms at each part. A shows the sawtooth wave of the X deflection, and B shows the square wave applied to the sample synchronized therewith. C indicates the generated secondary electron signal. AI with applied voltage! The voltage contrast component is displayed superimposed only on the wiring portion. D is a brightness modulation signal of the CRT, and the signal is set to 0 by the signal selection circuit 6 during even-numbered X deflection.

以上説明【7たように、上記実施例による本方式を用い
れば保護膜下の電圧コントラストの情報tSEM像どし
°C衣示することが可能となる。
As explained above, by using this method according to the above embodiment, it is possible to display information on the voltage contrast under the protective film in tSEM images.

次に、第4図に本発明の他の実施例のブロックダイヤグ
ラムを示す。1次電子の乍向方式及び、2次電子の検出
方式は先に述べた方法と同じである。特に試料の電圧印
加方式を中心に記述する。
Next, FIG. 4 shows a block diagram of another embodiment of the present invention. The direction method for primary electrons and the method for detecting secondary electrons are the same as those described above. In particular, we will focus on the method of applying voltage to the sample.

ロックインアンプ11を設けて、そのリファレンス(R
eference )  信号を試料印加電圧変調回路
12に入力する。試料印加電圧変調回路12の出力は、
ロックインアンプ11のリファレンス(Re−fere
nce )周波数(例えば30KI4z)で変調を受け
た所定の電圧を発生し、試料8士のA/配線に供給する
。AI!配線上の保護膜を通して照射された1次ビーム
により発生した2次電子信号は一般的なSEMの信号の
他に、AJ配線に印加した電圧コントラスト成分(Re
ference 周波数で変調を受けた成分)も含まれ
ることになる。これは保護膜がコンデンサーの働きをし
ていることで、変調周波数(Reference 周波
数30kHz)が高いために保護膜上に電圧コントラス
トの情報がそのまま伝わるからである。
A lock-in amplifier 11 is provided, and its reference (R
ference) signal is input to the sample applied voltage modulation circuit 12. The output of the sample applied voltage modulation circuit 12 is
Lock-in amplifier 11 reference (Re-fere)
A predetermined voltage modulated at a frequency (for example, 30KI4z) is generated and supplied to the A/wirings of the eight samples. AI! The secondary electron signal generated by the primary beam irradiated through the protective film on the wiring is not only a general SEM signal but also a voltage contrast component (Re
(components modulated at the reference frequency) are also included. This is because the protective film acts as a capacitor, and since the modulation frequency (reference frequency: 30 kHz) is high, voltage contrast information is transmitted directly onto the protective film.

これら二つの情報を含んだ信号は検出器5を通してロッ
クインアンプ11に入力される。ロックインアンプ11
は変調周波数(Reference 周波数)で検波を
行ない積分する。すると、その周波数成分だけの信号が
ロックインアンプ11の出力信号となりCBr4の輝度
信号となる。すなわち、ロックインアンプ11からの出
力信号には一般のSEMの信号は含まれず、A/’配線
に印加された電圧コントラストだけの情報がCRT面−
Fにおいて像仁なる。
A signal containing these two pieces of information is input to the lock-in amplifier 11 through the detector 5. lock-in amplifier 11
performs detection and integration at the modulation frequency (Reference frequency). Then, a signal containing only that frequency component becomes an output signal of the lock-in amplifier 11 and becomes a luminance signal of CBr4. That is, the output signal from the lock-in amplifier 11 does not include a general SEM signal, and only information about the voltage contrast applied to the A/' wiring is transmitted to the CRT screen.
In F, there is a statue.

このように上記方式を用いると、AI!配線等の電圧印
加した部分だけが像となるので断線個所の部分が簡単に
検査し易く便利であるが、凹凸の形状を観察できない欠
点がある。そこで、この方式の欠点を改良した例を以下
に示す。第5図にそのブロックダイヤグラムを示す。こ
の方式は第2図及び第4図の方式を組み合わせたもので
ある。試料印加電圧変調回路12はロックインアンプ1
1からの高いReference周波数で変調を受ける
When the above method is used in this way, AI! Since only the portion of the wiring or the like to which a voltage is applied becomes an image, it is convenient because it is easy to inspect the portion where the wire is broken, but it has the disadvantage that the shape of the unevenness cannot be observed. Therefore, an example in which the drawbacks of this method are improved is shown below. FIG. 5 shows its block diagram. This method is a combination of the methods shown in FIGS. 2 and 4. The sample applied voltage modulation circuit 12 is a lock-in amplifier 1
It is modulated at a high reference frequency from 1.

そしてその出力はスイッチング回路13に入力される、
そのスイッチング回路13は、偏向発振器4からのX走
査同期信号をも行って、低い周波数例えば50kHzで
同期してスイッチングをおこなう。したがって、例えば
、X偏向の奇数番目はスイッチがON状態でしかもその
出力電圧は30kHz  で変調された所定の電圧が出
力され、逆にX走査の偶数番目はスイッチがOFF状態
になり出力はOとなる。以上の出力電圧を試料8のAI
!配線に印加すると、1次ビームによって試料から発生
する二次電子信号はX偏向の奇数番目は主に電圧コント
ラストの情報、偶数番目は一般のSEMの情報と2つの
信号に分かれる。従って、検出器5からの信号を信号選
択回路6に入力し、X−走査と同期して選択し、奇数番
目は入力信号をロックインアンプ11に入力し積分しC
RTloの輝度変調信号として用いる。また、偶数番目
は入力信号をCBr4の輝度変調信号として用いる。以
上のことから、CBr4は一般的なSEM(I、CRT
IOは電圧コントラストの像を交互に表示することがで
きる。もちろん一つのCRT上に重ねて表示することも
容易に類推できる。
The output is then input to the switching circuit 13.
The switching circuit 13 also receives an X-scan synchronization signal from the deflection oscillator 4 to perform switching in synchronization at a low frequency, for example, 50 kHz. Therefore, for example, at the odd numbered X deflection, the switch is ON and a predetermined voltage modulated at 30kHz is output, and conversely, at the even numbered X scanning, the switch is OFF and the output is O. Become. The output voltage of sample 8 is
! When applied to the wiring, the secondary electron signal generated from the sample by the primary beam is divided into two signals: odd-numbered X deflection signals are mainly voltage contrast information, and even-numbered signals are general SEM information. Therefore, the signal from the detector 5 is input to the signal selection circuit 6 and selected in synchronization with the X-scan, and the odd-numbered input signal is input to the lock-in amplifier 11 and integrated.
Used as a luminance modulation signal for RTlo. Furthermore, the even-numbered input signal is used as a CBr4 brightness modulation signal. From the above, CBr4 is a general SEM (I, CRT
The IO can display alternating voltage contrast images. Of course, it can be easily assumed that the images can be displayed overlappingly on one CRT.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明による方式を用いることに
より、LSI等の半導体を保護膜が被われた最終段階で
、凹凸の形状観察と同時に電圧コントラスト−を表示す
ることが可能となった。
As explained above, by using the method according to the present invention, it has become possible to simultaneously observe the shape of unevenness and display the voltage contrast at the final stage when a semiconductor such as an LSI is covered with a protective film.

【図面の簡単な説明】[Brief explanation of drawings]

第11u(a)、 (b)は、本発明の基本的原理を説
明する図、第2図は、本発明の一実施例を示すブロック
線図、第3図は、上記ブロックダイヤグラムの各部の波
形図、第4図および第5図は、それぞれ本発明の他の実
施例を示すブロック線図である。 図において、1 ・・・電子ビーム、2 ・・・ 2次
電子、3 ・・・偏向器、4・・・ 偏向発振器、5 
・・・検出器、6 ・・・信号選択回路、7 ・・・試
料印加電圧回路、8・・・試料、9.、、CRT0矛2
図 +3図 Δtry押。寿介 +4問
11u(a) and (b) are diagrams explaining the basic principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing each part of the above block diagram. The waveform diagram, FIG. 4, and FIG. 5 are block diagrams showing other embodiments of the present invention, respectively. In the figure, 1... electron beam, 2... secondary electron, 3... deflector, 4... deflection oscillator, 5
. . . Detector, 6 . . Signal selection circuit, 7 . . . Sample application voltage circuit, 8 . . . Sample, 9. ,,CRT0 spear 2
Press figure + 3 figure Δtry. Jusuke + 4 questions

Claims (1)

【特許請求の範囲】[Claims] 1、低加速1次電子ビームを試料上に走査して発生する
2次電子信号を検出する検出手段と、−上記電子ビーム
を上記試料−FのX方向及びY方向に走査せしめる信号
を発生する偏向光゛振器と、上記試料に上記偏向発振器
によるX方向走査と同期した所定の矩形波電圧を印加す
る試料印加電圧回路と、上記X方向走査と同期して上記
検出器の出力信号を上記X方向走査の偶数番目あるいは
奇数番目のどちらだけ通過せしめる信号選択回路と、上
記X方向走査と同期して−り記信号選択回路の出力信号
を輝度変調信号に用いて像表示せしめる像表示手段を具
備してなることを特徴とする電圧コントラストの像表示
装置。
1. A detection means for detecting a secondary electron signal generated by scanning a low-acceleration primary electron beam on a sample; - generating a signal for causing the electron beam to scan in the X direction and the Y direction of the sample -F; a deflection optical oscillator; a sample application voltage circuit for applying a predetermined rectangular wave voltage to the sample in synchronization with the X-direction scanning by the deflection oscillator; A signal selection circuit that allows even or odd numbered signals to pass through in the X direction scan, and image display means that displays an image by using the output signal of the signal selection circuit as a brightness modulation signal in synchronization with the X direction scan. A voltage contrast image display device comprising:
JP58137534A 1983-07-29 1983-07-29 Voltage contrast image display apparatus Pending JPS5951540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58137534A JPS5951540A (en) 1983-07-29 1983-07-29 Voltage contrast image display apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58137534A JPS5951540A (en) 1983-07-29 1983-07-29 Voltage contrast image display apparatus

Publications (1)

Publication Number Publication Date
JPS5951540A true JPS5951540A (en) 1984-03-26

Family

ID=15200927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58137534A Pending JPS5951540A (en) 1983-07-29 1983-07-29 Voltage contrast image display apparatus

Country Status (1)

Country Link
JP (1) JPS5951540A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59210480A (en) * 1983-05-14 1984-11-29 東芝ライテック株式会社 Large color display unit
EP0495262A2 (en) * 1991-01-14 1992-07-22 Schlumberger Technologies, Inc. Integrated circuits modification with focused ion beam system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120256A (en) * 1974-08-13 1976-02-18 Yotsukaichi Gosei Kk HORIECHIRENOKISAIDOJUSHI SOSEIBUTSU

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120256A (en) * 1974-08-13 1976-02-18 Yotsukaichi Gosei Kk HORIECHIRENOKISAIDOJUSHI SOSEIBUTSU

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59210480A (en) * 1983-05-14 1984-11-29 東芝ライテック株式会社 Large color display unit
EP0495262A2 (en) * 1991-01-14 1992-07-22 Schlumberger Technologies, Inc. Integrated circuits modification with focused ion beam system

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