JPS5950669A - Horizontal synchronizing device - Google Patents

Abstract

PURPOSE:To attain high integration and stable operation, by using an A/D converter, a synchronizing separating circuit, a comparison signal generating circuit, a loop filter and a delay time control circuit or the like in a TV receiver so as to perform the digital horizontal synchronizing processing. CONSTITUTION:A composite video signal is A/D-converted 8, separated 9 synchronizingly and transmitted to a phase detecting circuit 10. An output signal V of the circuit 10 is averaged via the loop filter 11 and given to an oscillator 12. Then, the output frequency and phase of the oscillator 12 are synchronized with an input horizontal synchronizing signal. The phase of output is adjusted minutely at a delay time control circuit 13 and a horizontal deflection output signal E is obtained at a horizontal drive circuit 14 and a horizontal output circuit 15. This signal E is given to a comparison signal generating circuit 16 and a comparison signal U being zeroed at the center of output pulse is fed back to the circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital horizontal synchronizer that can be used in television receivers.

Conventional Structure and Problems Conventionally, the horizontal synchronization circuit used in a television receiver is an analog circuit, and is generally structured as shown in FIG. First, the conventional example shown in FIG. 1 will be explained.

3·°−1゛2 In this figure, the input signal is a composite video signal. 1 is a sync separation circuit for obtaining a sync signal containing horizontal pulses, vertical pulses and equivalent pulses from an input composite video signal (analog signal); 2 is a phase detection circuit; 3 is a loop filter;
4 is a voltage controlled oscillation circuit (VCO), 5 is a horizontal drive circuit, 6 is a horizontal output circuit, and 7 is a comparison signal generation circuit.

To briefly explain the operation of Fig. 1, first, the synchronization signal output from the synchronization separation circuit 1 and the output pulse E (for example, a horizontal flyback pulse) from the horizontal output circuit 6 are connected to a circuit composed of a resistor and a capacitor. Generally, a sawtooth waveform FC circuit, a large pulse width FC circuit, etc. is used to generate a comparison signal B with a sawtooth waveform in addition to the comparison signal generation circuit 7 which performs integration using a low-pass filter. In addition to the detection circuit 2, a phase error signal C corresponding to the phase difference between the synchronization signal and the comparison signal B is obtained as an output of the phase detection circuit 2. This phase error signal C is averaged by adding it to a loop filter 3 composed of a resistor and a capacitor or using a drag filter, and converts the phase error signal C into a substantially direct current control signal. This control signal is applied to a voltage sterilization oscillation circuit (VCO) 4, and controlled so that its oscillation frequency and phase match the input horizontal synchronizing signal. As a result of this control, the control signal approaches zero. The output of the VCO 4 is applied to the horizontal output circuit 6 via the horizontal drive circuit 6, and a horizontal deflection output signal (including a flyback pulse) is obtained as its output.

The control loop as described above automatically controls the horizontal oscillation frequency and phase to synchronize the horizontal deflection output signal with the input synchronizing signal and maintain that state.

However, since these conventional devices operate using analog signal processing, they contain many capacitors, etc., making it difficult to incorporate into semiconductor integrated circuit elements, and they are also large, which slows down production. In addition to being unable to achieve rationalization, there is a problem in that the operation of the circuit is not constant or unstable due to variations in circuit components.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an apparatus capable of overcoming such conventional drawbacks and achieving horizontal synchronization of a television receiver by digital 6-vertical signal processing.

Structure of the Invention In the present invention, first, a composite video signal is converted into a digital signal quantized into binary values, and then A/D conversion is performed to convert the digital signal into a horizontal pulse.

Obtain a synchronization signal containing a vertical pulse and an equivalent pulse.

On the other hand, a comparison signal generation circuit configured using an adder 1 multiplier and a unit delay circuit integrates the output pulse of the horizontal output circuit to generate a comparison signal, and the sync signal from the sync separation circuit and this comparison signal generation circuit A phase detection circuit configured using a multiplier, an adder, and a unit delay circuit performs a phase comparison. The phase detection output of the phase detection circuit is configured using an adder 1 multiplier and a unit delay circuit, and its transfer function is defined as (where α1, α2, and σ3 are the multiplication coefficients of the multipliers.

6 Page zl represents a unit delay) is averaged by a loop filter. The output of this loop filter is used as a control signal to control an oscillation circuit configured using a counter, thereby controlling the frequency and phase of the output pulse of the horizontal output circuit to be synchronized with the horizontal synchronizing signal. Furthermore, the phase of the oscillation output of this oscillation circuit is finely adjusted using a part of the control signal output from the loop filter. The output horizontal drive circuit and horizontal output circuit of the delay time control circuit thus obtained are driven.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

Figure 2 shows the schematic configuration. In the figure, 8 is a digital converter that converts the input composite video signal into a digital signal quantized into binary values, and 9 is a synchronizer that obtains a synchronization signal including horizontal pulses, vertical pulses, and equivalent pulses from the digital signal. It is a separate circuit.

1o is a phase detection circuit, 11 is a loop filter, and 12 is a horizontal oscillation circuit, each of which is constituted by a digital 7 beta circuit. Furthermore, 13 is a delay time control circuit for digital power reduction, 14 is a horizontal drive circuit,
15 is a horizontal output circuit, and 16 is a circuit for creating a digital signal comparison signal.

Next, the operation and details of each part will be explained. A-
The digital signal S, which is the output of the D converter 8 and which is the quantized composite video signal into binary values, generally requires 7 to 8 bits including the video signal and 9 color signals, and among them, horizontal and vertical synchronization The signal only needs to be 6 to 6 bits. Therefore, the synchronization separation circuit 9 uses the 5th to 6th bits from the 1st bit to - of the signal S (7th to 8th bits) as a synchronizing signal. The output T of the synchronization separation circuit 9 is a 5- to 6-pit digital signal (
However, these 5 to 6 bits may be handled as a 1-bit signal via a gate.

This synchronization signal T is applied as a first input to the phase detection circuit 1o. On the other hand, the output pulse E (for example, a flybank pulse) of the horizontal output circuit 15 is applied to the comparison signal generation circuit 16 to obtain a digital comparison signal U that becomes zero at the center of the output pulse E. Add as input of 2.

Here, as shown in FIG. 3, the comparison signal generation circuit 6 basically includes a multiplier 17 with a coefficient of -7-, a multiplier 1B with a coefficient aO, adders 19 and 20, and The delay circuit 21 has a delay of 2-+, and its transfer function is expressed by the following equation 1.

Here, the sampling frequency is 4fsc (fsc is the color subcarrier frequency: 14.31818MH in the NTSC system)
z) and the cutoff frequency is 3.2 KHz, α0−○, 9986, =O,0O0
It becomes 7.

Further, the comparison signal generating circuit 16 can also be constructed as shown in FIG.

In FIG. 4, reference numerals 22 and 23 are tri-state switches, and their control terminals are connected to the output pulse E of the horizontal output circuit 16 through an inverter 24. Therefore, the eighth
High level period of output pulse such as Na (retrace period)
tr] - The tri-state switch 22 is turned on and the constant 01 is added to the adder 25, and during the scanning period ts, the tri-state switch 23 is turned on and the constant 02 is added to the adder 25.
(negative number) is added to adder 25. The output signal Y of the adder 26 is fed back through the unit delay circuit 26, and the adder 27 receives the signal Y and the maximum value Yma of the signal Y.
A signal of 1/2 x is added via a multiplier 28 with a coefficient of 1/2, and a comparison signal U is obtained as output Z.

FIG. 6 shows operating signals of each part of the circuit of FIG. a is a horizontal flybank pulse, b is an output signal Y of the adder 25 (this temporarily represents an actual binary digital signal as an analog quantity), and C is a signal that is 1/2 of the maximum value of the output signal Y. 1/2Ymax,d is the output comparison signal U (same as above).

Next, the phase detection circuit 10 multiplies the horizontal synchronization signal and the comparison signal U by sampling synchronization, integrates the multiplication result]~, divides the result by the number of integrations, and averages the result by -S. By doing so, it operates to obtain a phase detection output V of one horizontal period. FIG. 6 shows an example of its configuration. In FIG. 6, 29 is a multiplier, 30 is an adder, 31 is a delay circuit for one sampling period, and 32 is a multiplier with a coefficient of 17H. Here, N is the number of times of addition by the adder 30, and is obtained by counting the time interval of the horizontal synchronizing signal in Zanoprinder cycles.

Further, the phase detection circuit 10 can also be configured as shown in FIG.

In FIG. 7, 33 is a detection circuit for the rising and falling edges of the horizontal synchronizing signal T. This edge detection circuit 33
The rising edge detection output which is the output of is input to the multiplier 34, and the multiplication result x1 with the comparison signal U which is the other input is obtained. On the other hand, the falling edge detection output is input to the multiplier 35, and similarly multiplication result x2 with comparison signal U is obtained.

X+ and X2 are added in an adder 36, and then added to
/2, and the phase detection output V is obtained as its output.

11 Gate゛ FIG. 8 shows operating signals of each part of the circuit of FIG. 7.

Here, d is the same comparison signal u as d in FIG. 6, 6 is the horizontal synchronizing signal T, f is the multiplication output x1 (negative value in this example),
g is the multiplication output x2, and h is the phase detection output V.

The output V of this phase detection circuit 10 is added to the loop filter 11 and averaged, and the control signal W is converted into a DC signal.
get.

The loop filter 11 basically includes multipliers 38, 39, 40, 41, 42 and an adder 43, as shown in FIG.
．． 44.45.46 and one horizontal period delay Z-1 circuit 4
7.48, and its transfer function is expressed by the following equation 2.

In the NTSC system, the frequency fH of the horizontal synchronizing signal is 15.
734KH2, 38, 39, 43.

The cutoff frequency of the low-pass filter composed of 44.47 is 1° es KHz, and
, 46, 46.48, the cutoff frequency of the phase ladder filter is 5. In the case of ○Hz, the coefficients of each multiplier have the following values.

α2=0.99805. α3−0°98438 is the output of such a loop filter 11.

A control signal W is applied to an oscillation circuit 12 composed of a counter, and the frequency and phase of the output of the oscillation circuit 12 are controlled to be synchronized with the input horizontal periodic signal T.

As a result, the control signal W approaches zero and synchronization is maintained.

The output of the oscillation circuit 12 is added to the delay time control circuit 13, and a part of the output W of the loop filter 11 (for example, the lower two bits α and β) is used to finely adjust the phase.

An example of the configuration of this delay time control circuit 13 is shown in FIG.

In FIG. 10, a part of the output W of the loop filter 11 (lower 13 page 2 bits α, β) obtained by averaging the phase detection output is applied to inverters 49 and 50 and buffer amplifiers 51 and 52, respectively, and their respective outputs are AND gates 53 , 54 , 56 .

66 plus the combination (o, o) of (α, β).

Decode (o, 1), (1, o), (1, 1).

Its output is a tri-state switch 67°68.59.
60 respectively. 61, 62, 63 are tri-state switches 57, 58, 59.

6Q is a delay gate having a constant delay time t.

With this configuration, the following delay time control can be performed between input and output. However, t is the sampling frequency', 4
This value is smaller than 174, which is one sampling time for fsc.

When (α, β) - (0, 0), the delay time between input and output is t
(α, β) = (0, 1) I //
is 2t (α, β) = (1, o) tt
〃 is 3t(α,β)=(1,1)/
/ // is 4. Then, the output of the delay time control circuit 13 is applied to the horizontal output circuit 16 via the horizontal drive circuit 14, and a horizontal deflection output signal is obtained as its output.

The horizontal oscillation frequency and phase can be controlled by a control loop using digital signal processing as described above, and the horizontal deflection output signal can be kept in synchronization with the input synchronization signal.

Effects of the Invention As described above, according to the present invention, since the horizontal synchronization device in a television receiver is constructed from a digital circuit, most of the components such as resistors and capacitors that are required in conventional analog devices are not required. Therefore, it can be constructed using semiconductor integrated circuits and can be highly integrated, making it possible to greatly rationalize circuit components and production processes.

Furthermore, the digital signal processing method has almost no circuit instability caused by variations in circuit components in the analog method, and therefore can provide extremely stable operation.

Figure 2 shows 15 of the horizontal synchronization device in one embodiment of the present invention.
The basic diagram, Figures 3 and 4 are circuit diagrams of the comparison signal generation circuit used in the same device, Figure 5 is a waveform diagram of each part, and Figures 6 and 7 are the circuit diagrams of the comparison signal generation circuit used in the same device. A circuit diagram of the phase detection circuit used, Fig. 8 is a waveform diagram of each part thereof, Fig. 9 is a circuit diagram of a loop filter used in the same device, and Fig. 10 is a circuit diagram of a delay time control circuit used in the same device. It is.

8...A-D converter, 9...Synchronization separation circuit, 1o...Phase detection circuit, 11...
・Loop filter, 12...Oscillation circuit, 13.
...Delay time control circuit, 14...Horizontal drive circuit, 15...Horizontal output circuit, 16...
...Comparison signal generation circuit.

Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 2 Figure 3 Figure 8 (Figure 9)

Claims (1)

[Claims] An A-D converter that converts a composite video signal into a digital signal quantized into binary values, and a synchronization signal containing horizontal pulses, vertical pulses, and equivalent pulses from the A-D converted digital signal. , a comparison signal generation circuit configured using an adder 2 multiplier and a unit delay circuit to generate a comparison signal by integrating output pulses of the horizontal output circuit; A phase detection circuit configured using a multiplier, an adder, and a unit delay circuit so as to add and compare the phases of a synchronization signal and a comparison signal from the comparison signal generation circuit, and averaging the phase detection output of the phase detection circuit. It is configured using an adder, 9 multipliers, and a unit delay circuit so that A loop filter is provided as shown in FIG. the configured oscillation circuit, a delay time control circuit that finely adjusts the phase of the oscillation output of the oscillation circuit using a part of the control signal output from the loop filter, and a horizontal control circuit driven by the output of the delay time control circuit. A horizontal synchronizing device comprising a drive circuit and a horizontal output circuit.