JPS5950158B2 - Signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing method that ignores signal changes due to noise and the like and detects only cases where the signal continues for a predetermined length (P bits) after the signal changes.

It is something that For example, in the input signal processing of a telephone exchange, subscriber line scanning and incoming line (incoming trunk) scanning are performed, and subscriber line call origination and incoming trunk call origination detection are performed at predetermined scanning intervals. .

In this case, a 1-bit supervisory signal is used, and processing is performed on the assumption that, for example, a supervisory signal of "O" means a call is in progress, and a supervisory signal of "1" means an idle state.

In other words, the scan result read in the previous cycle is "O" or "
1'' is stored in the memory, and in the next cycle, the current scan result is compared with the previous scan result in the memory, and if there is a discrepancy, it is determined that there has been a change in state. The scanning device takes input signals from electronic contacts such as relay contacts of subscriber line circuits, relay contacts of trunk circuits or multifrequency receivers, pushbutton receivers, etc., for example in the form of a matrix of resistors, diodes, etc.

For example, in a subscriber on-hook condition, the relay is inactive and the drive pulse applied to the matrix is read through a resistor, diode, and converted to a digital signal "1" output. Also, when a subscriber goes off hook,
Since the relay operates and the scanning contact operates, the drive pulse applied to the matrix flows from the scanning contact to the Jizo through the resistor, so there is no read input, and it is converted into a digital signal "O" output. In this way, the monitoring signal is generated by analog-to-digital conversion processing, but if it is subject to chattering during the conversion processing or if external noise is mixed in during propagation of the transmission line, the signal "1" is often
may change to "O" or "O" may change to "1".

In this case, the monitoring signal is a serial input signal, and when it is normal, it continues for a certain predetermined length after the signal changes, but when the signal changes due to noise etc., it continues for only one bit. It is a short signal that continues only for a predetermined length or less.

Therefore, in order to prevent switching equipment from malfunctioning due to noise, etc., it is necessary to ignore temporary signal changes in the serial input signal, and processing to remove temporary signal changes is required. becomes.

Conventionally, as one of such processes, an error protection method using majority logic has been used.

FIG. 1 is an explanatory diagram of a conventional signal processing method using majority logic. In FIG. 1a, the signal error protection circuit 3
The circuit is composed of a plurality of bits of memory, registers, logical arithmetic units, etc., and performs majority logic on successive predetermined bits of the serial input signal.

To this signal error protection circuit 3, a serial input signal arrives from a signal line 1, and at the same time a clock signal is input from a clock line 2. For example, when taking majority rule for 5 consecutive bits, if 3 or more of the 5 bits are ``1'', ``1'' is output to output line 4, and if 2 or less of the 5 bits are ``1'', then ``1'' is output. In this case, "0" is output to the output line 4. Now, in synchronization with the clock signal CLK on the clock line 2, a serial input signal 1NPSG as shown in FIG.
In the event of an error, the signal error protection circuit 3 performs a 5-bit majority rule, and as a result, outputs serial output signals 0UT and SG as shown on the output line 4.

For example, the output signal 0UTSG at time (5) is the majority logic of the input signal 1NPSG (1, 1, 0, 1, 1) at times (1), (2), (3), (4), (5). is taken and becomes "1", and the output signal 0UTSG at time (6) is , time (2), (3), (4)
, (5), (6) input signal 1NPSG(1,0,
The majority logic of 1, 1, 1) is taken and the result is "1". In this way, all temporary signal changes, such as the input signal "O" at time (3), are removed, and all "1"s are obtained from the majority logic output of the output line 4. . However, in the error protection method using majority logic, the number of bits to be stored is large, and storage elements corresponding to the number of bits are required.

In other words, in order to determine whether the signal values that account for the majority (=P or more) of (2P-1) consecutive serial input signals are "1" or "0", generally (2P-1) It is necessary to process the majority logic for bits, and for that purpose (
2P-1) storage elements must be provided. Here, P is a positive integer. SUMMARY OF THE INVENTION An object of the present invention is to configure a signal error protection circuit using a smaller number of storage elements, and to prevent continuous signals of a predetermined bit length (P bits) or more from among serial input signals. The object of the present invention is to provide a signal processing system equipped with an error protection means that detects only changes and ignores signal changes with a bit length shorter than that (P-1 bits or less).

Although the processing content of the present invention is slightly different from the error protection based on the conventional majority logic described above, it can be expected to have the same effect as the conventional method in terms of removing temporary signal changes. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a signal processing system showing one embodiment of the present invention.

The signal bus 203 includes an input buffer register 202,
Arithmetic circuit 204, accumulator 205, memory 20
6 and an output buffer 207 are connected.

Memory 206 stores signal data and control programs.

A control signal is generated by sequentially reading and decoding the instructions of the control program, and the operation of each register 202, 205, 207, memory 206, and arithmetic circuit 204 is controlled by this control signal (not shown). . The signal data stored in the memory 206 consists of 1-bit status data and q (= [10g2P)) bit counter data.
It is only data, and the number of storage elements is (1+[10g2P
)) pieces are sufficient. Note that the status data refers to the current status "1".
” or “0”, and in the case of an exchange, it indicates an idle state or a busy state. Also, the symbol [10g2P] represents the smallest integer equal to or larger than 10g2P,
For example, 2 when P=3, 3 when P=8, P=
When P=9, it is 4, and when P=15, it is also 4. When a new signal input arrives at the input buffer register 201 via the input signal 201, the following steps are performed according to the instructions of the control program.

[Step 1] The value of the input buffer register 202 and
The value of the state data of the signal data in the memory 206 is compared.

As a result of the comparison, the two values are equal (if not, the count data in the memory 206 is cleared to 0 and the process jumps to step 3. If the result of the comparison is that the two values do not match, the process proceeds to step 2). [Step 2] Add 1 to the count data in the memory 206 to make sure the count data is over.
Check whether it has flowed or not.

If it does not overflow, proceed to step 3; if it does, invert the state data value,
Then, clear the count data to 0 and proceed to step 3. [Step 3] Transfer the status data from the memory 206 to the output buffer 207, and if a new signal is input, return to step 1.

Since the above processing is performed, for example, when detecting only when there is a continuous signal change of 3 or more bits (P = 3)
To do this, 1-bit state data and 2-bit count data are used, and the count data is counted up only when the state data and input signal do not match. The state data value changes from “0” to “1” or “1” from the time of input.
” to “O”.

By constantly outputting the state data value, signal changes due to noise etc. can be ignored and only true state changes can be detected. Further, in this case, the memory 206 may have only three data storage elements.

FIG. 3 is a block diagram of a signal processing system showing another embodiment of the present invention.

In FIG. 3, it can be operated only by hardware, and includes a state-holding flip-flop 301 and a counter 30.
2, an exclusive OR circuit 303, and a NOT circuit 304.

The state-holding flip-flop 301 has a signal value of "1".
Alternatively, it holds "0" and outputs its state value from the output line 310 in synchronization with the clock signal on the clock line 306.

In addition, the exclusive OR circuit 303 (and the signal input line 305
It receives input from the output line 310, and outputs "1" when both signal values do not match, and outputs "0" when they match.
This output signal is input to the force counter 302 via the counter input line 307, at the same time it is inverted through the NOT circuit 304, and is input to the counter 302 via the counter reset line 308. As a result, if the input signal value and the state value of the state flip-flop 301 do not match, the counter 302 is counted up, and if they match, the counter 302 is reset. When counter 302 overflows, an overflow output is output on counter output line 309, and the state value of state holding flip-flop 301 is inverted by this output value.

For example, when detecting only continuous signal changes of P bits or more, the counter 302 may have [lOg2P] bits.

FIG. 4 is an operation state transition diagram of FIG. 3, and shows a case where P=3.

In FIG. 4, the state {S8, s^, s corresponds to the state when the state-holding flip-flop 301 is in the state "O", and the state {S?, s}, sf} corresponds to the state when the state-holding flip-flop 301 This corresponds to when the state is "1".

For example, if a signal "1" is input in state S^, s9
Transition to.

Next, when a signal "1" is input in state SA, an overflow output signal is output from the counter 302 and state S? Transition to. In this way, the state-holding flip-flop 3
When three input signals different from the state of 01 are input in succession, the state is inverted for the first time, and if there are two or less, the state is maintained and the output counter value is cleared. Even in the case of P, the state {s^~S8} and the state {S}~s? }about,
Perform the exact same action. FIG. 5 is an explanatory diagram of the processing contents of the signal processing method according to the present invention, and shows the case where P=3. If you use the method shown in Figure 2 or 3, even if there is an input of ``0'' at times (5) and (6) as shown in Figure 5 (upper row), So time (4) and (6
), even if there is an input of "1", it is assumed that this is a signal temporarily mixed in by external noise etc., and the input signal sequence is 1NPS.
Removed from G1, 2 and output signal sequence 0UTSG1, 2
Output. If such signal processing is performed using a conventional method using majority logic, it generally requires storage elements for (2P-1) bits, but according to the method shown in FIG. 2 or 3, It is only necessary to provide a total of (1+[10g2P)] memory elements, one for holding the state and [lOg2P] for the counter. For example, when P=3, the majority logic method requires 5 elements, whereas the present invention requires only 3 elements, and when P=5, the former requires 9 elements. The latter requires four elements, whereas the latter requires four elements. As explained above, according to the present invention, only continuous signal changes of a predetermined bit length (P bits) or more in a serial input signal are detected, and signal changes of a bit length less than that (P-1 bits or less) are detected. This has the advantage that the amount of metal materials can be reduced because a circuit that ignores this can be constructed using an extremely small number of memory elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram and operation explanation diagram of a conventional signal processing system using majority logic, FIG. 2 is a block diagram of a signal processing system showing an embodiment of the present invention, and FIG. A block diagram of the signal processing method showing an example, Fig. 4 is similar to Fig. 3.
The operation state transition diagram in the figure and FIG. 5 are explanatory diagrams of the processing contents of the signal processing method according to the present invention. 1: Signal line, 2: Clock line, 3: Signal error protection circuit, 4: Output line, 201, 305: Input signal line, 202:
Input buffer register, 203: Signal bus, 204:
Arithmetic circuit, 205: Accumulator, 206: Memory, 207: Output buffer, 208, 310: Output signal line, 301: State holding flip-flop, 302: Counter, 303: Exclusive OR circuit, 304: Not circuit, 306: Clock line, 307: Counter input line, 30
8: Counter reset line, 309: Counter output line,
CLK: clock signal, INPSG: input signal string, OU
TSG: Output signal string, Sg-, S? ...: State position.

Claims (1)

[Claims] 1. A first storage means for 1 bit that holds a signal state, and has a number of bits equal to the minimum integer value greater than or equal to log_2P in order to count a predetermined number of consecutive bits P after the serial input signal is inverted. a second storage means, which sequentially compares the serial input signal and the contents of the first storage means, resets the contents of the second storage means when they match, and resets the contents of the second storage means; The contents before the clock are output as they are, and when they do not match, the contents of the second storage means are counted up, and when the contents of the storage means overflow, the contents of the first storage means one clock before are output. A signal processing method characterized by inverting the content and outputting it.