JPS5825314B2 - remote monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a remote monitoring device with improved pulse integration means.

In a remote monitoring device, when pulse input from a slave station is integrated at the master station, conventionally the input pulse is treated as a 1-bit digital input (supervision), and this is reproduced at the master station and sent to the counter as a digital output. It is accumulated.

However, such means is inconvenient in the case of the 1:N cyclic method because it can only be applied when the period of the input pulse is sufficiently longer than the scan period.

As an integration method that improves these drawbacks, a counter is installed on the slave station side to integrate the input pulses, and the integrated value (for example, 6 digits BCD - 24 bits) is transmitted as a digital input, and this is reproduced on the master station. There are methods that display numerical values, but this method requires a large amount of information to transmit one integrated value (2 words are required for 24-bit transmission), so the disadvantage is that the transmission efficiency deteriorates. be.

The purpose of the present invention is to provide a remote monitoring device that can perform high-speed pulse input integration while minimizing the increase in the amount of information and hardware required for transmission, and that does not perform abnormal integration even if the power supply fails at the master station and slave stations. Our goal is to provide the following.

In the present invention, a slave station is provided with a buffer counter that integrates input pulses, a master station is provided with a corresponding buffer memory, and the count value of the buffer counter is taken into the buffer memory every time a cyclic scan is performed. The increment of the content is exchanged into a pulse train and integrated by an integrator, and the slave station and the master station are provided with means for preventing abnormal integration when a power supply failure occurs.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a conceptual block diagram of an apparatus that is the premise of the present invention.

In FIG. 1, 1 is a master station, 2 is a slave station, 3 is a communication line connecting the two, and 4 is an integrator.

The slave station 2 has a buffer counter 21, a scanner 22, a parallel/direct converter 23, and a modulator 24.

A buffer counter 21 is provided for each integration input point and integrates input pulses.

Respective input converters are also provided for other various inputs (circuits).

The count value of the buffer counter 21 and the outputs of various other input converters are sequentially sent to the parallel/direct converter 13 by the scanner 22.
The signal is connected to the communication line 3, is converted into a serial signal, is modulated by the modulator 14, and is sent to the communication line 3.

The master station 1 includes a demodulator 11, a serial/parallel converter 12, and a distributor 1.
3 and a pulse train restorer 14.

A pulse train restorer 14 is provided for each integrated output point, corresponding to the buffer counter 21 of the slave station 2.

Respective output converters are also provided for other various outputs (circuits).

The signal on the communication line is demodulated by a demodulator 11, converted into a parallel signal by a serial/parallel converter 12, and sequentially given to a pulse train restorer 14 and other output converters by a signal distributor 13.

The pulse train restorer 14 includes a buffer counter 21 of the slave station 2.
The count value of is given.

The pulse train restorer 14 has a buffer memory 141, a servo counter 142, a comparator 143, and an inhibit gate 144.

The count value of the buffer counter 21 of the slave station 2 is written into the buffer memory 141 by the distributor 13 .

Servo counter 142 counts clock pulses applied through inhibit gate 144.

The capacity of the servo counter 142 is equal to the capacity of the buffer counter 21 of the slave station.

The contents of the buffer memory 141 and the count value of the servo counter 142 are compared in a comparator 143, and when the two values match, the inhibit gate 144 is closed by the output of the comparator 143.

Therefore, clock pulses are applied to the servo counter 142 until its count value matches the contents of the buffer memory 141, and thereby the count value of the servo counter 142 changes in accordance with the contents of the buffer memory 141.

Therefore, the number of clock pulses input to the servo counter 142, ie, the number of output pulses of the inhibit gate 144, is equal to the increase in the contents of the buffer memory 141.

Buffer counter 2 of slave station 2 is stored in buffer memory 141.
Since a count value of 1 is being sent, the total number of output pulses of the inhibit gate 144 eventually becomes equal to the total number of input pulses of the slave station 2.

In other words, the input pulse train of the slave station 2 has been restored by the pulse train restorer 14 in the master station 1.

The output pulses of the inhibit gate 144 are integrated by the integrator 4.

The integrator 4 is provided on the supervisory control panel. In such a device, the capacity of the buffer counter 21 of the slave station 2 is made as small as possible without overflowing during the effective reading cycle of the master station 1.

This capacity is determined by the reading cycle of the master station 1 and the frequency of the input pulse, but usually about 12 bits is sufficient.

If the capacity of the buffer counter 21 is set to such a value, the buffer counter 21 will count input pulses while overflowing.
Since the pulse train also follows while overflowing, there is no problem in the pulse train restoration operation.

Furthermore, since the capacity of the buffer counter 21 is such that no overflow occurs during the effective reading cycle of the master station 1, the difference between the count value read each time into the buffer memory 141 of the master station 1 and the previous read value is , buffer counter 2
It does not exceed the capacitance value of 1.

Therefore, by the operation of the servo counter 142, the increase in the counted value each time is correctly restored as the number of pulses.

As a result, the buffer counter 21, buffer memory 14
4 and the servo counter 142 may have a small capacity, and the amount of information required to transmit the integrated value from the slave station 2 to the master station 1 may also be small.

If the power supply fails in the master station 1 or slave station 2 of such a device, each counter may malfunction and abnormal accumulation may occur.

During a power outage, the counter stops and the integration stops, and the integrated value during the power outage period is missing, but this is not a big problem.

However, when power is restored, there is a possibility that abnormal integration may occur due to uncertainty in the count value of the counter, which is a problem.

That is, due to the nature of the servo counter 142, if there is a difference between its count value and the value stored in the buffer memory 141, a counting operation is performed and a count pulse is given to the integrator. Even if an apparent difference occurs, a count pulse is generated and integrated by the integrator 4.

The difference between the values of the buffer memory 141 and the servo counter 142 occurs not only when power is restored to the master station 1, but also because the buffer counter 21 has lost its previous count value when the power to the slave station 2 is restored.

Therefore, in the master station 1 and the slave station 2, it is necessary to provide means for preventing abnormal integration caused by restoration of power supply.

A remote monitoring device according to an embodiment of the present invention provided with such means is shown in FIG.

In FIG. 2, the same parts as in FIG. 1 are given the same symbols.

FF1 is a flip-flop circuit provided in slave station 2 to hold its energization recovery flag, which is set when the power supply voltage is restored to normal by a signal given from the on-power clamp circuit (circuit), and is set by the signal given from the on-power clamp circuit (circuit). It will be reset at an appropriate time based on the instructions of

This energization recovery flag is transmitted to the master station as one bit of the transmission word. FF2 is a flip-flop circuit provided in the master station 1 and holds the energization recovery signal, G1 is an OR gate, and e is an AND gate. be.

The flip-flop circuit FF2 is an on-power switch in the master station 1.
It is set by a signal given from a clamp circuit (circuit) when the power supply voltage is restored to normal.

The output of the on-power clamp circuit is also given to the buffer memory 141 and servo counter 142 as a clear signal.

OR game 1 is the logical sum of the Q output of flip-flop circuit FF2 and the energization recovery flag of slave station 2 transmitted from slave station 2.
- Provided by G1 to the AND gate ring and controls its opening and closing.

AND gate G2 gives a write pulse to buffer memory 141 to servo counter 142 as an initial value load command.

The same data as the data written to the buffer memory 141 is given as an initial value.

The initial value load command is also given to the flip-flop circuit FF2 as a reset signal.

The flip-flop circuit FF2 is reset at the edge after the initial value load command.

In such a device, the operation when the power supply is restored is as follows.

When a power failure occurs in the slave station 2 and the power is restored, the flip-flop circuit FF1 is set, and the energization recovery flag is transmitted to the master station 1 together with the count value of the buffer counter 21.

In the master station 1, the received count value is applied to the buffer memory 141 and the servo counter 142, a tag energization recovery flag is applied to the AND gate ringing through the or game 1-01, and then a write pulse is generated.

The write pulse is applied to the buffer memory 141 and also to the servo counter 142 through the open AND gate G2.

Therefore, the received count value of the buffer counter 21 is written into the buffer memory 141 and the servo counter 142 at the same time.

Comparator 143 therefore produces a match output, which causes inhibit gate 144 to be closed and no clock pulses to be output.

In other words, immediately after power is restored to the slave station 2, the buffer counter 21
Even if the previous count value is lost, the integrator 4 does not perform abnormal integration due to this.

When the power recovery flag of slave station 1 is reset, the anime
) Since G2 is closed, the backup counter 21 is
Since the new count value is written only to the buffer memory 141, the pulse train restoration operation starts for the increment of the count value by the follow-up operation of the servo counter 142, and the totalization is performed for the previous value held by the integrator 4. will be held.

When a power failure occurs in master station 1 and the power is restored, the flip-flop circuit F is activated by the output of the on-power clamp circuit.
F2 is set.

Q output of flip-flop circuit FF2 is OR gate G1
is given to AND Gate G2 through and opens it.

The output of the on-power clamp circuit also clears the contents of buffer memory 141 and servo counter 142.

As a result, the contents of the two are forced to match, and differences due to uncertainty at the time of restoration of power are removed.

Therefore, no count pulse is generated to the integrator 4, and abnormal integration is prevented.

Thereafter, the first received count value of the buffer count 21 is simultaneously written into the buffer memory 141 and the servo counter 142 by a write pulse, and after this write, the edge after the write pulse causes the flip-flop circuit FF2
is reset and the AND gate is closed.

Thereafter, the new count value of the buffer counter 21 is written only to the buffer memory 141, pulse train restoration is started by the follow-up operation of the servo counter 142 in response to the increment of the count value, and the integration by the integrator 4 is restarted.

However, the integrator 4 is a mechanical integrator or a counter belonging to a power supply system different from that of the master station 1.

In this way, in the device shown in Fig. 2, when a power outage occurs in master station 1 or slave station 2, the number of input pulses is only lost during the power outage period, and no abnormal accumulation occurs due to the uncertainty of the counter when power is restored. It is highly reliable because there is no

As described above, according to the present invention, it is possible to obtain a remote monitoring device that can integrate input pulses at high speed while suppressing increases in the amount of information and hardware required for transmission as much as possible, and has a function to prevent abnormal integration when power is restored. A remote monitoring device equipped with this can be realized.

[Brief explanation of the drawing]

Figure 1 is a conceptual configuration diagram of the device that is the premise of the present invention;
The figure is a conceptual configuration diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Master station, 11... Demodulator, 12... Serial/parallel converter, 13... Distributor, 14... Pulse train restorer,
141... Buffer memory, 142... Servo counter, 143... Comparator, 144... Inhibit gate, 2... Slave station, 21... Buffer counter,
22...Scanner, 23...Parallel/Direct converter, 24.
...Modulator, 3...Communication line, 4...Integrator.

Claims (1)

[Claims] 1. The slave station includes a buffer counter that integrates input pulses, a first flip-flop circuit that holds the energization recovery flag of the slave station, and a energization recovery signal that is the count value of the buffer counter and the output of the first flip-flop circuit. The master station is equipped with a transmitter that sends a flag signal to the transmission line.
A receiver that receives a signal from a transmission line, inputs the count value of the buffer counter from the receiver, stores it by a write command from the receiver, and clears this stored value by a power recovery signal from the master station. A buffer memory, an inhibit gate that is closed by the match signal shown below at a control terminal and blocks the passage of clock pulses, and an inhibit gate that has a capacity equal to that of the buffer counter, and the counted value of the buffer counter from the receiver is inputted to the load input terminal as an initial value. A servo counter to which the output pulse of the inhibit gate is input to a count input terminal and whose count value is cleared by a power recovery signal from the master station, a value stored in the buffer memory and a count value of the servo counter are input; a comparator whose output terminal is connected to the control terminal of the inhibit gate, a second flip-flop circuit which holds the energization recovery signal of the master station, and an output of the second flip-flop circuit. A logical OR signal with the energization recovery flag of the slave station given from the receiver and a write command to the buffer memory are input, and the output is given to the servo counter as an initial value load command, and the output is sent to the second flip-flop. A remote monitoring device comprising: an AND gate that is applied as a reset signal to an input circuit; and an integrator that integrates output pulses of the inhibit gate.