SU1599863A1 - Data exchange device - Google Patents

Abstract

The invention relates to computing and can be used to exchange data between remote local subsystems via a communication channel. The purpose of the invention is to expand the functionality by providing an analysis of the state of the communication line, diagnosing faults and returning the device to a working state. The essence of the invention is that it eliminates the effect of random interference on the operation of the device, monitors the state of the communication line during information transfer, and in the event of a line failure, generates a diagnostic message about the type of link damage (open or short circuit). ). This goal is provided by the introduction of new elements and links. The introduction of a software reset unit and its connections allows the upper level system to detect the device hang up condition. The introduction of a diagnostic message generation unit with appropriate connections allows the issuance of diagnostic messages to the upper level system, and in the event of a device "hanging up" as a result of the interference, it is possible to recognize the fact of "hanging up" and take the device out of operation. The introduction of the link matching and analysis unit with its communications allows recognition of link damage (open circuit, short circuit) and a corresponding message to be taken to take prompt measures to restore the communication link. Introduction of a timer with its connections allows one to monitor the execution of the program of operation of the device by monitoring the time of execution of individual program blocks and, upon exceeding this time, issue an appropriate message to the upper level system. 2 hp f-ly, 5 ill.

Description

The invention relates to computing and can be used in computing systems. for interfacing local subsystems through communication channels.

The purpose of the invention is to expand the functionality by providing an analysis of the state of the communication line, diagnosing faults and returning the device to a working state.

Figure 1 presents the block diagram of the proposed device; figure 2 is a functional block diagram of a software reset; , in FIG. 3 - the same, the communication unit with the trunk; 4 is the same, the diagnostic message generation unit; FIG. 3 - the same, the link matching and analysis unit.

The device for data exchange (Fig. 1) contains a software reset unit 1, a communication unit 2 with a trunk, an interrupt unit 3, a diagnostic message generation unit 4, a linear input / output unit 5, a communication link analysis and analysis unit 6, a unit 7 firmware control, clock generator 8, timer 9, the first memory block 10, the control decoder 11, the second memory block 12, the device’s main address input 13, the device’s main control input 14, the device’s informational input-output 15, exit 16 preorgoana whether a device input 17 of the device 17, an address bus 18., a data bus 19, a control bus 20, a connection 21 between the device input 13. and a group of address inputs of blocks 1 and 4, a connection 22 between the device input 14 and a group of control the inputs of blocks 1 and 4, the connection 23 between the output of block 1 and the reset input of block 7, the connection 24 between input-output 15 of the device, the group of information inputs-outputs of block 2 and the group of information outputs of block 4, connection 25 between the confirmation output the capture unit 7 and the input unit 2, the connection 26 between the second code of unit 2 and the input request for the capture unit a 7, a link 27 between the first output of block 2 and the first interrupt request input of block 3, a link 28 between the first output of the block and the fourth interrupt request input of block 3, a link 29 between the output of block 4 and the second input of the block 3 distortion request, connection 30 between the sixth output of block 11 and the write enable input of block 4, connection 31 between the second output of block 6 and the third input of block 5, connection 32 between the serial inputs / outputs of blocks 5 and 6, connection 33 between the first output of block 3 and the request for interruption of block 7, link 34 between the output of block 9 and the third m entrance for

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millet block 3, connection 35 between the first output of block 11 and the gate input of block 3, connection 36 between the third output of block 11 and the synchronous input of block 5, connection 37 between the second output of block 8 and the synchronous inputs of blocks 9 and 5, respectively, connection 38 between the first output of block 8 and the synchronous input of block 7, the connection 39 between the fifth output of block 11 and the trigger input of block 9, the connection 40 between the second output of block 11 and the gate input of block 10, connection 41 between the fourth output of block 11 and the gate input block 12.

The software reset unit 1 (Fig. 2) contains a comparison element 42 and a switching field 43. Block 1 performs the formation of a Reset signal that sets the device to its initial state. The Reset signal is generated programmatically by a command from the upper level system through inputs 13, 14. Receiving a command to generate a signal Reset is performed to start the device during the initial start or to restart (removing the device from the hung state when analyzing the diagnostic message from block 4).

The communication unit 2 with the trunk (FIG. 3) contains the trigger 44, the first decoder 45, the first data buffer 46, the address counter 47, the command and control register 48, the second data buffer 49, the second decoder 50. The block 2 is intended to organize information exchange and control signals between the upper level system and the internal interface of the device, as well as to generate an interrupt signal to the block 7 upon restarting the device. The diagnostic message generation unit 4 (FIG. 4) contains a buffer register 51, a first control decoder 52, a register 53, a second control decoder 54, a trigger 55. Unit 4 receives diagnostic messages from block 7, generates a distortion signal in block 3 , as well as increasing the diagnosis-. messages to the upper level system.

Block 6 matching and analysis of the communication line (Fig.5) contains a demodulator 56, a modulator 57, the first resis

torus 58, comparator 59, an input transformer 60 consisting of primary | And secondary windings, an output transformer 61 containing a primary winding and two secondary, a second resistor 62. Unit 6 electrically coordinates the device parameters with the parameters of the communication line, provides the module signals in the link — and demodulation of signals received from the link. In addition, block 6 generates an interruption signal in the event of a link failure.

Interlock 3 is designed to generate an interrupt signal to the upper level system based on the signals generated by the device blocks during the execution of the device operation algorithm, and in accordance with the priority set by block 7.

Block 3 can be implemented on the basis of the known chip KR580BH59.

Line 5 I / O block. it is intended for byte-by-byte conversion of a parallel information code into a serial code issued on a communication line, S. also for converting information in a serial code received from a communication channel into a parallel code.

Unit 5 can be executed on the basis of a known microcircuit, for example, type KP580BB51, and functions according to the algorithm known for this microcircuit.

Firmware control block 7 is designed to organize the operation of device blocks and control the exchange of data in accordance with a specified network protocol, for example, the well-known HDLC protocol.

Block 7 can be performed on a known chip, for example, KR580BN80. The purpose of the inputs and outputs and the algorithm for implementing the commands of block 7 are completely similar to those known for microprocessors of the specified type.

The clock generator B is designed to form clock and synchronization signals coordinating the operation of the device units .. It can be performed on a known chip of the K580GF24 or INTEL 8224 type.

Timer 9 is designed to form time intervals with which the control device

The correctness of the execution of the algorithm of operation. As timer 9, an interval timer chip can be used; KR580VI53; Timer 9 operates according to the algorithm known for this type of chip.

The first memory unit 10 is an on-line memory device and is intended for the storage of operational information. It may be implemented on the basis of known K537RU10 microcircuits.

The control decoder generates the control signals initiating the operation of individual units of the device during the implementation of the functioning algorithm.

The second memory block 12 is a permanent storage device for storing a program of operation of the proposed device. It can be implemented on the basis of K556RT4, K556RT5, K573RF4 microcircuits.

The exchange of information, address and control signals between the device and the upper level system is carried out via an interface trunk, which can be constructed in accordance with a known interface protocol, such as IC1.

The device is connected to the interface trunk via the main address input 13, the main control input 14, the main information input-output 15.

Information is exchanged between block 7 and blocks 2-5, 9, 10, 12 and the address signals sent to block 11, through which the selected blocks are initialized, through an internal interface bus containing the address bus 18, data bus 19 and control bus 20.

The operation of the device is carried out according to the program stored in block 12. The entire program is divided into separate program blocks, the execution time of each of which is known. Before executing the current program block, its code number is entered into block 4, the contents of which can be read by the upper level system. At the same time, block 7 adjusts timer 9 to countdown the execution time of the current v

block. Upon completion of the execution of the current program block, a similar procedure is carried out before starting the next program block, etc.

The device works as follows. I

After turning on the power, the vBepxHero level system through block 1 brings block 7 to the initial state and through block 2 writes 10 rest bytes of restart into the allotted cell of the block, after which the first output of block 2 forms an interrupt signal, which is transmitted through block 3 to block 7.-Blo 7 accesses block 10, reads the restart byte and analyzes it.

At the initial start-up, unit 7 sets up unit 5 to receive and transmit and goes into standby mode of a command from the upper level system to transmit information to the communication line.

The upper level system accesses block 2 via inputs 13, 14 and inputs / outputs 15 captures the internal interface trunk and writes the necessary information into the allocated memory area of block 10 byte-by-bit. When the internal interface highway is captured, a second signal is generated at the second output of block 2 capture (ZHB). By this signal, the output unit 7 generates a capture confirmation signal (PZHV) and translates the group address outputs, information inputs-outputs and control 1 outputs connected to the address bus, the data bus and the control bus of the device’s internal interface bus, high impedance condition.

At the end of the recording of information in block 10, the upper level system writes down 10 bytes of information transfer to the communication line in the allocated memory cell of the block.

Block 7 counts from the allotted cell bytes of the transmission flag and rewrites the information from block 10 to block 5 byte-by-byte.

After transmitting the first byte of information to the communication link, block 5 forms a word state byte in which it indicates that it is ready to transmit the next byte.

Block 7 reads word bytes, analyzes it and bit by bit

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Readiness reads to block 5 the next information byte.

Before outputting information to the communication line, block 7 sets the timer 9 for the time required to transmit information to the communication line, and simultaneously writes the code number of the program block to block 4.

The information supplied to the communication line from block 5 in the serial code, through the input-output 32 enters the block 6. In block b, the analysis of the state of the communication line is carried out.

In the event of a short circuit, the communication line, on the first output of block 6, an interruption signal is generated, which through block 3 is transmitted to block 7. In this case, block 7 stops transmitting information to the link, forms a diagnostic message for the upper level system and through the internal interface trunk enters it into block 4. At the same time, at the output of block 4, an interrupt signal is generated, which enters block 3 and further into the upper level system.

A pedal, by issuing each information byte to the communication line, block 7 reads 5 bytes from the word state from the block and analyzes the receiver readiness bits (GPRM) and transmitter (GORD).

When a communication link is broken, the information sent to the line through the input-output of the block .6 enters the input-output of block 5, which in this case generates the readiness bit of the receiver (GPRM) in the word state byte. If, in the process of transmitting, in a byte, the words are conformed to the bit of the GPRM, block 7 perceives this as an interruption of the communication line. At the same time, it stops the information in block 5, generates the corresponding diagnostic message for the upper level system and enters it in block 4.

After the transfer of information to the communication line has been completed, block 7 writes to block 4 the code of the next Program block, sets timer 9 for the waiting time of the receipt from the communication line, and goes to the waiting mode of the receipt.

Upon receipt of the first byte from the communication line, block 5 in the word state byte generates a GPRM bit, from which block 7 reads from information block 5 and writes it to the allocated memory area of block 10. In the same way, all information is received from the communication line. After completion of receiving information from the communication line, unit 7 generates a corresponding message to the upper-system. This level enters into block 4. On the output of block 4, an interrupt signal is generated, which through block 3 is transmitted to the upper level system. In the process of transmitting information to a link, as a result of interference, a device may hang, which appears to be outputting an unauthorized infinite length of information to the link. In this case, upon the expiration of the control time allotted for transmitting information to the communication line, timer 9 generates an interrupt signal that goes to block 3, and from there to block 7. At the same time, block 7 organizes a repeated information flow to the link. If the situation does not change as a result of repeated information, block 7 generates a diagnostic message to the upper level system and enters it into block A. At the output of block 4, an interrupt signal is generated, which is transmitted through block 3. to the upper level system.

If, as a result of the interference, block 7 is in such a state that it does not respond to the interrupt signal from timer 9, then the device can be brought out of a hang state from the upper-level system. In this case, the upper level system, determining that the device does not perform the specified function, reads the state of its registers from block 4, analyzes the received information and, based on the result of the analysis, restarts the device. In this case, the upper level system refers to block 1, as a result, the output signal of block 1 generates a signal for setting block 7 to its initial state. In this case, the upper level system can restart the device both from the starting point of program execution, and from a given program block. The restart mode is determined by the contents of the restart status byte, which is entered by the upper level system into the allotted memory cell of the block 10.

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Block 7 nfcjra. The installation signal on it reads 10 restarts from the restart from the block and enters the appropriate mode of operation.

Block 1 works as follows.

An address code assigned to the device is set on the switching lola 43. When comparing on the element 42 of the code specified on the switching field 43 with the address code formed on the bus 21, and in the presence of a control signal coming over the bus 22, the installation signal of the block 7 is formed at the output of block 1.

Information exchange between the device and the upper level system is performed using block 2 (FIG. 3), which operates in two modes: initial setup of block 2 for writing / reading information from block 10; direct procedure of recording / reading information by the upper level system when operating with the unit 10 of the device.

In the initial block setting mode. As for system 2, the upper level system writes the initial memory address of block 10 to the address counter 47, and the Write (REC) or read (CTN) command to the 48 command and control register. At the same time, the upper level system on the 21 and 22 generates the corresponding signals that go to the remote controller 45. The output of the decoder produces a signal that enters the data buffer 46 and allows the passage of information Q from the bus 24 to the counter 47 of the address. At the same time, a signal is generated at the output of the decoder 45, which is fed to the counter 47 of the address and permits the recording of information from the bus 24 into it.

When entering the command rec or chtn in the register of 48 commands and control, the decipher 45 commands generates signals arriving in the buffer 46 0 data and the register of 48 commands and control. On these signals, the contents of the bus 24 are recorded in the register of 48 commands and controls.

In the mode of direct recording / reading of information when operating with,, block 10, the decoder 45, according to the corresponding signals at its input, generates control signals that trigger buffer 46 and pe0

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gistr 48 command and control. In this case, the output 26 of block 2 generates the signal ZHB entering the block 7. In turn, unit 7 generates a signal of the FILTER which is transmitted through communication 25 to the input of the counter 47 of the address and connects its outputs to the address bus 18. In addition, the PZHV signal is fed to the input of the decoder 45. In this case, the decoder 45 generates a control signal that allows information to pass through the buffer 49. data on the bus 19 data. At the same time, the decoder 45 generates a control signal, which is fed to the input of the register of 48 commands and controls. At the output of register 48, a LAP or CTN command is sent to bus 20. To generate an interrupt signal to block 7, the decoder 45, using signals from the upper level system (bus 21, 22), generates a trigger setup signal 44 in one state. The flip-flop 44 is reset to the zero state by a signal from the output of the decoder 50 in the presence of the corresponding signals on the tires 18 and 20 generated by the block 7.

Block 4 (figure 4) works as follows.

During the operation of the device, the code 53 of block 4 records the code of the current program block. The recording is performed by applying to the inputs 18 and 20 the corresponding address and control signals generated by block 7. If there is a control signal at input 30 from block 1, the second output of the control decoder 54 produces a signal on which information from bus 19 is entered into register 53.

When the device executes the current program block, the code of the next program block, etc., is entered into the register 53 of the block 4.

The reading of the code stored in register 53 is performed by the top level system if the device does not perform the specified functions.

In this case, if the inputs 21 and 22 have corresponding address and control signals on the second output of the control decoder 52, a signal is generated and the register is transmitted to the output 24.

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The diagnostic message is written to the register 53 of block 4 in the same way as described above. However, at the first output of the decoder 54, the corresponding address code at the input 18 generates a signal that sets the trigger 55 in the unit state. At the same time, at output 29 of block 4, an interrupt signal is generated, which is transmitted through block 3 to the upper level system.

The flip-flop 55 is reset by the upper level system after reading the information from the register 53.

Block 6 (figure 5) works as follows.

In the mode of transmitting information to the communication line, information in the serial code through input-output 32 is fed to the modulator 57, where the Scallock modulates signals that go to the communication line. From the output of the modulator 57 through a resistor 58, the signals go to the primary winding of the output transformer 61.

When a load is connected (the load is a communication line with a characteristic impedance Zg equal to the resistance of the resistor 62), the line 6 input-output 17 of block 6 generates a signal connected to the communication line.

The input and output transformers 60 and 61, together with the resistor 62 and the connected communication line (in FIG. 5, the signal conditionally shown as the communication line), represent the resistor Zg) are a balanced bridge. The first and second secondary windings of the output transformer 61 form two one; bridge arm, resistors 62 and Zg - the other two.

When informing the communication line, the potential of the signal at the connection point of the first and second secondary windings of the output transformer 61 is zero and equal to the potential at the connection point of resistors 62 and Z. At the same time, no current flows through the primary winding of the input transformer 60. Thus, when matching the communication line with the linear input-output of block 6 in the mode of transmitting information to the communication line, there is no signal at the input of demodulator 56.

When the link mismatch, i.e. when Z is infinitely large resistance (line break) or zero (there is a short circuit

The Research Institute of Communications, the balance of the bridge is disturbed. In this case, as information flows to the communication line, a current begins to flow through the primary winding of the input transformer 60. In this case, the signal from the secondary winding of the input transformer 60 arrives at the input of the demodulator 56, and a signal is generated at the first output of the demodulator 56 that notifies that information is available at the input of the demodulator 56.

Thus, in the information transfer mode to the communication line, the presence of a signal at the first output of the demodulator 56 indicates a break or short circuit in the communication line.

With a short circuit. in the communication line, i.e. when Z is zero, the current flowing through the first and second secondary windings of the output transformer 61 is more than doubled. Accordingly, the current flowing through the primary winding of the transformer 61 increases. This increases the voltage drop across the resistor 58, which leads to the operation of the comparator 59. At the output of the comparator, an interrupt signal is generated, which goes to block 3 and then to block 7 and informs it line faults.

Thus, in the mode of transmitting information to the communication line, the presence of signals in connections 31 and 28 indicates a short circuit in the communication line. The presence of a signal in the communication 31 and the absence of a signal in connection 28 indicates a break in the communication line,

In the mode of receiving information from the communication line, signals from the communication line through the input transformer 60 arrive at the input of the demodulator 56, where they are demodulated. At the first output of the demodulator, a potential is formed, indicating reception of information from the communication line, and at the second output of the demodulator 56, information signals in the sequential code, which are then fed to block 5.

Claims (3)

Invention Formula to A device for data exchange, containing a communication unit with a trunk, an interrupt unit, a linear input-output unit, a clock generator, the first to a second memory block, control 1599863 14 0 0 five A firmware decoder, a firmware control block whose address address group is connected via the address bus to the address input groups of the interrupt unit, linear input / output unit, first and second, memory unit, control descrambler, and address input-output group of the block connection with the trunk, the group of information inputs and outputs of the microprogram control unit via the data bus is connected to the first group of information inputs / outputs of the communication unit with the highway, to. groups of information inputs / outputs of the first memory block, linear input / output unit, block of interrupt 5 to the group of information outputs of the second memory block, group of control outputs of the microprogram control block via the control bus connected to the first group of control inputs of the block cb bridges with the main and control inputs of the prerange unit, the first to the second memory blocks, the linear I / O block, the first to the fourth outputs of the control decoder, are connected, respectively, with gates odes prershany unit, the first and second memory blocks, the block-vtoda linear input, the communication unit to the backbone via a group of address inputs, a second group of control. inputs, the second group of information inputs-outputs are connected to the corresponding main inputs-outputs of the device, the first and second outputs of the communication unit are connected to the main line respectively to the first input of the interruption request of the interruption unit and the capture request of the microprogrammed control unit whose capture acknowledgment output is connected to the gate input of the communication unit with the trunk, the first output of the interrupt unit is connected to. the interrupt request input of the MIIK-program control unit, the synchronous input of which is connected to the first output of the clock generator, the second output of which is connected to the synchronous linear I / O unit, the second output of the interrupt unit is the terminating output of the device, as such that in order to extend the functionality by providing an analysis 0 five 0 five 0 51 state of communication line in device a software reset unit, diagnostic message generation unit, a timer, the synchronization input of which is connected to the second clock generator output, a communication line matching and analysis unit, and a triggering timer input are introduced to the fifth output of the control digester, the second output of which is connected to the resolution input recordings of the diagnostic message generation unit, the strobed output of which is connected to the second input of the interruption request of the distortion block, the third and fourth inputs of the request of which are connected respectively to the output timer and the first output of the link matching and analysis unit, the second output is connected to the transfer enable input of the linear I / O unit, the serial input / output of which is connected to the information input / output of the matching and analysis link, and the output of the communication matching and analysis unit is the device’s line input / output; the output of the software reset unit is connected to the reset input of the firmware control unit, a group of address and control inputs of the software unit reset and the first groups of address and control inputs of the diagnostic message generation unit are connected to the corresponding device inputs, and the group of information outputs of the diagnostic message generation unit is connected to the main information input-output devices of the device, the second group of address inputs of the diagnostic message generation unit and the timer input group through The address bus is connected to the address output group of the firmware control block, the second group of control inputs The diagnostic message generation area and the timer control input group are connected via the control bus to the microprogram control output control group, the information input group of the diagnostic message generation unit and the information input-output timer group are connected via the data input-output group microprocessor control unit. 0 five 863 sixteen 2, The device according to claim 1, wherein the diagnostic message generation unit comprises a buffer register, first and second control decoders, a register, a trigger, the output of which is the gate output of the block, the R and S inputs of the trigger connected to the first outputs of the first and second control defibrators, the second outputs of the first and second control breakers, respectively, are connected to the write inputs of the buffer register and the register, the information input of the block is connected to the input of the register, and its output is from groups th five 0 five 0 five information inputs of the buffer register, whose outputs are a group of information outputs of the block, the address and control inputs of the second control decoder are connected respectively to the second groups of address and control inputs of the block, the address and control inputs of the first control decoder are connected respectively to the first groups of address and the control inputs of the block, the strobing input of the second control decoder is connected to the input of the recording resolution of the block. 3. The device according to claim 1, characterized in that the matching and analysis unit of the communication line contains a demodulator, a modulator, an input and output transformers, the first and second matching resistors, a comparator, the output of which is the first output of the unit, the first output the demodulator is connected to the second output of the block, the second output of the demodulator and the input of the modulator are information input-output, the input of the demodulator through the secondary The input transformer winding is connected to the common bus of the block, the modulator output is connected via the first terminating resistor and the primary winding of the output transformer is connected to the secondary bus of the block, the comparator input is connected to the first matching resistor and the primary winding of the input transformer, the beginning of the primary winding of the input transformer the second terminating resistor is connected to the beginning of the first secondary winding of the output transformer, the end of which is connected to the beginning of the second secondary winding of the output 17159986318 the transformer and the end of the primary format and the end of the second secondary coil of the input transformer, the start of the output transformer winding the input input primary winding are transferred by the linear input-output of the block 1 21 P P Jf 41 25 27 21 25 18 Fig.} 4S Fig 24 20 26 nineteen 14 GT1 G II // 2 J Flash. SI L 32 . ffS Jl. // yy hij r 55 60 ICP 61 n 59