SU1635282A1 - Device for control of switchboard - Google Patents

Description

(21) 4674978/09

(22) 04/05/89

(46) 03/15/91. BKHP. N-10

(75) V.А.Huralnik

(53) 621.395.664 (088.8)

(56) USSR author's certificate

No. 902308, cl. H 04 M 3/22,

03/19/80.

(56) DEVICE FOR THE CONTROL OF A COMMUTATION STATION

(57) The invention relates to telecommunications. The purpose of the invention is to increase the reliability of the control. The device contains a counter 1 call register 2

shift, counter 3 failures, analyzer 4 cycles and counter 5 cycles. Analyzer 4 consists of a one-shot, register, memory, comparators, a constant sensor, and a switch. At the end of each monitoring cycle, the contents of counter 5 increase. Counter 3 records the number of failures in the cycle, and register 3 reflects the state of the monitored station. Analyzer 4 generates Estimates More, Less or Equal to one output - with respect to the previous control cycle, pa another - with respect to a given rate. 1 epf-ly, 2 Il.

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FIG. one

The invention relates to telecommunications and can be used to control the quality of service on switching telephone and telegraph stations.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 shows the structural electrical circuit of the proposed device, FIG. 2 the same, the analysis of the torus cycle.

The device for monitoring the switching station contains a call counter 1, a shift register 2, a failure counter 3, a cycle analyzer 4 and a cycle counter 5, the analyzer 4 cycles containing a single vibrator 6, a memory register 7, the first and second comparators 8,

9, the sensor 10 constants and switch 11.

The device works as follows.

In its original state, all the nodes are zeroed. When connections are established in the controlled switching station, the call signals (the jobs are received at the input of the call counter 1, in which they accumulate, and at the clock input of the shift register 2). In the latter, each work pulse generates a data shift by one bit, the fault pulses arrive at the signal input of shift register 2, which is a serial data input, is therefore recorded at the first discharge of register 2; shift 1 is written down. The capacity of shift register 2 is equal to the capacity of call counter 1, but in counter 1 of calls the data is In the last shift, 1 and O (from right to left) correspond to the sequence of calls without refusal (O) and calls with refusal (1), i.e., in binary-decimal or binary code, and in shift register 2. the shift register 2 during the control cycle determined by the capacity of the counter 1 and register 2 retains the unfolded (sequential in time) pattern of the dynamics of operation of the monitored station.

At the same time, the failure pulse arrives at the counter addition input of the 3 failures, which is reversible, where the data on the failures are accumulated,

At the end of each monitoring cycle (overflow of the 2 call counter) from the output of the 1 call counter, when it returns to the initial state by one, the contents of the 5 cycle counter increase.

At the same time, through the first input of the analyzer 4, a pulse at the end of the cycle is fed to the one-shot 6, which is started. A one-shot pulse is a read pulse for memory register 7. The data on its signal input comes from the counter 3 output of the failures through the second input of the analyzer 4. Now the number of failures in the past control cycle will be stored in the register - 7 PLMP - until the end of the next cycle,

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data. Intermediate data of an x-cycle through the output of the counter 3 failures can be submitted to the display tribe (not shown).

From the output of the register 7 bm m., The data stored in it on the failures g of the last cycle is fed to the I - th gh of the comparator I (csgrvc yci, comparison of codes). Pa tporpg; Comparator 8 is constantly (continuously coming through the second, t of the analyzer 4 data from the failure counter 3. Comparator 8 compares them. From its output through the first one; analyzer 4, by a group of wires, the display elements (not shown) receive signals More, Less or Equal Since the data in register 7 of memory is changed by the secret (at the end of the next monitoring cycle), and the 3 failures compared from the counter go to the emperor I, then the first output of the analyzer of the loop is continuously present The best cycle is a fixed duration equal to the duration of a discrete cycle. At the end of a discrete cycle, the duration of which is determined by the call counter 1, the data in memory register 7 is changed and the comparison of subsequent current data is performed with new data, i.e. all the time, the failures of the current sliding cycle are compared with the failures of the previous discrete cycle.

In the second comparator 9, in the same way, failures in the current sliding cycle are continuously compared with the norm (or other value), the value of which is set in the sensor 10 constants and in the form of a digital code enters the comparator 9 while the standards for different switching systems are selected by switch 11. From the output of the comparator 9 through the second output of the analyzer 4, the comparison results, also in the form of signals Bolshaya, Less or Equal, but now in comparison with the standard, go to the display elements. In addition, readings from the outputs of counters 1, 3.5 of calls, refusals and cycles can be taken on the elements of the display or recording on technical media, if necessary, of exact digital data.

Thus, the device operates in the first control cycle. But since before it ends, the number of erne calls is not enough for a reliable estimate, the main operation mode of the device starts from the second monitoring cycle (after the first call counter overflows). It differs from the one considered in that now from the output of the register 2 shift to the input of the subtraction of the counter 3 failures, data can also be received. This happens if some call number of the previous cycle ended with a failure. In this case, at the output of the shift register 2, 1 appears (when calling without refusing its output O) and the contents of the failure counter 3 will decrease by one. It will happen with the same call number of the next (in this case, the current) cycle. If this call number in the previous cycle was without refusal, then the contents of counter 3 will not change. Thus, from the second cycle, the contents of counter 3 always correspond to the number of failures per complete sliding cycle. At the moment of the overflow of the counter 1 call, the counter 3 of failures contains data about the failure in the next discrete cycle.

Claims (2)

1. A device for controlling a switching station that contains a call counter and a failure counter, which is designed to increase the reliability of the control by introducing a shift register, a cycle analyzer and a pick counter, while the signal and clock inputs of the shift register are connected respectively to the input addition of the failure counters and with the input of the call counter, the output of which is connected to the input of the cycle counter and to the first input of the cycle analyzer, the second input of which is connected to the output of the failure counter, the input of which readout is connected output shift register. 2. The device according to claim 1, wherein the cycle analyzer comprises a serially connected one-shot, the input of which is the first input of the cycle analyzer, a memory register and the first comparator and a series-connected constant sensor, a switch and a second comparator, the second input of which is connected to the second input of the first comparator and the signal input of the memory register, which is the second input of the loop analyzer, the first and second outputs of which are the outputs of the first and second comparators, respectively. 0 five 7 eleven FIG. 2