JPS5947471B2 - Method for manufacturing insulated gate field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing an insulated gate field effect semiconductor device, and particularly to a method of forming a high impurity concentration region such as a channel stopper in these semiconductor devices.

In integrated circuits using insulated gate field effect elements such as MOS type elements, impurity diffusion of channel stoppers is often performed for electrical insulation between elements, which is an essential condition especially in N-channel MOS type integrated circuits. ing. This channel stopper is formed by diffusing impurities having the same conductivity type as the substrate impurities. The higher the impurity concentration, the better the effect as a channel stopper, but if the impurity concentration is too high in the area where this impurity region overlaps with the source or drain of the MOS transistor, the junction breakdown voltage will decrease, so the range of this impurity concentration is naturally limited. come. Therefore, in conventional integrated circuits, the channel stopper region and the source and drain regions are arranged so as to be separated on a mask. However, since the photosensitive resin used for selective etching has more or less pinholes, portions that are etched on the pinholes also occur outside the predetermined area during selective etching. Therefore, when high-concentration impurity diffusion is performed, the yield rate decreases in the conventional manufacturing method due to breakdown voltage deterioration due to the pinholes. Therefore, in reality, the impurity concentration of the channel stopper portion cannot be selected regardless of the withstand voltage. The present invention provides a method that can safely realize a high concentration region such as a high impurity concentration channel stopper compared to conventional methods.

The present invention includes a step of depositing an insulating film and an oxidation-resistant film on a semiconductor substrate, and selectively providing a first mask layer on the oxidation-resistant film. a step of selectively removing a portion of the oxidation-resistant coating that has not been removed to expose a portion of the insulating coating thereunder; forming a high concentration impurity region under an opening in the second mask layer spaced apart from the oxidation-resistant film; This method of manufacturing an insulated gate field effect semiconductor device includes the step of forming a thick oxide film on a portion of the semiconductor substrate where the oxidation-resistant film is not provided, using the oxidation-resistant film as a mask.

According to the present invention, the impurity region can be controlled to have an impurity concentration of 10<16> or more.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will now be described with reference to the drawings.In order to simplify the explanation, an N-channel MOS in which a channel stopper is essential will be described.

In the embodiment of the present invention, first, as shown in FIG. 1A, the impurity concentration is 3×10 15 /C! ! A silicon oxide film 2 with a thickness of 500 to 2,000 λ and a silicon nitride film 3 of 700 to 3,000× are grown on a P-type silicon substrate 1 of t, and only the silicon nitride film 3 is selectively removed using a photosensitive resin 4 using fluorine gas plasma.

Next, as shown in FIG. 1B, a photosensitive resin 1 is selectively placed to cover the silicon nitride film 3, and the exposed portion of the silicon oxide film 2 is etched using a hydrofluoric acid-based etching solution. Next, as shown in FIG. 1C, using the silicon oxide film 2 and the silicon nitride film 3 as masks, p+ boron is diffused in a temperature range of 770 C to 920 DEG C. to form a p+ diffusion region 5. Here, if there is a pinhole in the photosensitive resin 4 and l on the silicon nitride film 3, the pinhole in the photosensitive resin 4 will create a pinhole in the silicon nitride film 3VC, but no pinhole will occur in the silicon oxide film 2, and the photosensitive resin 4′
(7) Since the silicon nitride film 3 covers the entire pinhole, no pinhole is formed by etching the silicon oxide film 2. Furthermore, as is clear from FIG. 1B, the thickness of the photosensitive resin 1 on the side where the silicon nitride film 3 is not present is thicker, so that no penetrating pinholes are generated. Further, even if a thin pinhole exists here, it does not substantially affect the withstand voltage since it is far from the source/drain region. Therefore, in this method, pinholes are generated on the active region only when the pinholes of the photosensitive resins 4 and 4'f) overlap, and it can be said that this does not occur at all in terms of probability.

That is, the p+ poron diffusion region 5 does not necessarily occur outside the predetermined region. Next, as shown in FIG. 1D, using the nitride film 3 as a mask, +P boron oxidation is performed at a temperature of 900° C. to 1140° C. to form a silicon oxide film 6 with a film thickness of 0.7 to 1.4 μm. Using as a mask, the silicon oxide film 2 and the silicon nitride film 3 are removed by etching for a predetermined period of time using an etching solution containing hydrogenated oxygen and phosphoric acid, respectively.

Then, by forming an insulated gate transistor on the exposed silicon substrate by a known method, an N-channel MOS integrated circuit will be formed. The n+ phosphorus diffusion regions 7 and 8 of the source and drain formed at this time are separated from the p+ boron diffusion region 5 by the mask alignment, and the junction breakdown voltage is independent of the impurity concentration of the p+ boron diffusion region 5 and the impurity concentration of the substrate 1. It is determined by Therefore, the impurity concentration of the p+ boron diffusion layer 5 can be set to a high value determined solely for the purpose of serving as a channel stopper. The present invention has been explained above regarding N channels, but P
It is clear that similar effects can be obtained with channels.

In the embodiment of the present invention, a silicon nitride film is used as the oxidation-resistant film, but other materials such as alumina film, tantalum,
Molybdenum and the like can also be used if the etching solution is considered. Further, the high impurity concentration region formed according to the present invention can be used not only as a channel stopper but also for other purposes, and its conductivity type may be opposite to that of the substrate. Further, its formation is not limited to diffusion, but may also be performed by other means such as ion implantation. Further, the thick oxide film 6 may be omitted and a normal field film may be used.

[Brief explanation of the drawing]

FIGS. 1A-1D are cross-sectional views showing an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, and 3 is a silicon substrate.
is an oxidation-resistant film, 4 and l are photosensitive resin, 5 is an impurity diffusion region having the same conductivity type as the substrate, 6 is a thick silicon oxide film, 7 and 8 are source and drain regions, and 9 is a wiring aluminum layer. .

Claims (1)

[Claims] 1. A step of depositing an insulating film and an oxidation-resistant film on a semiconductor substrate, and selectively providing a first mask layer on the oxidation-resistant film, and a process in which the first mask layer is not provided. selectively removing a portion of the oxidation-resistant coating to expose the underlying portion of the insulating coating; and the exposed insulator on the remaining oxidation-resistant coating and adjacent to the oxidation-resistant coating. a step of providing a second mask layer on a portion of the coating, forming a high concentration impurity region under an opening in the second mask layer spaced apart from the oxidation-resistant coating; and removing the remaining oxidation-resistant coating. A method for manufacturing an insulated gate field effect semiconductor device, comprising the step of forming a thick oxide film as a mask on a portion of the semiconductor substrate where the oxidation-resistant film is not provided.