JPS5946869A - プリント板の診断方法 - Google Patents

プリント板の診断方法

Info

Publication number
JPS5946869A
JPS5946869A JP57157772A JP15777282A JPS5946869A JP S5946869 A JPS5946869 A JP S5946869A JP 57157772 A JP57157772 A JP 57157772A JP 15777282 A JP15777282 A JP 15777282A JP S5946869 A JPS5946869 A JP S5946869A
Authority
JP
Japan
Prior art keywords
flip
log
flop
pin
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57157772A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0233105B2 (enrdf_load_html_response
Inventor
Hisao Hidaka
日高 久男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57157772A priority Critical patent/JPS5946869A/ja
Publication of JPS5946869A publication Critical patent/JPS5946869A/ja
Publication of JPH0233105B2 publication Critical patent/JPH0233105B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
JP57157772A 1982-09-10 1982-09-10 プリント板の診断方法 Granted JPS5946869A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57157772A JPS5946869A (ja) 1982-09-10 1982-09-10 プリント板の診断方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57157772A JPS5946869A (ja) 1982-09-10 1982-09-10 プリント板の診断方法

Publications (2)

Publication Number Publication Date
JPS5946869A true JPS5946869A (ja) 1984-03-16
JPH0233105B2 JPH0233105B2 (enrdf_load_html_response) 1990-07-25

Family

ID=15656958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57157772A Granted JPS5946869A (ja) 1982-09-10 1982-09-10 プリント板の診断方法

Country Status (1)

Country Link
JP (1) JPS5946869A (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPH0233105B2 (enrdf_load_html_response) 1990-07-25

Similar Documents

Publication Publication Date Title
US4312066A (en) Diagnostic/debug machine architecture
DE19952272A1 (de) Verfahren und System zum Prüfen von auf eingebetteten Bausteinen basierenden integrierten Systemchip-Schaltungen
DE19948388A1 (de) Verfahren und System zum Prüfen eingebetteter Speicher
DE68927306T2 (de) Emulationssystem, fähig zur Anpassung an Mikrorechner mit verschiedenen On-Chip-Speicherkapazitäten
US4847838A (en) Circuit for testing the bus structure of a printed wiring card
JPS5946869A (ja) プリント板の診断方法
US6675323B2 (en) Incremental fault dictionary
US7523367B2 (en) Method and apparatus to verify non-deterministic results in an efficient random manner
EP0640919B1 (de) Prozessorschaltung mit Testeinrichtung
US20240418778A1 (en) Method and system for testing blocks within device under test (dut) using reconfigurable test logic
JPH08136614A (ja) 回路試験装置
Szygenda et al. Fault insertion techniques and models for digital logic simulation
JP2964746B2 (ja) プリント板回路の自動検証処理方法
Wang et al. A new validation methodology combining test and formal verification for PowerPC/sup TM/microprocessor arrays
JPH029370B2 (enrdf_load_html_response)
Giambiasi et al. SILOG: a practical tool for large digital network simulation
EP0231948A2 (en) Simulation system
JP3018886B2 (ja) プローブ設定方法
McClure Fault simulation of digital logic utilizing a small host machine
JPS58205262A (ja) Lsiの試験方法
JPS63134970A (ja) スキャンテスト回路生成装置
Peterson TESTING THE HP-65 LOGIC BOARD.
DE69621100T2 (de) Kodehaltepunktdekoder
CN116523410A (zh) 一种基于fpga的组合逻辑实验自动评分系统及方法
JP2744461B2 (ja) 回路設計システム