JPS5945527A - バス制御方法 - Google Patents

バス制御方法

Info

Publication number
JPS5945527A
JPS5945527A JP57156143A JP15614382A JPS5945527A JP S5945527 A JPS5945527 A JP S5945527A JP 57156143 A JP57156143 A JP 57156143A JP 15614382 A JP15614382 A JP 15614382A JP S5945527 A JPS5945527 A JP S5945527A
Authority
JP
Japan
Prior art keywords
bus
signal
processor
cluster
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57156143A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0583942B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Masaharu Yabushita
藪下　正治
Makoto Nomi
能見　誠
Nobuyuki Fujikura
藤倉　信之
Shoji Miyamoto
宮本　捷二
Koichi Ihara
廣一 井原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57156143A priority Critical patent/JPS5945527A/ja
Priority to DE8383108742T priority patent/DE3381602D1/de
Priority to EP83108742A priority patent/EP0103803B1/en
Priority to US06/530,078 priority patent/US4641237A/en
Publication of JPS5945527A publication Critical patent/JPS5945527A/ja
Publication of JPH0583942B2 publication Critical patent/JPH0583942B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
JP57156143A 1982-09-07 1982-09-07 バス制御方法 Granted JPS5945527A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57156143A JPS5945527A (ja) 1982-09-07 1982-09-07 バス制御方法
DE8383108742T DE3381602D1 (de) 1982-09-07 1983-09-05 Bus-steuerverfahren.
EP83108742A EP0103803B1 (en) 1982-09-07 1983-09-05 Bus control method
US06/530,078 US4641237A (en) 1982-09-07 1983-09-07 Bus control method and apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57156143A JPS5945527A (ja) 1982-09-07 1982-09-07 バス制御方法

Publications (2)

Publication Number Publication Date
JPS5945527A true JPS5945527A (ja) 1984-03-14
JPH0583942B2 JPH0583942B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-11-30

Family

ID=15621261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57156143A Granted JPS5945527A (ja) 1982-09-07 1982-09-07 バス制御方法

Country Status (4)

Country Link
US (1) US4641237A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0103803B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5945527A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3381602D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008509493A (ja) * 2004-08-13 2008-03-27 クリアスピード テクノロジー パブリック リミテッド カンパニー プロセッサメモリシステム

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833605A (en) * 1984-08-16 1989-05-23 Mitsubishi Denki Kabushiki Kaisha Cascaded information processing module having operation unit, parallel port, and serial port for concurrent data transfer and data processing
JPH0746308B2 (ja) * 1985-07-24 1995-05-17 株式会社日立製作所 表示制御装置およびマイクロコンピュータ・システム
CA1263760A (en) * 1985-09-27 1989-12-05 Alan L. Davis Apparatus for multiprocessor communication
AU586120B2 (en) * 1986-09-02 1989-06-29 Amdahl Corporation A method and apparatus for arbitration and serialization in a multiprocessor system
DE3708887A1 (de) * 1987-03-19 1988-09-29 Martin Neschen Paralleler datenbus
US5257374A (en) * 1987-11-18 1993-10-26 International Business Machines Corporation Bus flow control mechanism
US4958303A (en) * 1988-05-12 1990-09-18 Digital Equipment Corporation Apparatus for exchanging pixel data among pixel processors
US5101480A (en) * 1989-05-09 1992-03-31 The University Of Michigan Hexagonal mesh multiprocessor system
US5396599A (en) * 1990-01-16 1995-03-07 Nec Electronics, Inc. Computer system with a bus controller
US5233692A (en) * 1990-04-06 1993-08-03 Micro Technology, Inc. Enhanced interface permitting multiple-byte parallel transfers of control information and data on a small computer system interface (SCSI) communication bus and a mass storage system incorporating the enhanced interface
JP2501737B2 (ja) * 1992-02-28 1996-05-29 インターナショナル・ビジネス・マシーンズ・コーポレイション デ―タ転送方法及び装置
US6260093B1 (en) 1998-03-31 2001-07-10 Lsi Logic Corporation Method and apparatus for arbitrating access to multiple buses in a data processing system
US7668190B1 (en) * 2003-12-31 2010-02-23 Marvell International Ltd. Method for supporting multiple devices on a high speed physical link
US20060031622A1 (en) * 2004-06-07 2006-02-09 Jardine Robert L Software transparent expansion of the number of fabrics coupling multiple processsing nodes of a computer system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5629731A (en) * 1979-08-16 1981-03-25 Nec Corp Multiplex bus control system

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3984819A (en) * 1974-06-03 1976-10-05 Honeywell Inc. Data processing interconnection techniques
DE2742035A1 (de) * 1977-09-19 1979-03-29 Siemens Ag Rechnersystem
US4320452A (en) * 1978-06-29 1982-03-16 Standard Oil Company (Indiana) Digital bus and control circuitry for data routing and transmission
US4229791A (en) * 1978-10-25 1980-10-21 Digital Equipment Corporation Distributed arbitration circuitry for data processing system
US4384327A (en) * 1978-10-31 1983-05-17 Honeywell Information Systems Inc. Intersystem cycle control logic
US4390944A (en) * 1980-05-13 1983-06-28 Bti Computer Systems System for controlling access to a common bus in a computer system
FR2494010B1 (fr) * 1980-11-07 1986-09-19 Thomson Csf Mat Tel Dispositif d'arbitration decentralisee de plusieurs unites de traitement d'un systeme multiprocesseur

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5629731A (en) * 1979-08-16 1981-03-25 Nec Corp Multiplex bus control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008509493A (ja) * 2004-08-13 2008-03-27 クリアスピード テクノロジー パブリック リミテッド カンパニー プロセッサメモリシステム

Also Published As

Publication number Publication date
JPH0583942B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-11-30
US4641237A (en) 1987-02-03
EP0103803A3 (en) 1986-08-20
DE3381602D1 (de) 1990-06-28
EP0103803B1 (en) 1990-05-23
EP0103803A2 (en) 1984-03-28

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