JPS5944893A - Method of producing multilayer printed circuit board - Google Patents

Method of producing multilayer printed circuit board

Info

Publication number
JPS5944893A
JPS5944893A JP15604782A JP15604782A JPS5944893A JP S5944893 A JPS5944893 A JP S5944893A JP 15604782 A JP15604782 A JP 15604782A JP 15604782 A JP15604782 A JP 15604782A JP S5944893 A JPS5944893 A JP S5944893A
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
multilayer printed
coupling agent
inner layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15604782A
Other languages
Japanese (ja)
Inventor
陽一 金子
博 鈴木
「よし」田 純男
敏夫 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP15604782A priority Critical patent/JPS5944893A/en
Publication of JPS5944893A publication Critical patent/JPS5944893A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 杢発明は多層印刷回路板の製造法、詳しくけ、多層印刷
回路板の内部に埋込葦7”Lる内層回路板の回路鋼箔の
前処理法に関すな〇 多層印刷回路板は、あらかしめ内層回路ケ形成した印刷
回路板ケガラス繊維勿用い1こ織布、不餓布等の丞材に
エホヤシ側j1ば、ポリイミド4υj脂等(L)fP硬
化性樹脂ケ言αし半イ便化状態にし/こプリグレグ奮ブ
vして必吸枚#I虚ね付−欧て〃11熟力1」圧全施し
プリグレグ會硬化芒せる多層化接泊により、内層回路4
iiケグリグレグγ介して内部に卯込んで製造している
。。
[Detailed Description of the Invention] The present invention relates to a method for manufacturing a multilayer printed circuit board, and more particularly, to a method for pre-treating circuit steel foil for an inner layer circuit board with reeds embedded within the multilayer printed circuit board. A multilayer printed circuit board is a printed circuit board with a pre-stamped inner layer circuit formed. Glass fiber is not required, and additional materials such as woven cloth and nonwoven fabric are used on the side, and polyimide 4υj resin, etc. (L) fP curable resin is used on the side. The inner layer is fully compressed and the pre-greg is hardened by multi-layer bonding to make it semi-convenient. circuit 4
ii It is manufactured by inserting it inside through the Kegrigreg γ. .

従来よりこ(/J棟の多層印刷回路板の装造に2いて中
1!」層に用いら扛/)内層回路板の回路井」論にはあ
らかじめ表面を裏]用(マット聞)と同セを度の粗さに
した両面粗化銅?ゐ、あるいにさし〕に七の回路銅箔表
面に酸化皮膜形成処理′?r:施したりして各層間(/
J接層性ケ良くしている。しかし両りm粗化銅舶におい
ては通n′の片面粗化銅量に比較し、てコストが高くつ
くと共に粗化面の安定化が不十分である。また龍化皮膜
形成処理’I−J’M台はスルーホールメッキ形成時に
おける岐性故処理に劣!l銅箔表面と側脂間(/、)接
層性の低下が生じる。
Conventionally, this (/used in the construction of multi-layer printed circuit boards in the J Building, 2nd and 1st layer!/) The circuit wells of the inner layer circuit boards was prepared with the front surface on the back. Double-sided roughened copper with rough edges?ゐ、And then there is the oxide film forming treatment on the surface of the circuit copper foil in 7? r: Between each layer (/
It has good J contact properties. However, in the case of both m-roughened copper, the cost is higher and the roughened surface is not sufficiently stabilized compared to the single-sided roughened copper of n'. In addition, the 'I-J'M machine with the Ryuka film formation process is inferior to the process of branching when forming through-hole plating! l Deterioration of contact between the copper foil surface and the side fat occurs.

本発明はこり工う1点に鑑みてlさILlζもので、銅
箔による回路パターンが形成81’した内層回路板ケ、
熱硬化性樹脂r端拐に含浸乾燥し穴グリグレグケ介して
内部に埋込む多層印刷回路板の製造法に於て、内層回路
板ンプリグレグケ介して内部に埋込む前に、内層回路板
の回路銅箔表面に酸化皮膜を化成した佼、シランカップ
リング剤で処理すること2を時機とするものであ/b。
The present invention has been made in view of one point of difficulty in manufacturing, and includes an inner layer circuit board on which a circuit pattern of copper foil is formed 81';
In the manufacturing method of multilayer printed circuit boards, the inner layer circuit board is impregnated with a thermosetting resin, dried, and then embedded inside through the holes. It is a method in which an oxide film is chemically formed on the surface and treated with a silane coupling agent 2.

丁lわち本発明は多層印刷回路板り製盾工程においてあ
らかじめ内層回路ケ形成した印刷「1」銘板り忰j箔堀
面に酸化皮膜ケ化敗8せた俊、そυ表面會R31Xs(
世しRPI有機官能基、X&:1硅累原子と結付した加
水分計性の基)で表芒fLるシランカップリング剤で処
理するものである。
In other words, the present invention is a multilayer printed circuit board manufacturing process in which an oxide film is oxidized on the printed "1" name plate with an inner layer circuit formed in advance on the foil moat surface, and the surface R31Xs (
The surface of the RPI organic functional group (X&: a hydrometer group bonded to a silicon atom) is treated with a silane coupling agent.

内層回路82(1)回路銅箔表面に酸化皮膜全化成する
には、水酸化ナトリウム、リン酸三ナトリウム、亜塩素
酸ナトリウム(IJ混混水水浴液浸漬処理するりが好ま
しい。
Inner layer circuit 82 (1) circuit In order to completely form an oxide film on the surface of the copper foil, it is preferable to immerse the copper foil in a water bath containing sodium hydroxide, trisodium phosphate, or sodium chlorite (IJ mixed water).

水酸化ナトリウム6〜+ Og/1.  リン酸三ナト
リウム5〜20 g/71.亜塩素酸ナトリウム10〜
50 g/lの組成りものが特に好ブしい。
Sodium hydroxide 6~+ Og/1. Trisodium phosphate 5-20 g/71. Sodium chlorite 10~
A composition of 50 g/l is particularly preferred.

上記(/J量を超えると酸化皮膜形成速度がはやく安定
した均一酸化皮膜層が得らILない又上記の量未満の場
8は形成連装が遅く処理が安定しないとともに均一層が
得ら石ない。
If the amount exceeds the above amount (/J), the oxide film formation rate will be fast and a stable uniform oxide film layer will not be obtained.If the amount is less than the above amount, the formation will be slow and the process will not be stable and a uniform layer will not be obtained. .

本発明において用いらIしるシランカップリング剤には
例えはγ−アミノグロビルトリエトキシシラン、γ−メ
ルカプトフロビルトリメトキシシラン、γ−クリシトキ
シプロビルトリメトキシシラン、ビニルトリエトキシシ
ラン、♂−グリシドキシメチルジメトキシシランN−β
−ジメトキシシラン等があげらIL4用さrL/+樹脂
に最も増したシランカップリング剤が使用さ1【る0 内層回路板へのシランカップリング剤処理としてはあら
かじめ酸化皮膜を化成しfζ印桐回路板をシランカップ
リング剤c/J0.1〜1o%(垂M%、以下同じ)水
溶液又はメタノールアセトン等の溶液とした中へ浸び【
しその俊5o〜1o。
Examples of the silane coupling agents used in the present invention include γ-aminoglobiltriethoxysilane, γ-mercaptofurobiltrimethoxysilane, γ-crisitoxyprobyltrimethoxysilane, vinyltriethoxysilane, -glycidoxymethyldimethoxysilane N-β
- Dimethoxysilane etc. are used, and the most increased silane coupling agent is used for rL/+ resin for IL4.1 [ru0] As for the silane coupling agent treatment on the inner layer circuit board, an oxide film is chemically formed in advance, and Immerse the circuit board in a solution of silane coupling agent C/J 0.1 to 1o% (M%, same hereinafter) or methanol acetone.
Shisono Shun 5o-1o.

℃で乾燥し溶媒を除去′Tゐ方法がある。There is a method of removing the solvent by drying at ℃.

父、対応できる樹脂としてはエホキシ位・1脂、ポリイ
ミド樹脂等C/J辿常の熱硬化性樹脂がおけらnる。
Resins that can be used include C/J thermosetting resins such as epoxy resin and polyimide resin.

実施例1 あらかじめエポキシ樹脂を使用した銅張積層板(両面板
)に内層形路を形成し印刷回路板としたも(/Jk次の
方法に、cv処理しlt。
Example 1 A copper-clad laminate (double-sided board) using an epoxy resin was prepared with an inner layer path formed in advance to make a printed circuit board (/Jk).The following method was followed by CV treatment.

脱脂→粗化→水洗→(水酸化ナトリウム0.5%+リン
ば三ナトリウム1%十亜塩累岐ナトリウム5%)水溶欣
70℃、1分1hJ浸偵→水抗→シラン処理(日本ユニ
カー製曲品名A11+2o。
Degreasing → roughening → washing with water → (sodium hydroxide 0.5% + trisodium phosphorus 1% sodium decathate 5%) aqueous solution 70°C, 1 minute 1 h J immersion → water resistance → silane treatment (Nippon Unicar Product name: A11+2o.

N−β−(アミノエテル)−γ−アミノグロヒルトリメ
トキシシラン)1%水水溶液泥流1間浸漬→乾燥100
’C,50分間この印A11lj回路板を図面に下す構
成により加熱加圧(圧力6okg/(1)11編度17
0℃5時間120分)ケ行い多層化接層し多M機t1′
「成した。得らfL、た多層板(/、1%性を表1に示
す。
N-β-(aminoether)-γ-aminoglohiltrimethoxysilane) 1% aqueous solution mud flow 1 hour immersion → drying 100
'C, for 50 minutes, heat and pressurize this mark A11lj circuit board according to the configuration shown in the drawing (pressure 6 ok/(1) 11 knitting 17
0°C 5 hours 120 minutes) Multi-layer bonding and multi-M machine t1'
The obtained multilayer board (/, 1%) is shown in Table 1.

尚1図面中1に印刷回路板(内層)、2に回路銅箔、5
はプリプレグ、4は銅箔である。
In addition, in one drawing, 1 is printed circuit board (inner layer), 2 is circuit copper foil, 5 is
4 is prepreg and 4 is copper foil.

実施12す2 実施例1と同じ条件でシラン処理りシランカップリング
剤をγ−クリシドキシグロビルトリメトキシシツン(信
越化学製商品名KBM−406)にかえ1%水溶液冨渦
1分間浸漬として多N板を作成した。得らfL、た多層
仮り向性ケ、表1、に示す。
Implementation 12-2 Under the same conditions as in Example 1, the silane coupling agent was replaced with γ-crisidoxyglobiltrimethoxysilane (product name: KBM-406, manufactured by Shin-Etsu Chemical), and immersed in a 1% aqueous solution in a vortex for 1 minute. N board was created. The obtained fL and multilayer tropism are shown in Table 1.

実施例6 実施例1と同じ条件でシラン処理のシランカソゲリング
剤ケγ−アミ7グロとルトリエトキシシラン(日本ユニ
カー社装%曲品名A−1100)1%水溶液室御1分I
MJ役偵として多層板全作成した。得ら7した多層41
!2の特性音、表1、に示す。
Example 6 A silane casso gelling agent treated with silane under the same conditions as in Example 1, gamma-ami7glo and lutriethoxysilane (Nippon Unicar Co., Ltd., product name A-1100), 1% aqueous solution, 1 minute I in a chamber.
As an MJ actor, I created all the multilayer boards. Obtained 7 multilayer 41
! The characteristic sounds of No. 2 are shown in Table 1.

実施例4.5 夷7iI!i?111と同じ条件で、シラン処理浴液跋
度全そ71.ぞ2’1.%  0.1%、10%として
多層板τ作成した。祷ら肛た多層板(/J特1生ケ表1
にンバター8実施例6 実施e111と同条件で、ポリづミド但I脂金使用した
基板ケ使用して多層板を作成した。 4:tら7また多
層板の特性を表1に示す。
Example 4.5 夷7iI! i? Under the same conditions as in 111, the silanization bath liquid concentration was 71. 2'1. % 0.1% and 10%, multilayer plates τ were prepared. Multi-layer board (/J special 1 raw material table 1)
NIN BUTTER 8 EXAMPLE 6 A multilayer board was prepared under the same conditions as in Example e111 using a substrate made of polyamide but also gold. Table 1 shows the properties of the multilayer board.

比較例1.2 実施例1及び実施ヤ06と同条件でシラン処理會行なわ
ないで;t′rLぞt″L多層多層板取作成。曲らnた
多層板の特性を表1にηく丁。
Comparative Example 1.2 A multilayer board was prepared under the same conditions as in Example 1 and Example 06 without performing the silane treatment; .

比較例5 実施例1と1h、1条件で、酸化皮膜形成ケ行なゎj′
に、多層板を作成したQ倚らJ’lた多層板り特性を表
1に示す。
Comparative Example 5 Oxide film formation was carried out under the conditions of Examples 1 and 1h.
Table 1 shows the properties of the multilayer board produced by Q and J'l.

表 1 測定方法 9内1@銅箔引剥し試’4RJIS−C6481・ハン
ダ耐熱性試験  10 Q m+u角に切Fυ「シ1ζ
試験片全260℃リハンダに20秒10jフロートしそ
(/、I抜外観ケ観祭1゛る。
Table 1 Measurement method 9 inside 1@Copper foil peeling test '4RJIS-C6481/Solder heat resistance test 10 Q Cut into m+u angle Fυ"
All test pieces were re-soldered at 260°C for 20 seconds with a float for 10 seconds to observe the external appearance.

O耐項酸性試$2    160 X 30 mmニ切
Wr L表向銅9″i9を除去した試験片に直径1(m
+りの入音56穴あけ19%塩酸に置市させ”C塩酸が
内層面に授か込む1での時間を計測−]−々。
O acid resistance test $ 2 160 x 30 mm square cut Wr L A diameter 1 (m
Drill 56 holes and place in 19% hydrochloric acid and measure the time it takes for hydrochloric acid to infuse into the inner surface.

Q耐塩酸性44]断端早 Q:良(浸み込みがないンΔ
:用() ×:不良(役→込みがあゐ) 実施V117 実施例1と同じ条件で、脱カh−→柑化→水仇→(水[
V化ナトリウム1.5%+リン酸三ナトリウム0.8G
;’o+亜in累ばナトリウム5.2%)水浴畝85℃
、2分6o抄反ζl→水(冗→シラン処理(tlfff
ユニカー製「始品名A−1120%N−β−(7ミ/エ
チル)−γ−アミノノロヒルトリメトキシシラン)1%
水浴液歴編1分向8!頂→乾床+ Oo”c、  30
分子…の処理をして多層板ttt−成した。得らIした
多層叔り有性會、表2に示″J″0 比η0?12す4、5 実施数17とI=J l/宋件で、シンン処理及び鍍化
皮膜り形成才行なわrにそtL、−’f:’n歩層板ヶ
作成したθ狗らfした多層板り特性を衣2にボす。
Q Hydrochloric acid resistance 44] Premature residual limb Q: Good (no seepage)
:Use()
Sodium Vide 1.5% + trisodium phosphate 0.8G
;'o+sodium 5.2%) Water bath ridge 85℃
, 2 minutes 6o reaction ζl → water (redundant → silane treatment (tlfff)
Manufactured by Unicar "Original product name A-1120% N-β-(7mi/ethyl)-γ-aminonorohyltrimethoxysilane) 1%
Water bath liquid history edition 1 minute direction 8! Top → dry bed + Oo”c, 30
A multilayer plate ttt- was formed by processing molecules. The obtained multi-layer structure is shown in Table 2, and the number of tests is 17 and I=J l/Song. Add the characteristics of the multilayer board created by θgu et al. to Cloth 2.

表  2 以上説明し北、J:うに本発明に於てr、1.耐塩岐性
能等諸性能CIJf<n、た多層印刷回路4反ケ得るこ
とがでさるとともに多層1川(/、J4辿り信相性の向
上した多層印刷回路&を得々ことが出来る。
Table 2 As explained above, Kita, J: In the present invention, sea urchin r, 1. It is possible to obtain a multilayer printed circuit with various performances such as resistance to erosion, CIJf<n, and a multilayer printed circuit with improved reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

図面に多層&[J製造法ケ示す断+fu図である。 符+jの説明 1 内層回路基也  2 内層回路ガ;板上り回W6組
箔 5 プリプレグ   4 銅箔
The drawing is a cross-sectional view showing the multilayer & [J manufacturing method. Explanation of sign +j 1 Inner layer circuit base 2 Inner layer circuit ga; board up circuit W6 set foil 5 Prepreg 4 Copper foil

Claims (1)

【特許請求の範囲】 1、 飼司箔に、!:/)回路パターンか形成さrした
内層回路板を、P硬化性側脂を基材に含浸乾燥したプリ
プレグを介して内部に狸込む多層印刷回路板UJ製瑣法
に於て、内層回路板金ブリプレグケ介して内部に埋込む
前に、内1−回路叡の回路鋼箔表面に酸化皮膜r化IJ
又り、た佐、シランカップリング剤で処理すること葡特
徴とする多層印刷回路板の製造法。 2、内層Ifl!J絡板の回路鋼箔表面葡、水酸化ナト
リウム、リン酸三ナトリウム、亜塩素酸ナトリウムの水
沼液で処理し酸化皮膜會化成丁ゐ特?!’F NiV求
り範囲第1項dC1戊り多層印刷回路板の装逅法。 6、 水1イグ化ナトリウムが5〜10g/β、リン酸
三ナトリウムが5〜20’g/6.亜塩素晒ナトリウム
が10〜50g/l′t″あり、シランカップリング剤
での処理を、プランカップリング剤の081〜10%(
垂力t)浴液で行9@訂請求(1)範囲第1項、又tJ
第2項=己載り多層印刷回路板の製R法。
[Claims] 1. To Kaishihaku! :/) In the multilayer printed circuit board UJ manufacturing method, the inner layer circuit board on which a circuit pattern has been formed is inserted into the interior through a prepreg that has been impregnated with P-curable side fat as a base material and dried. Before embedding it inside through the Bripregket, apply an oxide film to the surface of the circuit steel foil.
A method for producing a multilayer printed circuit board characterized by treatment with a silane coupling agent. 2. Inner layer Ifl! The surface of the circuit steel foil of the J-board is treated with a water solution of sodium hydroxide, trisodium phosphate, and sodium chlorite to form an oxide film. ! 'F NiV calculation range 1st term dC1 mounting method for multilayer printed circuit board. 6. Water 1 Sodium iguide 5-10g/β, Trisodium phosphate 5-20'g/6. The amount of sodium chlorite bleached is 10~50g/l't'', and the treatment with the silane coupling agent is 081~10% of the plan coupling agent (
Power t) Line 9 @ Correction request (1) Range 1 with bath liquid, also tJ
2nd term = R method for manufacturing self-mounted multilayer printed circuit board.
JP15604782A 1982-09-08 1982-09-08 Method of producing multilayer printed circuit board Pending JPS5944893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15604782A JPS5944893A (en) 1982-09-08 1982-09-08 Method of producing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15604782A JPS5944893A (en) 1982-09-08 1982-09-08 Method of producing multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS5944893A true JPS5944893A (en) 1984-03-13

Family

ID=15619153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15604782A Pending JPS5944893A (en) 1982-09-08 1982-09-08 Method of producing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS5944893A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260695A (en) * 1989-03-31 1990-10-23 Toppan Printing Co Ltd Copper plated laminated board of multilayer wiring board, and multilayer wiring board
JPH03217075A (en) * 1990-01-22 1991-09-24 Mitsubishi Electric Corp Surface treatment of internal-layer base material for multilayer copper-clad laminated board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5276679A (en) * 1975-12-22 1977-06-28 Hitachi Ltd Method of producing multiilayer printed circuit board
JPS56118394A (en) * 1980-02-22 1981-09-17 Fujitsu Ltd Method of manufacturing multilayer circuit board
JPS56153797A (en) * 1980-04-28 1981-11-27 Hitachi Chemical Co Ltd Method of manufacturing multilayer printed circuit board substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5276679A (en) * 1975-12-22 1977-06-28 Hitachi Ltd Method of producing multiilayer printed circuit board
JPS56118394A (en) * 1980-02-22 1981-09-17 Fujitsu Ltd Method of manufacturing multilayer circuit board
JPS56153797A (en) * 1980-04-28 1981-11-27 Hitachi Chemical Co Ltd Method of manufacturing multilayer printed circuit board substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260695A (en) * 1989-03-31 1990-10-23 Toppan Printing Co Ltd Copper plated laminated board of multilayer wiring board, and multilayer wiring board
JPH03217075A (en) * 1990-01-22 1991-09-24 Mitsubishi Electric Corp Surface treatment of internal-layer base material for multilayer copper-clad laminated board

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