JPS5944867A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5944867A JPS5944867A JP15629382A JP15629382A JPS5944867A JP S5944867 A JPS5944867 A JP S5944867A JP 15629382 A JP15629382 A JP 15629382A JP 15629382 A JP15629382 A JP 15629382A JP S5944867 A JPS5944867 A JP S5944867A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- ion
- region
- type
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 230000001590 oxidative effect Effects 0.000 claims abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 abstract description 14
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 230000001133 acceleration Effects 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 235000013372 meat Nutrition 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置の製造方法の改良に関する。[Detailed description of the invention] (a) Technical field of the invention The present invention relates to an improvement in a method for manufacturing a semiconductor device.
■)技術の背景
シリコン(Si)基板等の半導体基板の素子形成予定領
域内に所定の不純物原子をイオン注入して半導体素子を
形成する方法は、注入後形成される不純物拡散領域が浅
く形成されるので高速で動作する半導体装置の製造に広
く利用されているのは周知である。■) Background of the technology A method of forming a semiconductor element by ion-implanting predetermined impurity atoms into a region where the element is to be formed in a semiconductor substrate such as a silicon (Si) substrate is a method in which the impurity diffusion region formed after implantation is formed shallowly. It is well known that it is widely used in the manufacture of semiconductor devices that operate at high speed.
(0) 従来技術と問題点
このようなイオン注入法を用いたバイポーラヤニCの従
来の製造方法について第1図を用いて説明する。(0) Prior Art and Problems A conventional method for manufacturing bipolar resin C using such an ion implantation method will be described with reference to FIG.
まずP型のSj−基板基板屑定のパターンでN、ipの
不純物原子、例えばアンチモン(Sb)等を拡散あるい
はイオン注入して埋没層2を形成する。First, a buried layer 2 is formed by diffusing or ion-implanting N and ip impurity atoms, such as antimony (Sb), in a P-type Sj-substrate pattern.
その後該基板l上にN型のシリコンエピクキシャ2層3
を形成してから所定パターンでP型の不純物原子例えば
ポロン(B)等を拡散して素子間分離領域4を形成する
。Thereafter, two N-type silicon epitaxial layers 3 are formed on the substrate 1.
After that, P-type impurity atoms such as poron (B) are diffused in a predetermined pattern to form element isolation regions 4.
次に後の工程で形成するトランジスタの寄生MO8効果
等の現象を低下させるための二酸化シリコン(si、o
2)膜5を8000〜4000人の厚さで該基板の熱酸
化により形成する。Next, silicon dioxide (si, o
2) Forming a film 5 with a thickness of 8000 to 4000 nm by thermal oxidation of the substrate.
その後該基板上にホトレジスト膜を厚さl−1,5μt
llで形成しベース形成予定領域上を所定パターンに諾
光、現像により形成する。図で6はこのようにして形成
されたホトレジスト膜である。次に該基板上よりボロン
(B+)原子を矢印Aのようにイオン注入したのち、該
基板を反応管内に導入し該反応管内に水中を通過した酸
素(02)ガスを導入し、反応管内をいわゆるWet0
2i囲気にして反応管を加熱処理してB十原子がイオン
注入されたSQL基板を熱処理し注入されたB十原子を
拡散していた。After that, a photoresist film is applied on the substrate to a thickness of l-1,5μt.
A predetermined pattern is formed on the region where the base is to be formed by exposure to light and development. In the figure, 6 is a photoresist film formed in this manner. Next, boron (B+) atoms are ion-implanted from above the substrate as shown by arrow A, and then the substrate is introduced into a reaction tube, and oxygen (02) gas that has passed through water is introduced into the reaction tube. So-called Wet0
The reaction tube was heat-treated under a 2i atmosphere, and the SQL substrate into which 10 B atoms were ion-implanted was heat-treated to diffuse the implanted 10 B atoms.
しかし従来のこのような方法では、Si基板表面におい
てイオン注入されたB十原子のため、注入後のSi結晶
のS1原子がSlの結晶格子中に規則正しく配列されて
おらず、そのためSlの結晶の原子配列が乱れており、
そのため導入された02ガスと結晶格子よりはみ出たS
i原子の反応によってSi基板表面が荒れて素子特性と
して耐圧が低下するなど欠点を生じていた。However, in this conventional method, due to the ten B atoms ion-implanted on the Si substrate surface, the S1 atoms of the Si crystal after implantation are not regularly arranged in the Sl crystal lattice, and therefore The atomic arrangement is disordered,
Therefore, the introduced 02 gas and the S protruding from the crystal lattice
Due to the reaction of i atoms, the surface of the Si substrate becomes rough, resulting in drawbacks such as a decrease in breakdown voltage as an element characteristic.
また前述の後の工程で形成するトランジスタの寄生MO
3効果を低減させるためのS:lO2膜5が3000〜
4000人とかなり分厚く形成されているので、その5
in2膜を通過して(B+)原子をイオン注入するため
には、加速電圧180に、eV程度迄」二昇させる必要
があり、そのため大がかりなイオン注入装置を必要とし
たり、あるいは加速電圧が大きいためSi基板の結晶面
が乱れたり荒れたりする欠点を生じていた。In addition, the parasitic MO of the transistor formed in the later process described above
3 S:lO2 film 5 to reduce the effect is 3000 ~
It is quite thick with 4,000 people, so part 5
In order to ion-implant (B+) atoms through the in2 film, it is necessary to raise the acceleration voltage to about 180 eV, which requires a large-scale ion implantation device or a large acceleration voltage. Therefore, the crystal plane of the Si substrate is disturbed or roughened.
働 発明の目的
本発明は上述した欠点を除去し、大規模なイオン注入装
置を必要とせずまたイオン注入後のSi基板の結晶面が
荒れないようにした新規な半導体装置の製造方法の提供
を目的とするものである。OBJECT OF THE INVENTION The present invention aims to provide a novel method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, does not require a large-scale ion implantation device, and prevents the crystal plane of a Si substrate from becoming rough after ion implantation. This is the purpose.
(θ)発明の構成
かかる目的を達成するための本発明の半導体装置の製造
方法は、表面に二酸化シリコン膜が形成され、かつ素子
間分離領域で画定されたシリコン基板の半導体素子形成
予定領域内に素子形成用不純物原子をイオン注入して半
導体素子領域を形成する工程を有する半導体装置の製造
に際し、前記基板の半導体素子形成予定領域上の二酸化
シリコン膜の一部を他の領域より薄くしてから不純物原
子をイオン注入後、該基板を非酸化性雰囲気内で熱処理
し、その後酸化性雰囲気内で熱処理する工程を含むこと
を特徴とするものである。(θ) Structure of the Invention In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention provides a semiconductor device manufacturing method in which a silicon dioxide film is formed on the surface and a semiconductor element formation area of a silicon substrate is defined by an element isolation area. When manufacturing a semiconductor device having a step of forming a semiconductor element region by ion-implanting impurity atoms for element formation into the substrate, a part of the silicon dioxide film on the area where the semiconductor element is to be formed of the substrate is made thinner than other areas. The method is characterized by including the steps of ion-implanting impurity atoms from the substrate, heat-treating the substrate in a non-oxidizing atmosphere, and then heat-treating the substrate in an oxidizing atmosphere.
(f) 発明の実施例
以下図面を用いて本発明の一実施例につき詳細に説明す
る。第2図より第7図までは本発明の半導体装置の製造
方法の工程を示す要部断面図である。(f) Embodiment of the Invention An embodiment of the invention will be described in detail below with reference to the drawings. FIG. 2 to FIG. 7 are main part sectional views showing the steps of the method for manufacturing a semiconductor device of the present invention.
まず第2図に示すようにP型の81基板ll上に所定パ
ターンでN型の不純物原子、例えばsb等を拡散してN
型の低抵抗の埋没層121r、形成後、該基板上にN型
の81工ピタキシヤル層13を形成する。First, as shown in FIG. 2, N-type impurity atoms, such as sb, are diffused in a predetermined pattern onto a P-type 81 substrate
After forming the type low resistance buried layer 121r, an N type 81 pitaxial layer 13 is formed on the substrate.
次いで該基板上に所定パターンでP型の不純物原子、例
えばBを拡散してP型の素子間分離領域141を形成す
る。次いでエピタキシャル層18上に厚さ8000オン
グストローム(入)程度の8102膜15を基板の熱酸
化により形成する。このSi、02膜は基板表面がN型
よJP型へ変換するのを防止したり、あるいは後の工程
で該基板にトランジスタ等の半導体素子を形成した際該
トランジスタに生じる寄生MOS効果等の現象を除去す
るものである。Next, P type impurity atoms, for example B, are diffused onto the substrate in a predetermined pattern to form a P type element isolation region 141. Next, an 8102 film 15 having a thickness of approximately 8000 angstroms is formed on the epitaxial layer 18 by thermal oxidation of the substrate. This Si,02 film prevents the substrate surface from converting from N type to JP type, or prevents phenomena such as parasitic MOS effects that occur in transistors when semiconductor elements such as transistors are formed on the substrate in a later process. It is intended to remove.
次いで該基板上に形成した所定パターンのホトレジスト
膜(図示せず)をマスクとしてプラズマエツチング法等
によシトランジスタのべ−x形成予定領域上のSiO2
膜を第3図のように所定のパターンにエツチングして形
成する。Next, using a photoresist film (not shown) with a predetermined pattern formed on the substrate as a mask, a plasma etching method or the like is performed to remove SiO2 on the region where the base x of the transistor is to be formed.
The film is formed by etching into a predetermined pattern as shown in FIG.
次に第4図のように該基板を約800℃の低温度で熱酸
化して前記パターンニングして露出した基板表面を再び
酸化して500人程0薄いSi○2膜16全16する。Next, as shown in FIG. 4, the substrate is thermally oxidized at a low temperature of about 800 DEG C., and the surface of the substrate exposed by the patterning is oxidized again to form a thin Si.sub.2 film 16 of approximately 500 layers.
またこの5102膜16は分厚い酸化膜16を形成後エ
ツチングしても形成できる。The 5102 film 16 can also be formed by etching after forming a thick oxide film 16.
次に第5図に示すように加速電圧50KeV、ドーズ量
8XIO14/adの条件でB十原子を矢印Bの方向か
ら基板18上にイオン注入する。Next, as shown in FIG. 5, ten B atoms are ion-implanted onto the substrate 18 from the direction of arrow B under the conditions of an acceleration voltage of 50 KeV and a dose of 8XIO14/ad.
このようにすればイオン注入してペース領域を形成すべ
き部分上のSiO2膜16が500人と薄く形成されて
いるので、加速電圧が従来の方法に比して低くなり、し
たがって大規模なイオン注入装置が不要となり、またイ
オン注入後のS1基板表面の結晶面も従来に比して損傷
が小さくなり、P型のB+のイオン注入領域17が形成
される。In this way, the SiO2 film 16 on the part where the pace region is to be formed by ion implantation is formed as thin as 500, so the accelerating voltage is lower than in the conventional method, and therefore large-scale ion implantation is possible. There is no need for an implantation device, and the crystal plane on the surface of the S1 substrate after ion implantation is less damaged than before, and a P-type B+ ion implantation region 17 is formed.
次いで該基板を非酸化性の窒素(N2)ガス雰囲気内の
反応管中に導入し、1170℃の温度で40分間熱処理
する。するとイオン注入後のS1基板表面の結晶はS1
原子が正規の格子間位置より位置ずれしているが、非酸
化性のガスを用いて熱処理すると、この位置ず−れして
いるSi原子もこの非酸化性のN2ガスとはあまり反応
せず、したがって基板表面の結晶面の荒れもあまり生じ
ない状態でSi基板が熱処理される。そしてこの熱処理
によって位置ずれしたSi原子が正常なSiの格子間位
置に戻ることになり第6図のように所定の厚さでB原子
が拡散されBの拡散層18が形成されることになる。Next, the substrate is introduced into a reaction tube in a non-oxidizing nitrogen (N2) gas atmosphere and heat-treated at a temperature of 1170° C. for 40 minutes. Then, the crystal on the surface of the S1 substrate after ion implantation is S1
The atoms are displaced from their normal interstitial positions, but when heat treated with non-oxidizing gas, these displaced Si atoms do not react much with the non-oxidizing N2 gas. Therefore, the Si substrate is heat-treated without causing much roughness of the crystal plane on the substrate surface. By this heat treatment, the displaced Si atoms return to their normal Si interstitial positions, and B atoms are diffused to a predetermined thickness to form a B diffusion layer 18, as shown in FIG. .
その後該基板を水(H20)中を通過せしめたo2ガス
、いわゆるWetOaガス雰囲気内の反応管中に挿入し
、該基板を1000℃の温度で60分間熱処理する。こ
のようにすると第7図のように所定の厚さのBの拡散層
19と拡散層上の5i02膜20が形成される。また本
発明の方法はB以外の不純物原子を用いて半導体装置を
形成する場合においても適用可能である。Thereafter, the substrate is inserted into a reaction tube in an atmosphere of O2 gas passed through water (H20), so-called WetOa gas, and the substrate is heat-treated at a temperature of 1000° C. for 60 minutes. In this way, as shown in FIG. 7, a B diffusion layer 19 of a predetermined thickness and a 5i02 film 20 on the diffusion layer are formed. Furthermore, the method of the present invention is also applicable to the case where a semiconductor device is formed using impurity atoms other than B.
(2)発明の効果
以上述べたように、本発明の方法によればB+原子のイ
オン注入時の加速電圧が低くてすみ、したがって大規模
なイオン注入装置を必要とせず、また注入後のS1基板
表面の荒れも少々くなるので形成される半導体素子の特
性が向上する利点を生じる。(2) Effects of the Invention As described above, according to the method of the present invention, the accelerating voltage during ion implantation of B+ atoms can be low, and therefore a large-scale ion implantation device is not required, and the S1 Since the surface of the substrate becomes less rough, there is an advantage that the characteristics of the formed semiconductor element are improved.
第1図は従来の半導体装置の製造方法を説明す、71ま
ための断面図、第2図より第7図までは本発明の半導体
装置の製造方法の一実施例を示す断面図である。
図において1.11はSi基板、2、■2は埋没層、8
.13はSj−エピタキシャル層、4.14は素子間分
離領域、5.15.16.20はS:LO2膜、17は
イオン注入層、18.19は拡散層、A、Bはイオン注
入の方向を示す矢印である。
第1肉
Δ
第2図
第3図FIG. 1 is a cross-sectional view showing a conventional semiconductor device manufacturing method, and FIGS. 2 to 7 are cross-sectional views showing an embodiment of the semiconductor device manufacturing method of the present invention. In the figure, 1.11 is the Si substrate, 2, 2 is the buried layer, 8
.. 13 is the Sj-epitaxial layer, 4.14 is the element isolation region, 5.15.16.20 is the S:LO2 film, 17 is the ion implantation layer, 18.19 is the diffusion layer, A and B are the directions of ion implantation. This is an arrow indicating. 1st meat Δ Figure 2 Figure 3
Claims (1)
域で画定されたシリコン基板の半導体素子形成予定領域
内に素子形成用不純物原子をイオン注入して半導体素子
領域を形成する工程を有する半導体装置の製造に際し、
前記基板の半導体素子形成予定領域上の二酸化シリコン
膜の一部を他の領域より薄くしてから不純物原子をイオ
ン注入後、該基板を非酸化性雰囲気内で熱処理し、その
後酸化検算囲気内で熱処理する工程を含むことを特徴と
する半導体装置の製造方法。A semiconductor device having a step of forming a semiconductor element region by ion-implanting impurity atoms for element formation into a region of a silicon substrate where a silicon dioxide film is formed on the surface and where a semiconductor element is to be formed, which is defined by an inter-element isolation region. During manufacturing,
A part of the silicon dioxide film on the area where the semiconductor element is to be formed on the substrate is made thinner than other areas, and impurity atoms are ion-implanted, and then the substrate is heat-treated in a non-oxidizing atmosphere, and then in an oxidizing atmosphere. A method for manufacturing a semiconductor device, the method comprising the step of heat treatment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15629382A JPS5944867A (en) | 1982-09-07 | 1982-09-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15629382A JPS5944867A (en) | 1982-09-07 | 1982-09-07 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5944867A true JPS5944867A (en) | 1984-03-13 |
Family
ID=15624641
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15629382A Pending JPS5944867A (en) | 1982-09-07 | 1982-09-07 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5944867A (en) |
-
1982
- 1982-09-07 JP JP15629382A patent/JPS5944867A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2001291679A (en) | Method for manufacturing semiconductor device | |
JPH04715A (en) | Manufacture of semiconductor device | |
JPS5944867A (en) | Manufacture of semiconductor device | |
JPH05267338A (en) | Manufacture of semiconductor device | |
JPH097967A (en) | Fabrication method of semiconductor device | |
JPS59231863A (en) | Insulated gate semiconductor device and manufacture thereof | |
JPH05326680A (en) | Manufacture of semiconductor device | |
JPH03209816A (en) | Manufacture of semiconductor device | |
JP2722829B2 (en) | Method for manufacturing semiconductor device | |
JPS63144567A (en) | Manufacture of semiconductor device | |
JP2828264B2 (en) | Method for manufacturing semiconductor device | |
JPS62248236A (en) | Manufacture of semiconductor device | |
JP2545904B2 (en) | Semiconductor device | |
JPS6081863A (en) | Manufacture of semiconductor device | |
JPH04260331A (en) | Manufacture of semiconductor device | |
JPH0547774A (en) | Manufacture of semiconductor device | |
JPH0442938A (en) | Manufacture of semiconductor device | |
JPS61129824A (en) | Manufacture of semiconductor device | |
JPH05190848A (en) | Manufacture of mosfet | |
JPH0274042A (en) | Manufacture of mis transistor | |
JPH01246871A (en) | Manufacture of bipolar transistor | |
JPS58220461A (en) | Manufacture of semiconductor device | |
JPH0442937A (en) | Manufacture of semiconductor device | |
JPH05243249A (en) | Manufacture of bipolar transistor | |
JPH03278568A (en) | Manufacture of semiconductor device |