JPS5944865A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5944865A JPS5944865A JP15490882A JP15490882A JPS5944865A JP S5944865 A JPS5944865 A JP S5944865A JP 15490882 A JP15490882 A JP 15490882A JP 15490882 A JP15490882 A JP 15490882A JP S5944865 A JPS5944865 A JP S5944865A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- region
- semiconductor device
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 20
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 229910021339 platinum silicide Inorganic materials 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 15
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 150000004767 nitrides Chemical class 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000889 atomisation Methods 0.000 description 1
- 238000007596 consolidation process Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002716 delivery method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置及びそのＶ！遣方法に関し、！痔に
改良された不純物拡散工程と電極配線形成工程を用いた
半導体装置及びその・縛造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor device and its V! Regarding the delivery method! The present invention relates to a semiconductor device and its binding method using an improved impurity diffusion process and electrode wiring formation process.
従来、半導体装置の製造り法に於てｌｒ：Ｌ 、各不純
物拡散工程及び電極形成が別々の工程で行なわれている
。この為、マスクの使用回数が多く熱サイ゛クルがひん
繁に反復されるため半導体基板表面の汚染及び４１１傷
が生じ、半導体装１ｔ’ｌσ）信頼１！トを低下させて
いる。更に各工程間における股引マージンは高集潰化に
対する大きな障害となっている。Conventionally, in a method for manufacturing a semiconductor device, lr:L, each impurity diffusion step, and electrode formation are performed in separate steps. For this reason, the mask is used many times and thermal cycles are repeated frequently, resulting in contamination and 411 scratches on the surface of the semiconductor substrate, resulting in poor reliability of the semiconductor device. This results in a decrease in Furthermore, the cross-cutting margin between each process is a major obstacle to high consolidation.
第１図（ａ）〜（ｄ）は各々従来の半導体装置の牌造工
程全工程順に説明する為の主要工程における半導体素子
の断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor element in main steps for explaining the entire process of making tiles for a conventional semiconductor device in order.
Ｐ型シリコン基板１０表面ＶＣＮ型不純物を拡散した埋
込み層２を形成し、その上にエピタキシアル成長によ、
すＮ型半導体のコレクタ領域３を形成し半導体基板２０
としたのち、絶縁分１２＋１酸化膜４ヶ・形成する。そ
してエピタキシアル層全ｊ俊化し、酸化膜５を形成する
〔第１図（ａ）〕。A buried layer 2 in which VCN type impurities are diffused is formed on the surface of a P-type silicon substrate 10, and a buried layer 2 is formed thereon by epitaxial growth.
A collector region 3 of an N-type semiconductor is formed on the semiconductor substrate 20.
After that, four insulating 12+1 oxide films are formed. Then, the entire epitaxial layer is atomized to form an oxide film 5 [FIG. 1(a)].
次に選択エツチングにより酸化膜５に所定パターンの窓
明けを行なったのち、酸化膜５をマスクとしてＰ型不純
物（例えばボロン）を拡散しペース領域６を形成する〔
第１図（ｂ）〕。Next, after opening a window in a predetermined pattern in the oxide film 5 by selective etching, a P-type impurity (for example, boron) is diffused using the oxide film 5 as a mask to form a space region 6.
Figure 1(b)].
次に、酸化膜５を除去したのち、１りび半導体基板３４
２０表面に酸化膜５１を形成する。そして選択エツチン
グによｆｆｆｆ化膜５１に所定パターンの窓明は全行な
ったのちＮ型不純物（例えばリン）を拡散しコレクタコ
ンタクト領域７及びエミッタ領域８を形成する〔第１図
ｆｃ）） 。Next, after removing the oxide film 5, the semiconductor substrate 34 is removed.
An oxide film 51 is formed on the surface of 20. After a predetermined pattern of windows is completely etched in the FFFF film 51 by selective etching, an N-type impurity (for example, phosphorus) is diffused to form a collector contact region 7 and an emitter region 8 (FIG. 1 fc)).
次に酸化膜５１Ｕ）各不純物領域に接する所定ｆｔ６分
にソく択エツチングによりコンタクト用の窓明ケを行な
いアルミニウム（Ａ７）を蒸着したのち、選択エツチン
グによシＡ／電極９を形成する〔第１図（ｄ）〕。Next, oxide film 51U) A window for contact is formed by selective etching in a predetermined 6 ft. area in contact with each impurity region, aluminum (A7) is vapor deposited, and then A/electrode 9 is formed by selective etching. Figure 1(d)].
上述し念従来のｎ％造方法に於ては、各工程（てホトエ
ツチング操作を含み、鹿に半導体基板表面が露出し、し
かも歳化膜全マスクとして利用している為酸化工程が多
い。このことＶ」、半導体基板表面の損傷の増加や不純
物の噴化１匣中への吸い込−！れ等による半導体素子特
性の劣化原因となっている。As mentioned above, in the conventional n% manufacturing method, each step (including photo-etching operation) exposes the surface of the semiconductor substrate to the surface of the semiconductor substrate, and there are many oxidation steps because the aging film is used as a mask. This is a cause of deterioration of semiconductor device characteristics due to increased damage to the surface of the semiconductor substrate and the absorption of impurities into the ejected container.
更にマスク合す精度、窓明は精度、エツチング精度等を
考慮した設計マージンを多く必要としている。Furthermore, a large design margin is required in consideration of mask matching accuracy, window brightness accuracy, etching accuracy, etc.
第２図は第１１閃（ｄ）における１１を極部拡大図であ
る。FIG. 2 is an extremely enlarged view of 11 in the 11th flash (d).
同図において、酸化膜５１に形成されたＡ−１’ル栖９
は酸化膜の凹凸のある部分でｈｅの１１Ｐ１字が薄くな
っており断線の生ずる危険性がある。′１１？にパワー
を必要とする半導体装ＩＨに於てはこのＡ７電極の断線
が問題となる。また電極部における設ｎ１マージンは電
極間隔すの外に電極コンタクトマージンａが必要であり
、高集積化に対し大きな障害となっている。In the same figure, A-1' route 9 formed on the oxide film 51
The 11P1 character of he becomes thinner in the uneven part of the oxide film, and there is a risk of wire breakage. '11? This disconnection of the A7 electrode poses a problem in semiconductor IH devices that require power. Furthermore, the n1 margin in the electrode section requires an electrode contact margin a in addition to the electrode spacing, which is a major obstacle to higher integration.
本発明の目的は半導体基板表面の損傷を少く（−１不純
物拡散領域全精度良く形成する半導体装的の製造方法を
提ｆｉｔすることにある。An object of the present invention is to provide a manufacturing method for semiconductor devices in which damage to the surface of a semiconductor substrate is minimized (-1 impurity diffusion regions are formed with high precision throughout).
不発明の他の目的は半導体装置の製造工程、特に電極形
成工程を減らして設計マージン金少くし、果績度の向上
した半導体装置及びその製造方法全提供するＣとにある
。Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same with improved performance by reducing the manufacturing process of a semiconductor device, especially the electrode forming process, thereby reducing the design margin.
不発明の半導体装置は、基板上に形成された白金シリサ
イド′直極と、この白金シリサイド電極に接鼻独しセル
ファライン方式で形成された不純物拡散領域をこの基板
に有する構造となっている。The semiconductor device according to the invention has a structure in which a platinum silicide direct pole is formed on a substrate, and an impurity diffusion region is formed in contact with the platinum silicide electrode using a self-line method.
また、本発明の半導体装置の製造方法は、回路素子゛領
域全形成づ−る基板上にシリコン膜を形成する工程と、
前記シリコン膜の所定領域を選択的に除去し、該シリコ
ン膜が除去された領域に酸化膜を・形成する工程と、前
記基板とシリコン膜との撮触部をとおして所定領域に不
純物全導入する工程とを含むことを特徴としている。Further, the method for manufacturing a semiconductor device of the present invention includes a step of forming a silicon film on a substrate for forming the entire circuit element region;
A step of selectively removing a predetermined region of the silicon film and forming an oxide film in the region where the silicon film has been removed, and completely introducing impurities into the predetermined region through a contact portion between the substrate and the silicon film. The method is characterized in that it includes a step of.
更に、本発明の半導体装置の製造方法は、回路素子領域
を形成する基板上の所定領域に部分的に該基板と接触す
るシリコン膜全形成する工程と、前記基板と前記シリコ
ン膜とのｊ妾触部をとおして不純物を導入する工程と、
前記シリコン膜上に白金膜を形成し熱処理全行ない白金
シリサイド電極配ａｔ形成する工程とを含むこと全特徴
としている。Furthermore, the method for manufacturing a semiconductor device of the present invention includes the steps of: forming the entire silicon film partially in contact with the substrate in a predetermined region on the substrate forming the circuit element region; and forming a bond between the substrate and the silicon film. a step of introducing impurities through the contact;
The present invention is characterized in that it includes a step of forming a platinum film on the silicon film and performing heat treatment to form a platinum silicide electrode arrangement.
本発明によれば、半導体基板上に不純物拡散領域全分離
する酸化膜を設けたのち、シリコン膜上から不純物を拡
散する。この為不純物領域？’４？定する窓明精度に余
裕があｊ）また、半導体基板表面の損傷が少ない。更に
、このシリコン膜を利用し白金シリサイド電極配線をセ
ルファライン方式で形成する為、電極工程が少くなり電
極コンタクトマージンが不要で、嘔債度の向上した半導
体装置が得られる。According to the present invention, an oxide film that completely isolates impurity diffusion regions is provided on a semiconductor substrate, and then impurities are diffused from above the silicon film. Is this an impurity area? '4? There is a margin in the window brightness accuracy that is determined.) Also, there is less damage to the semiconductor substrate surface. Furthermore, since the platinum silicide electrode wiring is formed using this silicon film by the self-line method, the number of electrode steps is reduced, an electrode contact margin is not required, and a semiconductor device with improved cost efficiency can be obtained.
次に本発明について実施例を用いて詳＆（ＩＩに説明す
る。Next, the present invention will be explained in detail using examples.
第３図（ａ）〜（ｇ）は各々本発明の一実施例の製造工
程全工程順に説明する為の半導体素子の断面図である。FIGS. 3(a) to 3(g) are sectional views of a semiconductor element for explaining the entire manufacturing process in order of one embodiment of the present invention.
Ｐ型シリコン基板１の表面にＮ型不純物を拡散した埋込
みＪ＊ ２ ＊形成し、その上にエビタキシアル成長に
よりＮ型半導体層のコレクタ領域３を形成し半導体基板
２０としたのち、絶縁分離酸化膜４を形成する。次に半
導体基板２０上にポリシリコン膜２１ 、 ＋ａ化シリ
コン膜２２．ｆｆｌ化シリコン膜２３を順に形成する〔
第３図（ａ）〕。A buried J* 2 * with N-type impurities diffused is formed on the surface of a P-type silicon substrate 1, and a collector region 3 of an N-type semiconductor layer is formed thereon by epitaxial growth to form a semiconductor substrate 20, and then an insulating isolation oxide film is formed. form 4. Next, a polysilicon film 21 , a +a silicon film 22 . The ffl silicon film 23 is formed in order [
Figure 3(a)].
次に、上記ポリシリコン膜２１．酸化シリコン膜２２．
窒化シリコン膜２３に所定パターンの窓明は全行ったの
ちベース領域を形成する窓部以外全レジスト膜２４で覆
いＰ型不純物としてボロンを熱拡散し、ベース領域６を
形成する〔第３１別（ｂ）〕。Next, the polysilicon film 21. Silicon oxide film 22.
After the silicon nitride film 23 is completely etched with a predetermined pattern, the resist film 24 is applied to the entire area except for the window portion forming the base region, and boron as a P-type impurity is thermally diffused to form the base region 6 [31st section ( b)].
次に、レジスト膜２４全除去したのち所定領域に選択ｒ
俊化により酸化膜２５．２６全形成する〔第３図（Ｃ）
〕。Next, after removing the entire resist film 24, select r
The entire oxide film 25.26 is formed by atomization [Figure 3 (C)]
].
次に、窒化シリコン膜２３と酸化シリコン膜２２全除去
したのち、再び窒化シリコン膜３３Ｊｌ−形成し、この
窒化シリコン膜３３に所定パターンの窓明けを行ったの
ちポリシリコン膜２１をとおしてリンの熱拡散全行ない
高濃度のＮ型コレクタコンタクト領域７を形成する〔第
３図（ｄ）〕。Next, after completely removing the silicon nitride film 23 and the silicon oxide film 22, a silicon nitride film 33Jl- is formed again, and after opening a window in a predetermined pattern in this silicon nitride film 33, phosphorus is formed through the polysilicon film 21. Thermal diffusion is carried out to form a highly doped N-type collector contact region 7 [FIG. 3(d)].
次に、窒化シリコン膜３３を除去したのち、再び窒化シ
リコン膜４３全形成しこの窒化シリコン膜４３に所定パ
ターンの窓明は全行ない、ポリシリコン膜２１をとおし
てボロン拡散を行ないベース領域６１を形成する。更に
リンの熱拡散によシベース領域６１上にエミッタ領域８
を形成する〔第３図（ｅ）〕。Next, after removing the silicon nitride film 33, the entire silicon nitride film 43 is formed again, a predetermined pattern of windows is completely formed on the silicon nitride film 43, and boron is diffused through the polysilicon film 21 to form the base region 61. Form. Furthermore, the emitter region 8 is formed on the base region 61 by thermal diffusion of phosphorus.
[Fig. 3(e)].
次に、窒化シリコン膜４３を除去したのぢ、半導体基板
２０上に白金膜２７全形成する〔第３１゛に１（ｆ）〕
。Next, after removing the silicon nitride film 43, the entire platinum film 27 is formed on the semiconductor substrate 20 [31st 1(f)]
.
次に、熱処理全行ない白金とポリシリコン全シフタさせ
たのち不要の白金膜を除去して白金シリサイド電極配線
２８を形成する〔第３図（ｇ）〕。Next, after a complete heat treatment is performed to completely shift the platinum and polysilicon, unnecessary platinum films are removed to form platinum silicide electrode wiring 28 [FIG. 3(g)].
以上の工程により第３図（ｇ）に示す半導体装置が得ら
れる。Through the above steps, the semiconductor device shown in FIG. 3(g) is obtained.
この半導体装置の製造方法に於ては、半導体基板２０の
表面は第３ ｒｇ （ｂ）の工程に於けるベース領域６
を形成する場合を除いて常にポリシリコン膜２１に覆わ
れている為汚染が少なく、かつ不純物拡散時における損
傷が少くなる。In this method of manufacturing a semiconductor device, the surface of the semiconductor substrate 20 is formed in the base region 6 in the third rg (b) step.
Since it is always covered with the polysilicon film 21 except when it is formed, there is less contamination and less damage during impurity diffusion.
また、第３図（ｅ）で説明したように、不純物・領域全
分離する酸化膜２５．２６を半導体基板表面に直接形成
する為、不純物拡散時の窓はこの酸化膜上にあればよい
。従って特に精度の高い窓明けは必要としない。更にこ
の酸化膜２５．２６は第３図（ｆ）、 （ｇ）に於て、
セルファライン方式による白金シリサイド電極配線形成
の電極配線分６１行なっている。この酸化膜の厚さは１
５０ＯＡ程度でよく、白金シリサイド電極配線の厚さを
１００ＯＡとすれば半導体装置の表面はほぼ平担となる
。Further, as explained with reference to FIG. 3(e), since the oxide films 25 and 26 that completely isolate the impurity/region are directly formed on the surface of the semiconductor substrate, the window for impurity diffusion only needs to be on this oxide film. Therefore, it is not necessary to open the window with particularly high precision. Furthermore, the oxide films 25 and 26 are as shown in FIGS. 3(f) and (g).
There are 61 electrode wiring lines formed by platinum silicide electrode wiring using the self-line method. The thickness of this oxide film is 1
It may be about 50 OA, and if the thickness of the platinum silicide electrode wiring is 100 OA, the surface of the semiconductor device will be almost flat.
この様に形成された半導体装置は電極配線がセルファラ
イン方式で形成されている為、従来のように電極形成の
為のホトレジスト工程は不要である。また電極コンタク
トマージンａも不要である為集積度が極めて高いものと
なっている。Since the semiconductor device formed in this manner has electrode wiring formed by the self-line method, there is no need for a conventional photoresist process for forming electrodes. Further, since an electrode contact margin a is not required, the degree of integration is extremely high.
例えば、従来の方法で半導体装置全形成する場合は、電
極間隔すに４μｍ１電極コンタクトマージンａに３μ曹
］１ 必要とするためコレクタ・エミッタ間は１０μｍ
程度必要であったが、本発明によればコンタクト領域
とエミッタ領域を分離する酸化膜２５の幅は５μｍ程で
よく、従って面積比で４倍の集積度を得ることも可能で
ある。For example, when forming the entire semiconductor device using the conventional method, the electrode spacing is 4 μm, 1 electrode contact margin a is 3 μm, so the collector-emitter distance is 10 μm.
However, according to the present invention, the width of the oxide film 25 separating the contact region and the emitter region may be about 5 μm, and therefore it is possible to obtain an integration degree four times as large in terms of area ratio.
この様に半導体装置の集積度全向上させることはコレク
タ・エミッタ間の抵抗金工げ、〜また寄生容量も小さく
なりハイスピード化とローパワ化に寄与する。In this way, improving the overall degree of integration of a semiconductor device reduces the resistance between the collector and emitter, and also reduces the parasitic capacitance, contributing to higher speed and lower power.
尚、本発明は実施例に示した半導体装置及びその製造方
法に限定されるものではない。Note that the present invention is not limited to the semiconductor device and its manufacturing method shown in the examples.
以上詳細に説明したように本発明によれば、半導体基板
表面の損傷を少くシ、不純物拡散領域全精度良く形成す
ると共に、電極形成の設計マージンが少なく集積度の向
上した半導体装置及びその製造方法が得られるのでその
効果は太きい。As described in detail above, according to the present invention, a semiconductor device and a method for manufacturing the same can reduce damage to the surface of a semiconductor substrate, form impurity diffusion regions with high precision, and have a small design margin for electrode formation and an improved degree of integration. The effect is significant because it can be obtained.
第１図（ａ）〜（ｄ）は各々従来の半導体装置の製造工
程全工程順に説明する為の半導体素子の断面図、第２図
は第１図（ｄ）Ｙｃおける電極部拡大図、第３図（ａ）
〜（ｇ）は各々本発明の一実施例の製造工程を工程順に
説明する為の半導体素子の断面図である。
１・・・・・・シリコン基板、２・・・・・・埋込み層
、３・・・・・・コレクタ″ｌ！ｆｆｌ域、４・・・・
・絶縁分離酸化膜、５．５１・・・・酸化膜、６．６１
・・・・・・ベース領域、７・・・・・・コレクタコン
タクト領域、８・・・・・エミッタ領域、９・・・・・
・Ａｌ電極、２０・・・・・半導体基板、２１・・・・
・・ポリシリコン膜、２２・・・・・酸化シリコン膜、
２３゜３３．４３・・・・・・窒化シリコン［，２４・
・・・・・レジスト膜、２５．２６・・・・・・酸化膜
、２７・・・・・・白金膜、２８・・・・・・白金シリ
サイド電極配線。
第Ｚ 図1(a) to 1(d) are cross-sectional views of a semiconductor element for explaining the entire manufacturing process of a conventional semiconductor device, respectively. FIG. 2 is an enlarged view of the electrode part in FIG. 1(d) Yc, and FIG. Figure 3 (a)
-(g) are cross-sectional views of a semiconductor element for explaining the manufacturing process of an embodiment of the present invention in order of process. 1...Silicon substrate, 2...Buried layer, 3...Collector "l!ffl region, 4...
・Insulating isolation oxide film, 5.51...Oxide film, 6.61
... Base region, 7 ... Collector contact region, 8 ... Emitter region, 9 ...
・Al electrode, 20...semiconductor substrate, 21...
...Polysilicon film, 22...Silicon oxide film,
23゜33.43...Silicon nitride [,24・
...Resist film, 25.26 ... Oxide film, 27 ... Platinum film, 28 ... Platinum silicide electrode wiring. Figure Z
Claims (3)
成する工程と、前記シリコン膜の所定領域全選択的に除
去し、該シリコン膜が除去された領域に酸化膜を形成す
る工程と、前記基板とシリコン膜との接触部金と」夕し
て所定領域に不純物を導入する工程と金含むことを特徴
とする半導体装１汽の製造方法。(1) A step of forming a silicon film on a substrate on which a circuit element is to be completely mounted, and a step of selectively removing a predetermined region of the silicon film and forming an oxide film in the region from which the silicon film has been removed. . A method of manufacturing a semiconductor device, comprising: a step of introducing impurities into a predetermined region of the contact portion between the substrate and the silicon film; and a step of introducing gold into a predetermined region.
発的に該基板と接触１−るシリコン膜全形成する工程と
、前記基板と前記シリコン膜との接触部をと外して不純
物を導入する工程と、前記シリコン１り上に白金膜全形
成し熱処理を行ない白金シリサイド電極配線を形成する
工程とを含むことを特徴とする半導体装置の製造方法。(2) A step of forming the entire silicon film elastically in contact with the substrate in a predetermined region of the substrate forming the circuit element region, and removing the contact portion between the substrate and the silicon film to remove impurities. 1. A method for manufacturing a semiconductor device, comprising the steps of: introducing a platinum film over the silicon substrate 1, and performing heat treatment to form a platinum silicide electrode wiring.
該白金シリサイド電４ｖ配腺ニ１見り１（シセルファラ
イン方式で形成された不純物拡散領域を該基板に有する
ことを特徴とする半導体装１＾。(3) platinum silicide electrode wiring formed on the substrate;
A semiconductor device 1 characterized in that the substrate has an impurity diffusion region formed by the platinum silicide line system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15490882A JPS5944865A (en) | 1982-09-06 | 1982-09-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15490882A JPS5944865A (en) | 1982-09-06 | 1982-09-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5944865A true JPS5944865A (en) | 1984-03-13 |
Family
ID=15594585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15490882A Pending JPS5944865A (en) | 1982-09-06 | 1982-09-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5944865A (en) |
-
1982
- 1982-09-06 JP JP15490882A patent/JPS5944865A/en active Pending
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