JPS5944783B2 - Method for manufacturing complementary MOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a complementary MOS semiconductor device that improves the ion implantation process for forming source, drain, and wiring layers.

As is well known, complementary MOS semiconductor device (hereinafter simply CMO)
(abbreviated as S) is usually made by fabricating a semiconductor substrate in which a p-type well is selectively formed on an n-type silicon substrate, and a p-well is formed in this n-type region.
A channel MOS transistor is formed in a p-type region, and an n-channel MOS transistor is formed in a p-type region.

Such CMOS has features such as consuming power only during transient times, being less susceptible to substrate effects, having a high noise margin, and operating over a wide power supply voltage range. by the way,
Conventional CMOS is manufactured by the following method.

First, a p-well region 2 is selectively formed on an n-type silicon substrate 1 to produce a semiconductor substrate 3, and a thermal oxidation treatment is performed to grow a silicon oxide film 4, a portion of which becomes a gate oxide film. Then, a field oxide film 5 separating each element region is grown using a selective oxidation technique. Subsequently, a gate electrode 6 made of polycrystalline silicon is formed on the silicon oxide film 4 of the n-type silicon substrate 1 and the p-well region 2 as each active region.
, 62 (as shown in FIG. 1a). Subsequently, arsenic ions as an n-type impurity are implanted. At this time, Figure 1b
Arsenic is ionized through the p-well region 2 and the silicon oxide film 4 of the n-type silicon substrate 1 as shown in FIG. Since a high p-type impurity is implanted, there is no problem even if arsenic is implanted into both regions. After covering the C and p-well regions 2 with a resist film 7, boron ions as a p-type impurity are implanted into the n-type silicon substrate 1vC through the silicon oxide film 4 (as shown in FIG. 1c). After that, after removing the resist film 6,
Heat treatment is performed for approximately 0 minutes to activate and diffuse each ion implantation layer in the p-well region 2 and the surface layer of the n-type silicon substrate 1.
A p+ type source 81, a drain 9,
, and a p+ type wiring layer 101 in the p-well region 2.
+ type source 82, drain 92 and n+ type wiring layer 1
02 to manufacture CMOS (as shown in FIG. 1d)
. However, in the conventional method described above, since boron has a smaller mass and a smaller stop power than arsenic, even if ions are implanted at the same acceleration voltage, the peak value is deep.

Therefore, the source 82, drain 92, and wiring layer 102 on the n-channel side formed in the p-well region 2 are 0.0.
The depth is approximately 2 μm, whereas the source 81, drain 91, and wiring layer 101 on the p channel side have a depth of 0.6 μm.
There is a difference in v, such as μm. As a result, p channel M
As a result of lateral diffusion of the OS transistor, the effective channel length decreases, resulting in short channel effects and the like. Measures to improve these problems include (1) reducing the ion implantation amount, (2) lowering the acceleration voltage, and (3) increasing the oxide film thickness of the source and drain when boron ions are implanted to form the source and drain on the p-channel side. Possible methods include making it thicker.

However, in method 1, the resistance of the p+ wiring layer formed at the same time becomes high, which becomes an obstacle to high-speed operation. In method 2, when the acceleration voltage is lowered, the ion implantation time is significantly extended, and there is a limit to the low acceleration voltage.

Furthermore, in method 3, when increasing the thickness of the oxide film on the source and drain, it is very difficult to selectively oxidize only the source and drain on the p-channel side, and the entire surface is forced to be oxidized. Naturally, the oxide films on the side sources and drains are not thick either, so there is an inconvenience that the accelerating voltage for arsenic ion implantation must be increased. That is,
When the accelerating voltage of arsenic ions reaches 100 ke degrees, arsenic escapes into the gate oxide film and gate region under the gate electrode, resulting in a short channel problem due to a decrease in channel length. In order to overcome this drawback, the inventor of the present invention has conducted extensive research to overcome the above-mentioned drawbacks, and has found that by selectively implanting oxygen ions into the n-type active region, that is, the portion where the source and drain are to be formed on the p-channel side, and performing heat treatment. By forming a thicker oxide film than other regions, p
When selectively implanting p-type impurities, the amount of p-type impurities implanted into the source, drain, and wiring layer in the same region can be controlled by the difference in the thickness of the oxide film, and less p-type impurity is implanted into the areas where the source and drain are planned to be formed. It has been found that a larger amount of p-type impurity can be implanted into the portion where the wiring layer is to be formed.

As a result, by selectively ion-implanting n-type impurities into the p-type active region and then performing high-temperature heat treatment, the depth of the source and drain on the p-channel side can be made shallow, and at the same time, the depth of the source and drain on the p+ wiring layer can be reduced. We have discovered a method for manufacturing CMOS that can increase the concentration of MOS transistors, lower the resistance, and set the channel length to the same level as that of an n-channel MOS transistor. That is, the present invention provides a complementary structure in which a gate electrode, a source, a drain, and a wiring layer of the opposite conductivity type to the active region are provided on a semiconductor substrate having p-type and n-type conductivity active regions, respectively. In manufacturing a MOS semiconductor device, after forming an oxide film on the main surface of a semiconductor substrate, a step of forming a gate electrode on a portion of the oxide film of each active region, a source of the n-type active region of the substrate, After selectively ion-implanting oxygen into the region where the drain is to be formed, heat treatment is performed to increase the thickness of the oxide film in the region where the source and drain are to be formed, and p-type impurity is added only to the n-type active region. selectively ion-implanting n-type impurities into the p-type active region of the semiconductor substrate through the oxide film, and after ion-implanting each impurity, The method is characterized by comprising a step of applying heat treatment to each active region to form a source, a drain, and a wiring layer of a conductivity type opposite to that of the active region. Examples of gate electrode materials used in the present invention include polycrystalline silicon, non-SB doped polycrystalline silicon, and metal silicides such as molybdenum silicide, tungsten silicide, tantalum silicide, and platinum silicide.

In the present invention, the selective oxygen ion implantation and heat treatment into the source and drain formation areas of the n-type active region (for example, n-type silicon substrate) are performed in comparison to the oxide film on the wiring layer formation areas in the same area. The film thickness of the oxide film on the portion where the drain is to be formed is adjusted, and the difference in the film thickness of the oxide film is used to change the degree of impurity implantation during subsequent ion implantation of p-type impurities.

Such ion implantation conditions and heat treatment conditions may be appropriately selected depending on the depth of the source and drain on the p-channel side to be formed, the resistance of the wiring layer, etc. However, the present invention has the advantage that the depths of the source and drain and the resistance of the wiring layer can be easily controlled by changing the ion implantation conditions and heat treatment conditions. Examples of p-type impurities in the present invention include boron, antimony, etc., and examples of n-type impurities include arsenic, phosphorus, etc.

Next, embodiments of the present invention will be described with reference to FIGS. 2a-d.

Example (1) First, a p-well region 102 is selectively formed on an n-type silicon substrate 101 to create a semiconductor substrate 103, and then a thermal oxidation treatment is performed to form a gate insulating portion on the surface of the substrate 103. A SiO2 film 104 having a thickness of 100 mm was grown to form a film.

Subsequently, each active region (n-type silicon substrate 101, p-well region 102) is separated by selective oxidation technology, and a field oxide film 105 is grown to separate the source, drain, and wiring layer in each active region. , gate electrodes 1061 and 1062 made of polycrystalline silicon were formed on the n-type silicon substrate 101 and the SiO2 film 104 in the channel region of the p-well region 102. Subsequently, the p-well region 1 of the semiconductor substrate 103 is formed by photolithography.
A resist pattern 107 is formed to cover the wiring layer formation portion of the n-type silicon substrate 101 and the n-type silicon substrate 101.
7 as a mask, output oxygen at 90 keV, dose amount 1×
1016/CT! The source on the n channel side under the condition of l,
After ion implantation into the region where the drain was to be formed, heat treatment was performed. At this time, as shown in FIG. 2a, a thick SiO2 film 108 with a thickness of 1,500 mm is formed in the portions of the n-type silicon substrate where the source and drain are to be formed, and the SiO2 film 108 is formed in the portions of the same substrate 101 where the wiring layers are to be formed. The film thickness has been increased compared to .

(1;) Next, the resist pattern 107 is removed and a resist pattern 109 covering the p-well region 102 is formed again by photolithography, and then boron is applied to the exposed n-type silicon substrate 101 using the pattern 109 as a mask. 40keV, dose 5×1015/c-! Ion implantation was performed under IL conditions.

At this time, as shown in FIG.
Since the SiO2 film 104 is thicker than the SiO2 film 104 in the area where the layer is to be formed, shallow and low concentration boron implanted layers 110, 110 are formed in the area where the source and drain are to be formed, and deep and high concentration boron implanted layers are formed in the area where the wiring layer is to be formed. A concentrated boron ion implantation layer 111 was formed. (1i1) Next, the resist pattern 109 is removed and arsenic is applied to the entire surface at a dose of 50 keV1 at a dose of 5×1
015/CT! Ion implantation was performed under conditions of 1.

At this time, as shown in FIG. 2c, arsenic ion-implanted layers 112, 112, 1 with the same depth and the same concentration are formed in the source and drain portions of the p-well region 102 and the wiring layer formation portions, respectively.
13 were formed. At this time, the n-type silicon substrate 10
Arsenic is also ion-implanted into No. 1, but since the pre-formed boron ion-implanted layers 110, 110, and 111 have a higher diffusion coefficient than arsenic, what is needed to form the source, drain, and wiring layers on the p-channel side? It doesn't affect anything. (!ψ Next, the semiconductor substrate 103 after each impurity ion implantation is
Heat treatment was performed at 0'C for about 30 to 40 minutes. At this time, the second
As shown in FIG. d, the boron ion implantation layers 110, 110, 111 of the n-type silicon substrate 101 are electrically activated.
and diffused into p+ type source 1141 and drain 115
The arsenic ion-implanted layers 112, 112, 113 in the p- well region 102 are electrically activated and diffused to form an n+ type source 1142, drain 1152, and n+ interconnect layer 1162. Formed CMOS
was manufactured. Therefore, in this embodiment, an n-type silicon substrate 1 on which a p-channel MOS transistor is formed.
The SiO2 film 108, which is thicker than the wiring layer formation area of the same substrate 101, can be selectively formed in the source and drain formation areas of the substrate 101, making it possible to change the degree of boron ion implantation.

Therefore, the source 114 on the p-channel transistor side
, drain 115, can be controlled to a shallow depth (0.2 μm) similar to that of the source 1142 and drain 1152 on the n-channel transistor side, and the p+ wiring layer 1161 of the same p-channel transistor can be deep with high concentration. . As a result, it was possible to easily obtain a CMOS in which the channel length of the p-channel transistor was comparable to that of the n-channel transistor, the p+ interconnection layer 1161 had a low resistance of 20 to 30 Ω/Cd, and was capable of high-speed operation. As described in detail above, according to the present invention, a p-channel MOS transistor that suppresses the short channel consisting of a shallow source and drain without adversely affecting the formation of an n-channel MOS transistor and without significantly changing the process of the conventional method. In addition to forming a channel MOS transistor, it is also possible to achieve high concentration and low resistance in the p+ wiring layer on the side of the transistor, resulting in high speed and
This method has remarkable effects such as being able to manufacture high-density and highly reliable complementary MOS semiconductor devices.

[Brief explanation of the drawing]

1A to 1D are cross-sectional views showing the CMOS manufacturing process according to the conventional method, and FIGS.
FIG. 3 is a cross-sectional view showing the manufacturing process of S. 101... N-type silicon substrate, 102... P-well region, 103... Semiconductor base, 104, 108...
・SlO2 film, 105...Field oxide film, 106
1,1062...gate electrode, 1141...p+ type source, 1151...p+ type drain, 116,...
・p+ wiring layer, 1142...n+ type source, 1152
...n+ type drain, 1162...n+ wiring layer.

Claims (1)

[Claims] 1 Complementary MOS semiconductor device having a structure in which a gate electrode and a source, drain, and interconnection layer of the opposite conductivity type to the active region are respectively provided in each active region of a semiconductor substrate having active regions of p-type and n-type conductivity. In manufacturing, after forming an oxide film on the main surface of the semiconductor substrate, there is a step of forming a gate electrode on a part of the oxide film of each active region, and a planned source and drain formation of the n-type active region of the substrate. After selectively ion-implanting oxygen into the region, heat treatment is performed to increase the thickness of the oxide film in the region where the source and drain are to be formed, and p-type impurity is added only to the n-type active region of the semiconductor substrate. A step of selectively implanting ions through oxide films having different film thicknesses, a step of selectively implanting ions of an n-type impurity into the p-type active region of the semiconductor substrate through the oxide film, and a heat treatment after ion implantation of each impurity. 1. A method of manufacturing a complementary MOS semiconductor device, comprising the steps of: forming a source, a drain, and a wiring layer of a conductivity type opposite to that of the active region in each active region.