JPS5944695B2 - Information identification device with Mitsuming clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides information (consisting of a clock signal train and a data signal train) recorded in frequency modulation on the magnetic surface of a magnetic recording medium such as a magnetic recording disk of a magnetic disk drive, in which a clock signal is transmitted at multiple locations. The present invention relates to an information identification device for identifying a missing clock from information having the above-mentioned property transferred in a loop transmission device or the like (information having the property of being missing) and information having the above-mentioned property transferred in a loop transmission device or the like.

Generally, in order to efficiently store information in a magnetic disk device, a magnetic recording divided sector method is used in which variable length recording is performed, and each track contains a synchronization pattern, track address, sector address, sector length information, flag information, etc. It consists of an identification field section consisting of an identifier field section, a data field section for storing information, and a gap section provided to absorb rotation period deviation, head switching time, etc.

In such a configuration, in order to prevent an erroneous write or read operation even if a track other than the requested track is sought due to a head positioning error, and to confirm the information recorded in each sector, It is determined whether the identification field part requests reading of a predetermined synchronization pattern recorded on the track.

However, unless a special pattern is provided that occurs only before the synchronization pattern in the identifier field, the information in the data field and the identifier field may overlap depending on the timing when reading the information. If the synchronization pattern is incorrectly matched and information is read or written from the middle of the data field, causing serious trouble in the operation of the central processing unit, or if the above-mentioned format configured on the magnetic recording disk is There is a risk that it may be destroyed, making it impossible to read important information. Therefore, in order to prevent this, a missing clock is provided in front of the identification field section, and a missing clock is installed in front of the identification field section, and uses a complicated and expensive circuit such as a PLL (PhaseLOckLOOp) to store information consisting of a clock signal train and a data signal train. It is a well-known fact that the presence or absence of a missing clock was detected by separating it into a data section and a clock section. This invention was made to enable easy and inexpensive detection of a missing clock from information consisting of a clock signal train and a data signal train in which a missing clock is provided. An example will be explained based on the drawings, taking a magnetic disk separately.

1 and 2, reference numeral 1 denotes a clock signal train C1 to Cl5 which is magnetically frequency modulated on the magnetic surface of a magnetic recording medium (for example, a magnetic recording disk) and a data signal train having a phase different from this clock signal train. Magnetic recording information (hereinafter abbreviated as recording information) consisting of D1 to D, O and having no clock signal at a prescribed position called a missing clock.

), 2 are enable signals that control the timing from which the recording information 1 is introduced. 3 is an AND gate circuit which receives the recording information 1 and enable signal 2 as input; 4 is the output of the AND gate circuit 3, that is, the enabled clock signal train and data signal train; 5 is the output 4 of the AND gate circuit 3; The input window width circuit triggers the window width circuit output signal 6 (High level or LOW level) occurs for a specified time and the window width circuit output signal 6 occurs for a specified period of time, the clock signal C3~
If Cl5 or the data signals D1 to DlO do not arrive, the window width circuit output signal 6 disappears.

In other words, the High level or L level held until now
Ow level is reversed. Conversely, when the clock signals C3 to Cl5 or the data signals D1 to DlO arrive again while the window width circuit output signal 6 has been occurring for a specified period of time, the window width circuit output signal 6 is continuously generated for a specified period of time. occurs. That is, it is a retriggerable one-shot circuit. 7 is a D flip. Flop circuit (hereinafter referred to as DF)
It is abbreviated as F circuit.

), and in this DFF circuit, the output signal 6 of the window width circuit 5 is input to the input terminal D, and the AND gate circuit 3 is input to the input terminal T.
The output signal 4 of is input. If a signal had been generated at the input terminal D immediately before the signal was applied to the input terminal T, a 0ne's signal 8 of the opposite level (LOW level or High level) is generated at the output terminal C.
Further, this DFF circuit 7 is connected to the delay circuit output 1 of the delay circuit 9.
It has a set terminal R connected to 0, and when a falling signal (LOW level) is applied to this, the 0ne's signal 8 is forcibly extinguished.

9 is a delay circuit, and the output terminal C of the DFF circuit 7, that is, 0
The ne's signal is input, and a delayed 0ne's signal is generated at the delay circuit output 10 after a predetermined time has elapsed since the 0ne's signal 8 was generated.

From the above, if n clock signals or data signals in the recorded information 1 are generated between the extinction of the window width circuit output signal 3 and the next extinction, the output terminal C of the DFF circuit 5 will be 0.
It is characterized in that n-1 ne5s signals 8 are generated.

Reference numeral 11 denotes an odd number detection circuit, which inputs the output terminal C of the DFF circuit 7, that is, the 0ne's signal 8, and its output, the odd number detection circuit output 10, changes the state held every time the 0ne/s signal 8 is applied. The inversion state is repeated.

The odd number detection circuit 11 also has a set terminal R which receives the window width circuit output signal 6 of the window width circuit 5 as an input, and when a falling signal (LOW level) is applied to this, the odd number detection circuit output 12 is forcibly set to the initial value. Note that this odd number detection circuit 11 receives a 0ne/s signal 8.
0ne's signal 8 produced at the delay circuit output 10 instead of '
It is clear that 0ne's signal 8' or delayed 0ne's signal 8' can be input to the odd number detection circuit 11.
It is obvious that the 's signal 8' may be replaced with a counter for counting. Reference numeral 13 denotes a missing clock detection circuit, to which the odd number detection circuit output 12 of the odd number detection circuit 11 is applied to the input terminal J, and the window width circuit output signal 12 of the window width circuit 5 is applied to the input terminal T.

The output of the missing clock detection circuit 13 is
If a signal is present at the input terminal J immediately before the signal is applied to the input terminal T, a missing clock detection signal 14 (high level or LOW level) is generated. In the above configuration, the object of the present invention is to determine whether or not a signal is applied to the input terminal J of the missing clock detection circuit 3 immediately before the signal is applied to the input terminal T. In other words, in FIG. 2, the 0ne's signal is generated in an interval A where there is no missing clock (from the extinction of the window width circuit output signal 6 sandwiched between the clock signals Cl and C2 in the recorded information 1 to the next extinction). 8 occurs six even numbers, and the odd number detection circuit output 12 is in the initial state (in this case L
Although this is an Ow level, it goes without saying that it can be realized using the reverse High level or a counter.
) is back. This shows that an even number of 0ne's signals 8 were generated. On the other hand, in FIG. 2, the beginning and end of the section with the missing clock (from the disappearance of the window width circuit output signal 6 sandwiched between the clock signals C8 to C9 and the data signals D7 to D8 in the recorded information 1 to the next disappearance) The clock signal and data signal in recorded information 1 are C9.
~D6 and D8~Cl3 form an even number of groups, so if the sum of the clock signal and data signal is n, then n-1.
DF having the characteristic of generating 0ne's signals 8
It can be seen that an odd number of 0ne/s signals 8 are generated at the output terminal C of the F circuit 7.

From this, the missing signal can be detected by checking the odd number detection circuit output 12, which expresses whether an even number or an odd number of 0ne's signals 8 have been generated at the timing when the window width circuit output signal 6 disappears.・The presence or absence of a clock can be detected. Incidentally, the High level and LOW level shown in FIG. 2 and the above description, and the timing 1 are shown, but the present invention is not limited thereto.

Since the present invention is constructed as described above, it has the advantage that the missing clock present in the recorded information 1 can be identified accurately and easily. Although a magnetic disk storage device has been described above, the present invention is not limited to this, and may be used in magnetic recording devices, loop transmission devices, and other frequency modulation information identification devices that use similar frequency modulation methods.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an information identification device for explaining an embodiment of the present invention, and FIG. 2 is a timing diagram of each part of FIG. , 3 is an AND gate circuit, 4 is an output of the AND gate circuit, 5 is a window width circuit, 6 is a window width circuit output signal, 7 is a DFF circuit, 8 is a 0ne's signal, 9 is a delay circuit, 10
is the delay circuit output, 11 is the odd number detection circuit, 12 is the odd number detection circuit output, 13 is the missing clock detection circuit, 14
is the missing clock detection signal, A is the area outside the missing clock, and C is the missing clock area.

Claims (1)

[Claims] 1. In an information identification device configured to detect a missing clock signal from information consisting of a clock signal train and a data signal train having a phase different from this clock signal train,
A window width circuit that inputs the above information and maintains the output level state while the clock signal and data signal are present alternately, and inputs the output of the window width circuit and the clock signal and data signal. a signal generating circuit that generates a pulse signal corresponding to the number of pulses of the clock signal and the data signal that occur during a period in which the output of the window width circuit maintains a predetermined state; an identification circuit that generates an output capable of identifying whether the number of pulse signals generated from the signal generation circuit is odd or even within a period in which the state is maintained; an output state of the window width circuit; and an output state of the identification circuit. and a detection circuit for detecting the missing clock signal according to the information.