JPS5462809A - Magnetic recording information identifying apparatus - Google Patents

Magnetic recording information identifying apparatus

Info

Publication number
JPS5462809A
JPS5462809A JP12932577A JP12932577A JPS5462809A JP S5462809 A JPS5462809 A JP S5462809A JP 12932577 A JP12932577 A JP 12932577A JP 12932577 A JP12932577 A JP 12932577A JP S5462809 A JPS5462809 A JP S5462809A
Authority
JP
Japan
Prior art keywords
signal
circuit
signals
terminal
recording information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12932577A
Other languages
Japanese (ja)
Other versions
JPS5944695B2 (en
Inventor
Nobuyuki Asahi
Takahito Kyo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12932577A priority Critical patent/JPS5944695B2/en
Publication of JPS5462809A publication Critical patent/JPS5462809A/en
Publication of JPS5944695B2 publication Critical patent/JPS5944695B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE: To enable the missing clock in recording information to be accurately and readily identified by detecting the missing clock signal from the output states of a window width circuit and a counter circuit.
CONSTITUTION: Output signals 6, 4 of a window width circuit 5 and an AND 3 are inputted respectively to the terminals D, T of a DFF circuit 7. To the terminal C is generated the One's signal 8 of an opposite level when the signal is produced in the terminal D at the immediate before the time when the signal is applied to the terminal T. However, when a fall signal is applied to the reset terminal R connecting to the output 10 of a delay circuit 9, the signal 8 annihilates. The circuit 9 outputs a delayed one's signal 8' when a specified time elapses after the signal 8 was inputted. Therefore, when (n) clock signals or data signals of recording information 1 are produced from the annihilation of the signal 6 until the next annihilation, the signals 9 are obtained in n-1 number. Then, if the number of production of the signals 9 is checked at the timings at which the signal 6 annihilates by checking the outputs of an odd number detection circuit 11, then the presence or not of any missing clock may be accurately and readily detected.
COPYRIGHT: (C)1979,JPO&Japio
JP12932577A 1977-10-28 1977-10-28 Information identification device with Mitsuming clock Expired JPS5944695B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12932577A JPS5944695B2 (en) 1977-10-28 1977-10-28 Information identification device with Mitsuming clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12932577A JPS5944695B2 (en) 1977-10-28 1977-10-28 Information identification device with Mitsuming clock

Publications (2)

Publication Number Publication Date
JPS5462809A true JPS5462809A (en) 1979-05-21
JPS5944695B2 JPS5944695B2 (en) 1984-10-31

Family

ID=15006787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12932577A Expired JPS5944695B2 (en) 1977-10-28 1977-10-28 Information identification device with Mitsuming clock

Country Status (1)

Country Link
JP (1) JPS5944695B2 (en)

Also Published As

Publication number Publication date
JPS5944695B2 (en) 1984-10-31

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