JPS5577044A - Data signal detection system - Google Patents

Data signal detection system

Info

Publication number
JPS5577044A
JPS5577044A JP15182078A JP15182078A JPS5577044A JP S5577044 A JPS5577044 A JP S5577044A JP 15182078 A JP15182078 A JP 15182078A JP 15182078 A JP15182078 A JP 15182078A JP S5577044 A JPS5577044 A JP S5577044A
Authority
JP
Japan
Prior art keywords
signal
signals
automatic stop
control signal
pulses synchronized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15182078A
Other languages
Japanese (ja)
Inventor
Shigeru Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP15182078A priority Critical patent/JPS5577044A/en
Publication of JPS5577044A publication Critical patent/JPS5577044A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrically Operated Instructional Devices (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE: To detect data signals with a high reliability by using two sets of signals different in frequency to generate an automatic stop signal and a control signal.
CONSTITUTION: At a reproducing time of recorded sound signal S1, automatic stop signal S2 formed by a prescribed number of signals f1 and f2 of alternate frequencies F1 and F2, and control signal S3 where signal f2 exists between signals f1 of a prescribed repeat period, detection circuits 7 and 8 generate pulses synchronized with signals f1 and f2. When pulses synchronized with signal f1 of signal S2 from circuit 7 are counted by counter 25 of automatic stop signal detection circuit 9 to reach a set value, an automatic stop signal is generated. Simultaneously, AND gates 29 and 30 are opened by this signal, and pulses synchronized with signal f1 of signal S3 become clock pulses, and a control signal dependent upon pulses synchronized with signal f2 is generated from shift register 31, and the automatic stop signal and the control signal are outputted when signals f1 and f2 exist together. Consequently, generation of the automatic stop signal and the control signal for erroneous data detection dependent upon components of signal f1 or signal f2 in signal S1 is prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP15182078A 1978-12-07 1978-12-07 Data signal detection system Pending JPS5577044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15182078A JPS5577044A (en) 1978-12-07 1978-12-07 Data signal detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15182078A JPS5577044A (en) 1978-12-07 1978-12-07 Data signal detection system

Publications (1)

Publication Number Publication Date
JPS5577044A true JPS5577044A (en) 1980-06-10

Family

ID=15527020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15182078A Pending JPS5577044A (en) 1978-12-07 1978-12-07 Data signal detection system

Country Status (1)

Country Link
JP (1) JPS5577044A (en)

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