JPS5941829A - Forming method of ohmic contact with compound semiconductor - Google Patents

Forming method of ohmic contact with compound semiconductor

Info

Publication number
JPS5941829A
JPS5941829A JP15206382A JP15206382A JPS5941829A JP S5941829 A JPS5941829 A JP S5941829A JP 15206382 A JP15206382 A JP 15206382A JP 15206382 A JP15206382 A JP 15206382A JP S5941829 A JPS5941829 A JP S5941829A
Authority
JP
Japan
Prior art keywords
layer
compound semiconductor
mask
oxide film
ohmic contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15206382A
Other languages
Japanese (ja)
Inventor
Yukio Kaneko
幸雄 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15206382A priority Critical patent/JPS5941829A/en
Publication of JPS5941829A publication Critical patent/JPS5941829A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To execute the formation of a high-concentration layer, the formation of an ohmic electrode and relative positioning by a simple process by forming a hole in which the opening section of a first layer is than that of a second layer, etching the compound semiconductor while using the thin-film of the first layer as a mask and vapor-growing an element. CONSTITUTION:An electrode pattern is formed by a photo-resist 14, a nitride film 13 and an oxide film 12 are etched through dry etching using CF4 gas while using the pattern as a mask, and the hole in which the opening section of the oxide film 12 of the first layer is wider than that of the nitride film of the second layer on the oxide film is formed. Gallium arsenide 11 is etched by using a mixed liquid of sulfuric acid, hydrogen peroxide and water while using the oxide film 12 as a mask and entered in a thermal decomposition system growth oven employing arsine-organic gallium-hydrogen, and a gallium aresenide crystal 15 in high concentration is grown selectively. When metals 16, 17 forming the ohmic contact are evaporated while using the nitride film 13 as a mask, step broken sections 18, 18' can be formed, the metals are alloyed through heat treatment, and the excellent ohmic contact is obtained.

Description

【発明の詳細な説明】 マイクロ波の見通し自通信、衛星通信など通信システム
が発展しより多くの情報を送ることが望まれるようにな
るとともに1それに使用される素子としてより高周波で
動作することが望まれるようになってきた。半導体素子
の素材は、従来シリコンが主流であったが、高周波素子
用の素材として現在化合物半導体が、その電子移動度の
大きさから着目されている。その中では、砒化ガリウム
に関する研究が特に進んでおり、砒化ガリウムの電界効
果型トランジスターは既に実用レベルに到達している。
[Detailed Description of the Invention] With the development of communication systems such as microwave line-of-sight communication and satellite communication, it has become desirable to send more information. It has become desired. Conventionally, silicon has been the mainstream material for semiconductor devices, but compound semiconductors are currently attracting attention as materials for high-frequency devices because of their high electron mobility. Among these, research on gallium arsenide is particularly advanced, and field-effect transistors using gallium arsenide have already reached a practical level.

電界効果型トランジスターにおいて、良好な性能を得る
ために重要なことはゲート長を短くすることと、ソース
抵抗を低くすることである。
In field effect transistors, it is important to shorten the gate length and lower the source resistance in order to obtain good performance.

ソース抵抗を低くする方法として、従来から動作層より
1桁以上高い濃度を有する結晶をオーミック接触を形成
する部分に埋込むという方法が知られている。しかしな
がら化合物半導体の場合その不純物濃度を2x 10t
ll cML−3以上に高くすることは難かしく、金属
に比べ比抵抗を十分低くすることができないのでソース
抵抗を低くするためには、高#度な結晶をゲートに近づ
けるだけでなく、オーミックの電極金属もゲートに近づ
ける必要がある。−刀先学的な露光機によるフォトレジ
ストパターンの相対的な位置合わせの精度は±0.5μ
m程度である。従って選択成長による高濃度層形成後、
新ためてフォトレジストによリオーミック電極のパター
ンを形成する場合で両者のパターンの位置が逆転しない
よう圧するには、第り図(a)(b)に示すようにオー
ミック成極のパターン2tj:、高温[14のパターン
1に比べて少くとも0.5μm以上は、しジぞいている
必要がある。
As a method of lowering the source resistance, a method is conventionally known in which a crystal having a concentration one order of magnitude higher than that of the active layer is buried in a portion where an ohmic contact is to be formed. However, in the case of compound semiconductors, the impurity concentration is 2x 10t
It is difficult to increase the resistivity higher than cML-3, and it is not possible to make the resistivity sufficiently low compared to metals. Therefore, in order to lower the source resistance, it is necessary to not only bring the high-density crystal close to the gate, but also to use ohmic The electrode metal also needs to be close to the gate. - The accuracy of relative alignment of photoresist patterns using an exposure machine is ±0.5μ
It is about m. Therefore, after forming a high concentration layer by selective growth,
When forming a new ohmic electrode pattern using photoresist, in order to apply pressure so that the positions of both patterns do not reverse, ohmic polarization pattern 2tj: It is necessary that the pattern is at least 0.5 μm or more smaller than the pattern 1 of the high temperature [14].

第1図(a)は高濃度I@パターンと゛成極パターンの
関係を示す平面図、第1図(b)はその断面図である。
FIG. 1(a) is a plan view showing the relationship between the high concentration I@ pattern and the polarization pattern, and FIG. 1(b) is a cross-sectional view thereof.

このことは、素子の特性面で不利であるばかりでなく、
難かしい位置合わせを必要とすることから製造歩留9を
低くするという欠点を有していた。
This is not only disadvantageous in terms of device characteristics, but also
Since difficult positioning is required, this method has the disadvantage of lowering the manufacturing yield.

本発明は以上の問題点に対処してなされたもので簡易な
プロセスにより高a度層の形成とオーミック成極や形成
を行いそれと同時に相対的な位置合せを好適に行いうる
化合物半導体へのオーミック接触の形成方法を提供する
にある。
The present invention has been made in response to the above problems, and it is possible to form a high a degree layer and ohmic polarization through a simple process, and at the same time, to perform ohmic polarization and formation of a compound semiconductor with suitable relative alignment. To provide a contact formation method.

本発明の要旨は、化合物半導体上に二層の性質の異なる
薄膜を被着させ化合物半導体側の層(第Xt脅)がその
上の層(第2層)より広い開口部を有する穴を形成する
第1の工程と、第1層の薄膜をマスクとして化合物半導
体をエツチングし次に気相成長により高濃度の化合物半
導体を選択的に成長させる第2の工程と、第2層の薄膜
をマスクとしてオーミック接触を得るための金属を高濃
度領域上に形成し第1層及び第2層の薄膜を除去すると
同時に第2層の薄膜上の金属も除去する第3の工程と、
高温処理を行い前記金属と高#度化合物半導体を合金化
する第4の工程とを含むことを特徴とする化合物半導体
へのオーミック接触の形成方法にある。
The gist of the present invention is to form a hole in which two layers of thin films with different properties are deposited on a compound semiconductor, and the layer on the compound semiconductor side (layer X) has a wider opening than the layer above it (second layer). a first step in which the compound semiconductor is etched using the first layer thin film as a mask, and then a high concentration compound semiconductor is selectively grown by vapor phase growth; a third step of forming a metal on the high concentration region to obtain ohmic contact, removing the first and second layer thin films, and simultaneously removing the metal on the second layer thin film;
A method for forming an ohmic contact to a compound semiconductor, comprising a fourth step of performing high-temperature treatment to alloy the metal and a high-temperature compound semiconductor.

以下本発明の実施例にもとづき詳細に説明する。The present invention will be described in detail below based on embodiments.

第2図(a)〜(h)は本発明の一実施例の説明のため
の工程断面図である。本発明の一実施例は砒化ガリウム
電界効果トランジスタの製造に適用した例につき説明す
る。すなわち (1)砒化ガリウム結晶11上に4000Xの厚さの第
1層の酸化膜12とその上に200OAの厚さの第2層
の窒化膜13をeva法により成長させる(第2図(a
))。
FIGS. 2(a) to 2(h) are process sectional views for explaining one embodiment of the present invention. An embodiment of the present invention will be described with reference to an example in which the present invention is applied to manufacturing a gallium arsenide field effect transistor. That is, (1) a first layer oxide film 12 with a thickness of 4000X and a second layer nitride film 13 with a thickness of 200OA are grown on the gallium arsenide crystal 11 by the EVA method (see FIG. 2(a)).
)).

(2)次に7オトレジスト14により電極パターンを形
成しく第2図(b) > 、このパターン14をマスク
とし、Cir’4 ガスを用いたドライエツチングによ
り窒化膜13及び酸化膜12をエツチングする(第2図
(C))。
(2) Next, an electrode pattern is formed using a 7-photoresist 14 (see FIG. 2(b)). Using this pattern 14 as a mask, the nitride film 13 and oxide film 12 are etched by dry etching using Cir'4 gas ( Figure 2 (C)).

(3)次にフッ酸とフッ化アンモニウムの混合液で約3
0抄製度エツチングを行う。このとき酸化膜は100A
/秒程度エツチングされるが、窒化膜はほとんどエツチ
ングされないので、第1層の酸化膜12がその上の第2
層の窒化膜より広い開口部を有する穴を形成することが
出来る。
(3) Next, add a mixture of hydrofluoric acid and ammonium fluoride to
0 papermaking degree etching is performed. At this time, the oxide film is 100A
/second, but the nitride film is hardly etched, so the first oxide film 12 is etched into the second layer above it.
Holes having openings wider than the nitride layer can be formed.

しかる後フォトレジストを除去する(第2図(d))。Thereafter, the photoresist is removed (FIG. 2(d)).

(4)次いで酸化膜12をマスクとして硫酸、過酸化水
素、水の混合液を用いて砒化ガリウムを約3000λエ
ツチングする(第2図(e))。
(4) Next, using the oxide film 12 as a mask, the gallium arsenide is etched by approximately 3000λ using a mixed solution of sulfuric acid, hydrogen peroxide, and water (FIG. 2(e)).

(5)この状態でこの結晶をアルシン(AsHs)−有
機ガリウム−水素を用いる熱分解方式の成長炉に入れ、
高濃度の砒化ガリウム結晶を約300OAの厚さに選択
的に成長させる。このとき有機ガリウムとして例えば’
a(Cz Hs)zClを用い適尚な条件を選ぶことに
より嗜化膜上に砒化ガリウム結晶は全く成長しない(第
2図(f))。
(5) In this state, put this crystal in a pyrolysis type growth furnace using arsine (AsHs)-organic gallium-hydrogen,
High concentration gallium arsenide crystals are selectively grown to a thickness of approximately 300 OA. In this case, as organic gallium, for example, '
By using a(Cz Hs)zCl and selecting appropriate conditions, no gallium arsenide crystals will grow on the attenuated film (FIG. 2(f)).

(6)次に窒化膜13をマスクとして、オーミック接触
を形成するための金属として金(Au )−ゲルマニラ
A (Ue ) (ue/Au 12 W%)を150
0Atニツケル(Ni)を500^蒸着する。この時酸
化膜2がその上の窒化膜13より広い開口部を有してい
ることにより、高濃度の砒化ガリウム結晶とオーミック
電極の位置が正しく配列され、かつ金/ゲルマニウムー
ニッケルの層に段切れ部分18.18’ができる(第2
図(g))。
(6) Next, using the nitride film 13 as a mask, 150% of gold (Au)-gel manila A (Ue) (ue/Au 12 W%) is used as a metal for forming ohmic contact.
Deposit 500^ of 0At nickel (Ni). At this time, since the oxide film 2 has a wider opening than the nitride film 13 above it, the high concentration gallium arsenide crystal and the ohmic electrode are aligned correctly, and the gold/germanium-nickel layer is stepped. A cut part 18.18' is formed (second
Figure (g)).

(7)次にこのウェーハを7ツ酸、フッ化アンモニウム
の混合液に約2時間程度つけておくと、18゜18′で
示された金/ゲルマニウムニッケルの段切れ部分からエ
ツチング液が入り酸化膜2をエツチングする。酸化膜が
完全にエツチングされると、酸化膜上の窒化膜及び金/
ゲルマニウム・ニッケルはウェーハからはく離される。
(7) Next, when this wafer is soaked in a mixed solution of hexafluoric acid and ammonium fluoride for about 2 hours, the etching solution enters the gold/germanium nickel step shown at 18°18' and oxidizes. Membrane 2 is etched. When the oxide film is completely etched, the nitride film and gold/metal layer on the oxide film are removed.
The germanium nickel is stripped from the wafer.

この状態で、このウェーハを水素中で480°Cの熱処
理を行うと、砒化ガリウムと金/ゲルマニウム・ニッケ
ルが合金化され、良好なオーミック接触が得られる。
In this state, when this wafer is heat-treated in hydrogen at 480° C., gallium arsenide and gold/germanium/nickel are alloyed, and good ohmic contact is obtained.

以上実施例では砒化ガリウムにオーミック接触は1つま
でもない。
In the above embodiments, there is no ohmic contact with gallium arsenide.

以上説明したように本発明によれば1回、フォトレジス
トのパターンを形成するだけで、高濃度の化合物半導体
とのオーミック電極を形成することができ、かつそのパ
ターンを微小寸法で正しい配列とすることができる。
As explained above, according to the present invention, an ohmic electrode with a highly concentrated compound semiconductor can be formed by forming a photoresist pattern only once, and the pattern can be arranged correctly in minute dimensions. be able to.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)(b)は高濃度の埋込層とオーミックの電
極金属のパターンの位置関係を示す平面図及びその断面
図、第2図(a)〜(h)は本発明の一実施例の説明の
ための工種断面図である。 1.1′・・・・・・高濃度埋込層のパターン、2.2
’・・・・・・オーミックの゛電極金属のパターン、3
.3’・・・・・・高濃度埋込層、11・・・・・・砒
化ガリウム結晶、12・・・−・・酸化膜、13・・・
・・・窒化膜、14・・・・・・フォトレジスト、15
・・・・・・高濃度の砒化ガリウム、16・・・・・・
金、ケルマニウム、17・・・・・・ニッケル[L18
118′・・・・・・段切れ部。 翳1図 捧2図
FIGS. 1(a) and 1(b) are plan views and cross-sectional views showing the positional relationship between the high-concentration buried layer and the ohmic electrode metal pattern, and FIGS. It is a sectional view of the work type for explaining an example. 1.1'...Pattern of high concentration buried layer, 2.2
'・・・Ohmic 'electrode metal pattern, 3
.. 3'...High concentration buried layer, 11...Gallium arsenide crystal, 12...--Oxide film, 13...
...Nitride film, 14...Photoresist, 15
...High concentration of gallium arsenide, 16...
Gold, kermanium, 17...nickel [L18
118'...Step break part. 1 picture of shadow 2 picture

Claims (1)

【特許請求の範囲】[Claims] 化合物半導体上に二層の性質の異なる薄膜を被着させ化
合物半導体側の層(第1層)がその上の層(第214)
より広い開口部を有する穴を形成する第1の工程と、第
1層の薄膜をマスクとじて化合物半導体をエツチングし
次に高濃度の化合物半導体を選択的に成長さ、せる第2
の工程と、第2層の薄膜をマスクとしてオーミック接触
を得るための金属を高濃度領域上に形成し、第1層及び
第2層の薄膜を除去すると同時に第2層の薄膜上の金属
も除去する第3の工程と、高温処理を行い前記金属と高
濃度化合物半導体を合金化する第4の工程とを含むこと
を特徴とする化合物半導体へのオーミック接触の形成方
法。
Two thin films with different properties are deposited on the compound semiconductor, and the layer on the compound semiconductor side (first layer) is the layer above it (the 214th layer).
The first step is to form a hole with a wider opening, and the second step is to etch the compound semiconductor using the first layer thin film as a mask, and then selectively grow a high concentration compound semiconductor.
The second layer thin film is used as a mask to form metal on the high concentration region to obtain ohmic contact, and the first and second layer thin films are removed while the metal on the second layer thin film is also removed. A method for forming an ohmic contact to a compound semiconductor, comprising a third step of removing the metal and a fourth step of alloying the metal and the high concentration compound semiconductor by performing high-temperature treatment.
JP15206382A 1982-09-01 1982-09-01 Forming method of ohmic contact with compound semiconductor Pending JPS5941829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15206382A JPS5941829A (en) 1982-09-01 1982-09-01 Forming method of ohmic contact with compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15206382A JPS5941829A (en) 1982-09-01 1982-09-01 Forming method of ohmic contact with compound semiconductor

Publications (1)

Publication Number Publication Date
JPS5941829A true JPS5941829A (en) 1984-03-08

Family

ID=15532241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15206382A Pending JPS5941829A (en) 1982-09-01 1982-09-01 Forming method of ohmic contact with compound semiconductor

Country Status (1)

Country Link
JP (1) JPS5941829A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01154854A (en) * 1987-12-11 1989-06-16 Nkk Corp Continuous casting method for steel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01154854A (en) * 1987-12-11 1989-06-16 Nkk Corp Continuous casting method for steel

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