JPS58200575A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58200575A JPS58200575A JP8300882A JP8300882A JPS58200575A JP S58200575 A JPS58200575 A JP S58200575A JP 8300882 A JP8300882 A JP 8300882A JP 8300882 A JP8300882 A JP 8300882A JP S58200575 A JPS58200575 A JP S58200575A
- Authority
- JP
- Japan
- Prior art keywords
- film
- emitter
- silicon
- etching
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 230000007704 transition Effects 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 2
- 238000002955 isolation Methods 0.000 abstract description 14
- 238000009413 insulation Methods 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 5
- 239000011733 molybdenum Substances 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract 2
- 238000009933 burial Methods 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 19
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002751 molybdenum Chemical class 0.000 description 1
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- XUIMIQQOPSSXEZ-AKLPVKDBSA-N silicon-31 atom Chemical compound [31Si] XUIMIQQOPSSXEZ-AKLPVKDBSA-N 0.000 description 1
- 210000004894 snout Anatomy 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造法に関し、詳しくは、Ｕ型ア
イソレーションによって素子間分離したバイポーラトラ
ンジスタのエミッタ形成にとくに有用な半導体装置の製
造法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that is particularly useful for forming the emitter of a bipolar transistor whose elements are separated by U-type isolation.
従来のバイポーラトランジスタでは、第１図に示すよう
に、エミッタ３は、ベース拡散領域２に完全に含まれる
ように、写真食刻法を用いて形成されている。これは、
エミッタ３を形成する際、ホトマスク４と半導体基板中
の素子間の絶縁分離領域ｌと重なると、エミッタ３は絶
縁分離領域中に形成されないことから、エミッタ３０面
積がホトマスク４０面積よりも減少するためである。ま
た、ホトマスク４と絶縁分離領域１との重なり方は、マ
スク合せ誤差に応じて変化するため、エミッタ面積もマ
スク合せ誤差に応じて変化し、トラ □ンジスタの特性
変化を招くことになる。In a conventional bipolar transistor, as shown in FIG. 1, the emitter 3 is formed using photolithography so as to be completely included in the base diffusion region 2. this is,
When forming the emitter 3, if the photomask 4 overlaps the insulation isolation region l between the elements in the semiconductor substrate, the emitter 3 will not be formed in the insulation isolation region, so the area of the emitter 30 will be smaller than the area of the photomask 40. It is. Furthermore, since the way the photomask 4 and the insulation isolation region 1 overlap changes depending on the mask alignment error, the emitter area also changes depending on the mask alignment error, leading to changes in the characteristics of the transistor.
しかし、エミッタ３會ベース拡散領域２内に完全におさ
めるためには、マスク合せ誤差を考慮に入れて、ベース
拡散鎖酸を大きくする必散があり、このため、トランジ
スタ面積が増加してしまう。However, in order to completely fit the emitter 3 into the base diffusion region 2, it is necessary to take mask alignment errors into account and increase the base diffusion chain, which increases the transistor area.
また、エミッタを写真食刻法で形成する際、第２図に示
すような矩形のホトマスク９を用いることにより、マス
ク付せ誤差にかかわらずエミッタ８０面積を一定に保つ
ことができる。すなわち、矩形のホトマスク９０４辺の
内、相対する２辺を１
マスク合せ饋差以丘にベース拡散領域７から離れた絶縁
分離領域６中に設け、かつ、他の２辺を絶縁分離領域６
からマスク合せ誤差以上離れたベース拡散領域７中に設
ける。このようにすると、絶縁分離領域６中にはエミッ
タが形成されないため、エミッタ８０２辺の長さは、ベ
ース拡散領域７０辺ｌＯの長さで決まり、他の２辺の長
さは、ホトマスク９の辺１１の長さで決まる。従って、
エミッタ８０面積は一定に保たれることになる。またベ
ースｍｉｎ域７の辺ｌＯの長さもエミッタ８０大きさま
で微細化でき、トランジスタ面積を縮少することができ
る。Further, when forming the emitter by photolithography, by using a rectangular photomask 9 as shown in FIG. 2, the area of the emitter 80 can be kept constant regardless of masking errors. That is, among the four sides of the rectangular photomask 90, two opposing sides are provided in the insulating isolation region 6 which is located away from the base diffusion region 7 at the mask alignment gap, and the other two sides are provided in the insulating isolation region 6.
The base diffusion region 7 is provided at a distance of more than a mask alignment error from the base diffusion region 7. In this case, since no emitter is formed in the insulation isolation region 6, the length of the emitter 802 side is determined by the length of the base diffusion region 70 side IO, and the lengths of the other two sides are determined by the length of the photomask 9. It is determined by the length of side 11. Therefore,
The emitter 80 area will remain constant. Furthermore, the length of the side lO of the base min region 7 can be miniaturized to the size of the emitter 80, and the transistor area can be reduced.
しかし、第２図に示す方法では、ベース抵抗が増加し、
バイポーラトランジスタの遅延時間が増加してしｉう。However, in the method shown in Figure 2, the base resistance increases,
The delay time of the bipolar transistor increases.
これは、ベースコンタクト孔１２までベース電流が流れ
るためには、エミツタ８下部の抵抗の大きいベース領域
を通過する会費があるためである。一方、第１図に示し
た場合では、ベース電流は、ベース周辺の比較的抵抗が
低い領域全経由してベースコンタクト孔５まで流れるた
め、第２図の場合よりベース抵抗が減少する。This is because, in order for the base current to flow to the base contact hole 12, there is a need to pass through the base region of high resistance below the emitter 8. On the other hand, in the case shown in FIG. 1, the base current flows to the base contact hole 5 through the entire region around the base where the resistance is relatively low, so that the base resistance is reduced compared to the case shown in FIG.
本発明は、従来のバイポーラトランジスタのエミッタ形
成法のこれらの問題点ケ解決することを目的としたもの
で、シリコン埋め込みによるＵ型アイソレーションを用
いた絶縁膜分離領域からある一定距ｈｆ隔てた領域にセ
ルファラインによってエミッタを形成する方法を提供す
るものである。The present invention aims to solve these problems in the conventional emitter formation method for bipolar transistors. The present invention provides a method of forming an emitter using a self-line.
以下バイポーラトランジスタの製造に関する実施例を用
いて、本発明の詳細な説明する。The present invention will be described in detail below using examples relating to the manufacture of bipolar transistors.
まず、第３図に示すように、シリコン半導体基板２１０
表面に、周知の方法によってコレクタ埋込Ｉ＠ ２２
ｆｒ設け、その上にトランジスタの能動部分となるシリ
コンエピタキシャル層２３を形成した後、その表面を熱
酸化して酸化シリコン膜２４を形成し、さらにその上に
、周知のＣＶＤ法によってテラ化シリコン膜２５を形成
した。First, as shown in FIG. 3, a silicon semiconductor substrate 210 is
Embed the collector on the surface by a well-known method I@22
After forming a silicon epitaxial layer 23 that will become the active part of the transistor, the surface is thermally oxidized to form a silicon oxide film 24, and then a TERRA silicon film 24 is formed on it by a well-known CVD method. 25 was formed.
次に通常のホトエツチング法を一用いて上記チツ化シリ
コン膜２５會パターニングした後、露出された酸化シリ
コン膜２４をエッチして除去する。Next, the silicon oxide film 25 is patterned using a conventional photoetching method, and then the exposed silicon oxide film 24 is etched and removed.
七の後、反応性スパッタエツチングａｔ用い、テラ化シ
リコン膜２５をマスクにして、埋込み層２２およびシリ
コン半導体基板２１１エツチングし、コレクタ埋込み層
２２を突き抜けるように溝２６會形成した。After that, the buried layer 22 and the silicon semiconductor substrate 211 were etched using reactive sputter etching using the terraned silicon film 25 as a mask, and a groove 26 was formed so as to penetrate through the collector buried layer 22.
次に、チャネル発生防止の目的で埋込みｒｍ ２２と反
対の導電性を持つ不純物を、イオン打込み法によって上
記＃１２６の底面に導入した。チッ素雰囲気中でアニニ
ルした後、チツ化シリコン膜２５をマスクに選択酸化を
行ない、上記溝２６内に厚い酸化シリコン膜２７（０，
３〜１．０μｍ８度）を形成して、溝２６の表面を覆っ
た。Next, for the purpose of preventing channel generation, an impurity having conductivity opposite to that of the buried rm 22 was introduced into the bottom surface of #126 by ion implantation. After annealing in a nitrogen atmosphere, selective oxidation is performed using the silicon nitride film 25 as a mask to form a thick silicon oxide film 27 (0, 0,
3 to 1.0 μm (8°) to cover the surface of the groove 26.
マスクに用いた上記テラ化シリコン膜２５を除去した後
、第４図に示すように、イオン打込み法によって、ベー
ス拡散１−２８を形成した。さらに、通常のＣＶＤ法に
よってチツ化シリコン膜２９および酸化シリコン膜３０
？形成した後、溝２６内に多結晶シリコン３１Ｔｈ形成
することによりアイソレーションが形成された。なお、
ここでは溝２６円に多結晶シリコンを形成したが、非晶
質シリコンないしは単結晶シリコンでもよい。After removing the Tera silicon film 25 used as a mask, a base diffusion 1-28 was formed by ion implantation, as shown in FIG. Furthermore, a silicon oxide film 29 and a silicon oxide film 30 are formed by a normal CVD method.
? After the formation, isolation was formed by forming polycrystalline silicon 31Th in the groove 26. In addition,
Here, polycrystalline silicon is formed in the groove 26, but amorphous silicon or single crystal silicon may also be used.
次に、モリブデン膜３２を被着し、４００〜１０００ｔ
：”の熱処理を行ない、モリブデン膜３２と多結晶シリ
コン３１とを反応させ、金楓シリブイド３３を形成した
。この際、モリブデンシリサイド３３を横方向にも成長
させ、ベース拡散層２８を一部覆うようにモリブデンシ
サイドのひきし３４を形成した。その後、未反応のモリ
ブデン膜３２をリン酸系のエツチング液で除去した。Next, a molybdenum film 32 is deposited and
:'' heat treatment was performed to cause the molybdenum film 32 and polycrystalline silicon 31 to react, forming a gold maple silicide 33. At this time, the molybdenum silicide 33 was also grown in the lateral direction to partially cover the base diffusion layer 28. A molybdenum oxide film 34 was formed in this manner. Thereafter, the unreacted molybdenum film 32 was removed using a phosphoric acid-based etching solution.
次に、第２図のホトマスク９■ようなもの管用い通常の
写真食刻法によシ沸酸系のエッチ液でエミッタ形成時の
孔３５ｆｒ形成した。このようにすると、第５図に示す
ように、モリブデンシリ丈イド３３の下部の酸化シリコ
ン膜３０はエツチングされずに残る。その恢、モリブデ
ンシリ丈イド３３をＣＦ、？！−主成分ガスとしたドラ
イエツチング法により除去した。このとき、エミッタ孔
３５０部分のチン化シリコン膜２９も若干エッチされる
が、すべてエッチされない程度にチン化シリコン膜２９
の膜厚を設定した。Next, holes 35fr for forming an emitter were formed using a fluoric acid-based etchant using a conventional photoetching method using a tube such as the photomask 9 in FIG. In this way, as shown in FIG. 5, the silicon oxide film 30 under the molybdenum silicate film 33 remains without being etched. In that case, molybdenum series Id 33 is CF? ! -Removed by dry etching method using gas as the main component. At this time, the silicon nitride film 29 in the portion of the emitter hole 350 is also slightly etched, but the silicon nitride film 29 is not completely etched.
The film thickness was set as follows.
次に、第６図に示すように、多結晶シリコン３１ｉ熱酸
化して酸化シリコ呵、岬３６ ｔ ｆｆｐ成した後、Ｃ
Ｆｎｔ主成分ガスとして用いたドライエツチング法によ
り、エミッタ孔３５の領域のチン化シリコン膜２９をエ
ツチングした。その後、イオン打込み法によりエミッタ
拡散層３７倉形成した。Next, as shown in FIG. 6, polycrystalline silicon 31i is thermally oxidized to form a silicon oxide layer, cape 36tffp, and then C
The silicon nitride film 29 in the region of the emitter hole 35 was etched by dry etching using Fnt as the main component gas. Thereafter, 37 emitter diffusion layers were formed by ion implantation.
以上のように形成したバイポーラトランジスタの平面横
這に、第７図のようになる。すなわち、絶縁分離領域１
３でかこまれたベース拡散領域１４中に、第２図記号９
で示したようなホトマスク１６會用いてエミッタ１５１
に形成するわけであるが、ホトマスク１６下部において
エミッタ１５と絶縁膜分離領域１３の間にはベース拡散
領域１７が形成される。従って、第７図に示した構造の
トランジスタでは、第１図に示したトランジスタと同様
、ベース電流がエミッタ下部のベースの周辺の比較的抵
抗が低いペース拡散領域全経由して、ベースコンタクト
孔１８まで流れるため、ベース抵抗は第２図のトランジ
スタ構造より減少する。The horizontal plane of the bipolar transistor formed as described above is as shown in FIG. That is, the insulation isolation region 1
In the base diffusion region 14 surrounded by 3, there is a symbol 9 in FIG.
Emitter 151 is formed using a photomask 16 as shown in
However, a base diffusion region 17 is formed between the emitter 15 and the insulating film isolation region 13 under the photomask 16. Therefore, in the transistor having the structure shown in FIG. 7, as in the transistor shown in FIG. 2, the base resistance is reduced compared to the transistor structure of FIG.
また、第７図に示したホトマスク１６の下部にあるエミ
ッタ１５と絶縁１盆離領域１３との間隔は第４図の金桟
シリサイド３３のひさし３４の長ざで決まる。従って、
このひさし３４Ｇ’）長さをホトマスク１６と半導体基
板との間の合せ誤差以下にすると、ベース拡散領域１４
の面積は、第１図に示したベース拡散領域よりも減少さ
せることができる。このため、第７図に示したトランジ
スタ面積は第１図に示したトランジスタ面積より減少さ
せることができる。Further, the distance between the emitter 15 at the bottom of the photomask 16 and the insulation 1 isolation region 13 shown in FIG. 7 is determined by the length of the eaves 34 of the metal silicide 33 shown in FIG. Therefore,
When the length of this eave 34G') is made equal to or less than the alignment error between the photomask 16 and the semiconductor substrate, the base diffusion region 14
The area of the base diffusion region shown in FIG. 1 can be reduced compared to the base diffusion region shown in FIG. Therefore, the area of the transistor shown in FIG. 7 can be made smaller than the area of the transistor shown in FIG.
【図面の簡単な説明】
＠１図および第２図は従来技術により作製されたバイポ
ーラトランジスタの一部の構造を示す平面図、第３図乃
至第６図は本発明の一実施例を示す工程図、第７図は本
発明の実施例を示す平面図である。
１．６．１３・・・菓子間の絶縁分離領域、２，７゜１
４．１７・・・ベース拡散領域、３，８．１５・・・エ
ミ７り、５，１２．１８・・・コレクタコンタクト子り
。
４．９．１６・・・エミッタ形成時のホトマスク、ｌＯ
・・・ベース拡散領域の辺、１１・・・エミッタ形成時
のホトマスクの辺、２１・・・基板、２２・・・埋込層
、２３・・・シリコンエピタキシャル層、２８・・・ベ
ース拡散１−５３７・・・エミッタ拡散層、２４，２７
゜３０．３６・・・酸化シリコン膜、２５．２９・・・
テラ化シリコン［，３１・・・’４ 結晶シリコン、３
２・・・モｌＪｔ図
葛 ３ 目
５
１！Ｊ ４ 図
第 ５ 目
！吻
％ ６ 因
３５ ２４ ３６
／
ｚｔｌ[BRIEF DESCRIPTION OF THE DRAWINGS] Figures 1 and 2 are plan views showing the structure of a part of a bipolar transistor manufactured by the conventional technique, and Figures 3 to 6 are steps showing an embodiment of the present invention. FIG. 7 is a plan view showing an embodiment of the present invention. 1.6.13...Insulating separation area between sweets, 2.7゜1
4.17...Base diffusion region, 3,8.15...Emitter 7, 5,12.18...Collector contact. 4.9.16...Photomask during emitter formation, lO
... Side of base diffusion region, 11 ... Side of photomask during emitter formation, 21 ... Substrate, 22 ... Buried layer, 23 ... Silicon epitaxial layer, 28 ... Base diffusion 1 -537... Emitter diffusion layer, 24, 27
゜30.36...Silicon oxide film, 25.29...
Tera silicon [,31...'4 Crystalline silicon, 3
2...Mol Jt Zu Kuzu 3 eyes 5 1! J 4 Figure 5! Snout% 6 factor 35 24 36 / ztl
Claims (1)
する工程。 （２）上記チン化シリコン膜の所望部分をエッチして除
去する工程。 （３）上記チン化シリコン膜をマスクに用いて上記半導
体基板をエッチし、溝を形成する工程。 （４）上記壽の表面ケ酸化シリコン膜によって覆う工程
。 （５） 絶縁膜を全面に形成する工程。 （句 上記無内にシリコンを充填する工程。 （７）遷移金輌膜を被着する工程。 （８）熱処理により、上記遷移金輌膜と上記溝内に充填
されているシリコンの表面を反応させ、上記溝上および
周辺部に金稿シリサイド膜を形成する工程。 （９）Ｅ記遷移金媚膜の未反応の部分を除去する工程。 （Ｘ）上記金鵬シリサイド膜倉マスクに用いて、上記絶
縁膜の露出部分をエッチし除去する工程。 （旬上記金属シリサイド膜を除去する工程。 （功上記溝内のシリコンの露出された部分を酸化する工
程。 （２）上記絶縁膜をマスクに用いて、上記チン化シリコ
ン膜の露出された部分をエッチし除去する工程。[Claims] 1. A method for manufacturing a semiconductor device including the following process. (1) Step of depositing a silicon nitride film on the surface of a semiconductor substrate. (2) A step of etching and removing a desired portion of the silicon nitride film. (3) A step of etching the semiconductor substrate using the silicon nitride film as a mask to form a groove. (4) A step of covering the surface of the box with a silicon oxide film. (5) Step of forming an insulating film over the entire surface. (phrase) Step of filling the above groove with silicon. (7) Step of depositing a transition gold film. (8) Heat treatment causes the surface of the transition gold film and the silicon filled in the groove to react. (9) Step of removing unreacted portions of the E-type transition gold film. (X) Using the above metal silicide film mask, A step of etching and removing the exposed portion of the insulating film. and etching and removing the exposed portion of the silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8300882A JPS58200575A (en) | 1982-05-19 | 1982-05-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8300882A JPS58200575A (en) | 1982-05-19 | 1982-05-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58200575A true JPS58200575A (en) | 1983-11-22 |
Family
ID=13790214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8300882A Pending JPS58200575A (en) | 1982-05-19 | 1982-05-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58200575A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4983226A (en) * | 1985-02-14 | 1991-01-08 | Texas Instruments, Incorporated | Defect free trench isolation devices and method of fabrication |
-
1982
- 1982-05-19 JP JP8300882A patent/JPS58200575A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4983226A (en) * | 1985-02-14 | 1991-01-08 | Texas Instruments, Incorporated | Defect free trench isolation devices and method of fabrication |
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