JPS5940862U - Peak value voltage detection circuit - Google Patents
Peak value voltage detection circuitInfo
- Publication number
- JPS5940862U JPS5940862U JP13555582U JP13555582U JPS5940862U JP S5940862 U JPS5940862 U JP S5940862U JP 13555582 U JP13555582 U JP 13555582U JP 13555582 U JP13555582 U JP 13555582U JP S5940862 U JPS5940862 U JP S5940862U
- Authority
- JP
- Japan
- Prior art keywords
- peak value
- detection circuit
- voltage detection
- value voltage
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来のピーク値検出回路。第２図は、デユー
ティファクタの小さく急峻なスパイク！圧波形の例。第
３図は、第１図の回路に於いてコンデンサーの値を太き
（とった場合の出力波形。第４図は、同じくコンデンサ
ーの値を小さくとった場合の出力波形。第５図は、本考
案に於いて正のピーク値電圧検出回路の一実施例。第６
図は、本考案の実施例に於ける各部の電圧波形。なお回
路図に於いて１，６は入力端子、２． ｚｌ、 ｚ２・
・・Ｚｎはインピーダンス変換器、３．Ｄｌ、Ｄ２．・
・・Ｄｎはダイオード、４．７はコンデンサ、５，８は
出力端子、Ｔ１． Ｔ２．・・・Ｔｎはすこしずつ遅れ
時間の異る遅延回路、又波形図においてａはスパイク波
形、ＣＬ、Ｃ８はそれぞれコンデンサの値の大きい時及
び小さい時の出力波形、ｂ、 ｃは遅延回路を通した
時のスパイク波形。ｄはコンデンサのない時を仮定した
出力波形、ｅは出力端子に於けるピーク値出力。
さ ５回
よ−し７
５＋Ｃ口Figure 1 shows a conventional peak value detection circuit. Figure 2 shows a small and steep spike in the duty factor! Example of pressure waveform. Figure 3 shows the output waveform when the capacitor value is set to a large value in the circuit shown in Figure 1. Figure 4 shows the output waveform when the capacitor value is set to a small value. An embodiment of the positive peak value voltage detection circuit in the present invention. 6th
The figure shows voltage waveforms at various parts in an embodiment of the present invention. In the circuit diagram, 1 and 6 are input terminals, 2. zl, z2・
...Zn is an impedance converter, 3. Dl, D2.・
...Dn is a diode, 4.7 is a capacitor, 5 and 8 are output terminals, T1. T2. ...Tn is a delay circuit with slightly different delay times, and in the waveform diagram, a is a spike waveform, CL and C8 are output waveforms when the capacitor value is large and small, respectively, and b and c are output waveforms that pass through the delay circuit. The spike waveform when d is the output waveform assuming no capacitor, and e is the peak value output at the output terminal. 5 times 7 5+C mouth
Claims (1)
時間の異る同数個の遅延回路と同数個のダイオニドと１
個のコンデンサーと出力端子とから構成され、入力端子
と各インピーダンス変換器の入力端を互いに接続し、各
インピーダンス変換器の出力端と各遅延回路の入力端子
をそれぞれ接続し、各遅延回路の出力端子を各ダイオー
ドの一方の電極へそれぞれ接続し、各ダイオードの他方
の電極を互いに接続しコンデンサーと出力端子へ接続し
た事を特徴とするピーク値検出回路。An input terminal, multiple impedance converters, the same number of delay circuits with slightly different delay times, the same number of diodes, and 1
The input terminal and the input terminal of each impedance converter are connected to each other, the output terminal of each impedance converter is connected to the input terminal of each delay circuit, and the output terminal of each delay circuit is connected to each other. A peak value detection circuit characterized in that a terminal is connected to one electrode of each diode, the other electrode of each diode is connected to each other, and connected to a capacitor and an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13555582U JPS5940862U (en) | 1982-09-07 | 1982-09-07 | Peak value voltage detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13555582U JPS5940862U (en) | 1982-09-07 | 1982-09-07 | Peak value voltage detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5940862U true JPS5940862U (en) | 1984-03-15 |
| JPH025420Y2 JPH025420Y2 (en) | 1990-02-08 |
Family
ID=30305072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13555582U Granted JPS5940862U (en) | 1982-09-07 | 1982-09-07 | Peak value voltage detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5940862U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4926249A (en) * | 1972-07-06 | 1974-03-08 | ||
| JPS50103107A (en) * | 1974-01-24 | 1975-08-14 | ||
| JPS56142935A (en) * | 1980-04-08 | 1981-11-07 | K M Kikaku Kk | Stabilized piling method for earth slope |
-
1982
- 1982-09-07 JP JP13555582U patent/JPS5940862U/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4926249A (en) * | 1972-07-06 | 1974-03-08 | ||
| JPS50103107A (en) * | 1974-01-24 | 1975-08-14 | ||
| JPS56142935A (en) * | 1980-04-08 | 1981-11-07 | K M Kikaku Kk | Stabilized piling method for earth slope |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH025420Y2 (en) | 1990-02-08 |
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