JPS58101398U - sample hold circuit - Google Patents
sample hold circuitInfo
- Publication number
- JPS58101398U JPS58101398U JP19542181U JP19542181U JPS58101398U JP S58101398 U JPS58101398 U JP S58101398U JP 19542181 U JP19542181 U JP 19542181U JP 19542181 U JP19542181 U JP 19542181U JP S58101398 U JPS58101398 U JP S58101398U
- Authority
- JP
- Japan
- Prior art keywords
- hold circuit
- sample hold
- terminal
- supplied
- diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electronic Switches (AREA)
- Details Of Television Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のサンプルホールド回路の構成を示す接続
図、第2図はこの考案の一実施例の接続図、第3図は二
の考案の一実施例の動作説明に用いる等価回路図である
。
1・・・・・・入力端子、2・・・・・・出力端子、4
,5・・・・・・パルス電圧の供給される端子。Figure 1 is a connection diagram showing the configuration of a conventional sample and hold circuit, Figure 2 is a connection diagram of an embodiment of this invention, and Figure 3 is an equivalent circuit diagram used to explain the operation of an embodiment of the second invention. be. 1...Input terminal, 2...Output terminal, 4
, 5...Terminal to which pulse voltage is supplied.
Claims (1)
サが接続され、出力信号が取出される第2の端子、パル
ス信号が供給される第3及び第4の端子の各端子間の枝
路に、夫々複数個のダイオードを直列に接続してダイオ
ードブリッジを構成し、上記複数個のダイオードの接続
点をコンデンサを介して接地するようにしたサンプルホ
ールド回路。A branch path between the first terminal to which the input signal is supplied, the second terminal to which the hold capacitor is connected and the output signal is taken out, and the third and fourth terminals to which the pulse signal is supplied. , a sample and hold circuit in which a plurality of diodes are connected in series to form a diode bridge, and a connection point of the plurality of diodes is grounded via a capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19542181U JPS58101398U (en) | 1981-12-25 | 1981-12-25 | sample hold circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19542181U JPS58101398U (en) | 1981-12-25 | 1981-12-25 | sample hold circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58101398U true JPS58101398U (en) | 1983-07-09 |
JPS6125119Y2 JPS6125119Y2 (en) | 1986-07-28 |
Family
ID=30108698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19542181U Granted JPS58101398U (en) | 1981-12-25 | 1981-12-25 | sample hold circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58101398U (en) |
-
1981
- 1981-12-25 JP JP19542181U patent/JPS58101398U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6125119Y2 (en) | 1986-07-28 |
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