JPH025420Y2 - - Google Patents

Info

Publication number
JPH025420Y2
JPH025420Y2 JP1982135555U JP13555582U JPH025420Y2 JP H025420 Y2 JPH025420 Y2 JP H025420Y2 JP 1982135555 U JP1982135555 U JP 1982135555U JP 13555582 U JP13555582 U JP 13555582U JP H025420 Y2 JPH025420 Y2 JP H025420Y2
Authority
JP
Japan
Prior art keywords
waveform
capacitor
output terminal
peak value
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982135555U
Other languages
Japanese (ja)
Other versions
JPS5940862U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13555582U priority Critical patent/JPS5940862U/en
Publication of JPS5940862U publication Critical patent/JPS5940862U/en
Application granted granted Critical
Publication of JPH025420Y2 publication Critical patent/JPH025420Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は、スイツチング電源等のスパイク電圧
の様にデユーテイフアクターの小さくかつ急峻な
電圧波形のピーク値を検出する回路に関するもの
である。
[Detailed Description of the Invention] The present invention relates to a circuit that detects the peak value of a small and steep voltage waveform of a duty factor, such as a spike voltage of a switching power supply.

従来のこの種の回路は、第1図に示す様に1個
のインピーダンス変換器と1個のダイオードと1
個のコンデンサーより構成されている。従つて第
2図に示す様なスイツチング電源のスパイクのよ
うにデユーテイフアクターの小さく急峻な電圧波
形に対してはピーク値を検出する事が不可能であ
つた。すなわちコンデンサーの値を大きくすると
第3図のCLの様に、スパイク波形があまりに単
時間である為、ピーク値とコンデンサーの出力電
圧を等しくするまで充電することが出来ずピーク
値よりかなり低い電圧値しか出力することが出来
ない。又第4図のCSの様にCを小さく選ぶと波高
値までコンデンサーの値は追従するが、コンデン
サー容量が少さい為、ダイオードの逆漏れ電流や
コンデンサーの内部抵抗や出力端子へつながれる
直流電圧計の入力抵抗等によりピーク値電圧を短
時間しか維持することが出来ず結局ピーク値検出
回路として使用する事が不可能であつた。
A conventional circuit of this type consists of one impedance converter, one diode, and one impedance converter, as shown in Figure 1.
It consists of several capacitors. Therefore, it has been impossible to detect the peak value of a small and steep voltage waveform of a duty factor, such as a spike in a switching power supply as shown in FIG. In other words, when the value of the capacitor is increased, as shown in C L in Figure 3, the spike waveform is so short that it is not possible to charge the capacitor until the peak value is equal to the output voltage of the capacitor, resulting in a voltage that is much lower than the peak value. Only values can be output. Also, if C is chosen to be small like C S in Figure 4, the value of the capacitor will follow up to the peak value, but since the capacitance of the capacitor is small, the reverse leakage current of the diode, the internal resistance of the capacitor, and the DC current connected to the output terminal will increase. The peak value voltage could only be maintained for a short time due to the input resistance of the pressure gauge, and as a result, it was impossible to use it as a peak value detection circuit.

本考案は、デユーテイフアクターの小さく急峻
な電圧波形の波高値を検出する事を目的としたも
のである。
The purpose of the present invention is to detect the peak value of a small and steep voltage waveform of a duty factor.

本考案は、入力端子と複数のインピーダンス変
換器と少しずつ遅れ時間の異る同数個の遅延回路
と同数個のダイオードと1個のコンデンサーと出
力端子とから構成され、入力端子と各インピーダ
ンス変換器の入力端を互いに接続し各インピーダ
ンス変換器の出力端と各遅延回路の入力端子をそ
れぞれ接続し、各遅延回路の出力端子を各ダイオ
ードの一方の電極へそれぞれ接続し、各ダイオー
ドの他方の電極を互いに接続しコンデンサーと出
力端子へ接続した事を特徴とするピーク値検出回
路である。
The present invention consists of an input terminal, multiple impedance converters, the same number of delay circuits with slightly different delay times, the same number of diodes, one capacitor, and an output terminal. The input terminals of each impedance converter are connected to each other, the output terminal of each impedance converter is connected to the input terminal of each delay circuit, the output terminal of each delay circuit is connected to one electrode of each diode, and the other electrode of each diode is connected to the output terminal of each impedance converter. This is a peak value detection circuit characterized by connecting the two to each other and to the capacitor and output terminal.

本考案に一実施例を第5図に示し正のピーク値
検出の場合について説明する。入力端子6に入力
されたデユーテイフアクタの小さなスパイク波形
はそれぞれ互いに入力を接続されたn個のインピ
ーダンス変換器Z1,Z2……Zoに入力される。そし
てその後にそれぞれ接続された少しずつ遅延時間
の異る遅延回路T1,T2……Toを通ることによ
り、第6図のa,b,cのようにスパイク波形が
時間的に遅れる。これらの波形をそれぞれ後へ接
続されたダイオードD1,D2,……Doが正の成分
だけを通過させるので、各ダイオードのカソード
間を互いに接続すれば出力端子8には第6図dの
様に、急峻な波形の形は同じであるが同一時間内
に存在する波形の数がふえたデユーテイフアクタ
の改善された波形が得られる。この波形dは出力
端子8にコンデンサ7を接続する事により各波形
ごとに波高値検出されて波形eの様に目的のピー
ク値電圧を得る事が出来る。
An embodiment of the present invention is shown in FIG. 5, and the case of detecting a positive peak value will be described. The small spike waveform of the duty factor input to the input terminal 6 is input to n impedance converters Z 1 , Z 2 . . . Z o whose inputs are connected to each other. Then, by passing through connected delay circuits T 1 , T 2 , . . . , T o having slightly different delay times, the spike waveform is delayed in time as shown in a, b, and c in FIG. 6. The diodes D 1 , D 2 , ...D o connected to the rear of these waveforms pass only the positive components, so if the cathodes of each diode are connected to each other, the output terminal 8 will have the waveform shown in Figure 6 d. An improved waveform of the duty factor is obtained in which the shape of the steep waveform is the same, but the number of waveforms existing within the same time is increased. By connecting the capacitor 7 to the output terminal 8, the peak value of this waveform d is detected for each waveform, and the desired peak value voltage can be obtained as in the waveform e.

ここで波形eは、第5図に於いてコンデンサ7
の値を大きくとり第3図CLの様に放電時間を長
くする様選んだ時のものである。波形eに示す如
く最初のスパイク波形が終わるとコンデンサの放
電が始まるが、従来の場合と異り完全に放電しき
る前に本考案による遅延スパイク波形b……cが
コンデンサーに加わる為、充電開始の電圧がスパ
イク波形のくりかえしとともに逐次上昇しついに
は、ピーク電圧に等しくなる。
Here, the waveform e corresponds to the capacitor 7 in FIG.
This is when the value of is set large and the discharge time is lengthened as shown in Figure 3 C L. As shown in waveform e, the capacitor starts discharging when the first spike waveform ends, but unlike the conventional case, the delayed spike waveform b...c according to the present invention is applied to the capacitor before it is completely discharged, so it is difficult to start charging. The voltage increases sequentially as the spike waveform repeats, and finally becomes equal to the peak voltage.

この様に入力信号波形と全く同一波形を時系列
上に複数新たに作り出すことにより従来不可能で
あつたデユーテイフアクタの小さな高周波成分の
大きい急峻な電圧波形のピーク値を検出すること
が可能となりスイツチング電源のスパイク等のピ
ーク値測定が可能となる。又本考案を用いれば波
高値を従来より正しい値でそのまま時間的に従来
より長く保存することが可能となるので、高速直
流電圧計を用い測定の同期をとる事により、急峻
な波形の単発現象のピーク値測定も可能となる。
In this way, by creating multiple new waveforms that are exactly the same as the input signal waveform in time series, it is possible to detect the peak value of the steep voltage waveform of the duty factor with a large high frequency component, which was previously impossible. This makes it possible to measure peak values such as spikes in switching power supplies. In addition, by using the present invention, it is possible to store the peak value as it is at a correct value for a longer period of time than before, so by synchronizing measurements using a high-speed DC voltmeter, it is possible to detect single phenomena with steep waveforms. Peak value measurement is also possible.

又、ダイオードの向きを逆にとる事により負の
ピーク値の検出や、両方併用する事により正負間
のピーク値を測定する事も本考案で可能となる。
Furthermore, by reversing the direction of the diode, it is possible to detect a negative peak value, and by using both in combination, it is also possible to measure a peak value between positive and negative.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来のピーク値検出回路。第2図
は、デユーテイフアクタの小さく急峻なスパイク
電圧波形の例。第3図は、第1図の回路に於いて
コンデンサーの値を大きくとつた場合の出力波
形。第4図は、同じくコンデンサーの値を小さく
とつた場合の出力波形。第5図は、本考案に於い
て正のピーク値電圧検出回路の一実施例。第6図
は、本考案の実施例に於ける各部の電圧波形。な
お回路図に於いて1,6は入力端子、2,Z1,Z2
……Zoはインピーダンス変換器、3,D1,D2
……Doはダイオード、4,7はコンデンサ、5,
8は出力端子、T1,T2,……Toはすこしずつ遅
れ時間の異る遅延回路、又波形図においてaはス
パイク波形、CL,CSはそれぞれコンデンサの値
の大きい時及び小さい時の出力波形、b,cは遅
延回路を通した時のスパイク波形。dはコンデン
サのない時を仮定した出力波形、eは出力端子に
於けるピーク値出力。
Figure 1 shows a conventional peak value detection circuit. Figure 2 is an example of a small and steep spike voltage waveform of a duty factor. Figure 3 shows the output waveform when the capacitor value is increased in the circuit shown in Figure 1. Figure 4 shows the output waveform when the capacitor value is also reduced. FIG. 5 shows an embodiment of the positive peak voltage detection circuit according to the present invention. FIG. 6 shows voltage waveforms at various parts in the embodiment of the present invention. In the circuit diagram, 1 and 6 are input terminals, 2, Z 1 , Z 2
...Z o is an impedance converter, 3, D 1 , D 2 ,
...D o is a diode, 4 and 7 are capacitors, 5,
8 is the output terminal, T 1 , T 2 , ... T o are delay circuits with slightly different delay times, and in the waveform diagram, a is a spike waveform, and C L and C S are the values when the capacitor value is large and small, respectively. The output waveform at the time, b and c are the spike waveforms when passed through the delay circuit. d is the output waveform assuming no capacitor, and e is the peak value output at the output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端子と複数のインピーダンス変換器と少し
ずつ遅れ時間の異る同数個の遅延回路と同数個の
ダイオードと1個のコンデンサーと出力端子とか
ら構成され、入力端子と各インピーダンス変換器
の入力端を互いに接続し、各インピーダンス変換
器の出力端と各遅延回路の入力端子をそれぞれ接
続し、各遅延回路の出力端子を各ダイオードの一
方の電極へそれぞれ接続し、各ダイオードの他方
の電極を互いに接続しコンデンサーと出力端子へ
接続した事を特徴とするピーク値検出回路。
It consists of an input terminal, multiple impedance converters, the same number of delay circuits with slightly different delay times, the same number of diodes, one capacitor, and an output terminal. Connect each other, connect the output terminal of each impedance converter and the input terminal of each delay circuit, connect the output terminal of each delay circuit to one electrode of each diode, and connect the other electrode of each diode to each other. A peak value detection circuit characterized by being connected to a capacitor and an output terminal.
JP13555582U 1982-09-07 1982-09-07 Peak value voltage detection circuit Granted JPS5940862U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13555582U JPS5940862U (en) 1982-09-07 1982-09-07 Peak value voltage detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13555582U JPS5940862U (en) 1982-09-07 1982-09-07 Peak value voltage detection circuit

Publications (2)

Publication Number Publication Date
JPS5940862U JPS5940862U (en) 1984-03-15
JPH025420Y2 true JPH025420Y2 (en) 1990-02-08

Family

ID=30305072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13555582U Granted JPS5940862U (en) 1982-09-07 1982-09-07 Peak value voltage detection circuit

Country Status (1)

Country Link
JP (1) JPS5940862U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4926249A (en) * 1972-07-06 1974-03-08
JPS50103107A (en) * 1974-01-24 1975-08-14
JPS56142935A (en) * 1980-04-08 1981-11-07 K M Kikaku Kk Stabilized piling method for earth slope

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4926249A (en) * 1972-07-06 1974-03-08
JPS50103107A (en) * 1974-01-24 1975-08-14
JPS56142935A (en) * 1980-04-08 1981-11-07 K M Kikaku Kk Stabilized piling method for earth slope

Also Published As

Publication number Publication date
JPS5940862U (en) 1984-03-15

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