SU1415366A2 - High-voltage high-frequency voltage converter - Google Patents

Abstract

The invention relates to electrical engineering, namely voltage converters. The purpose of the invention is to improve the quality of the output voltage by reducing the instability of the output voltage in a wide range of variation of the load current. The voltage converter is built on a push-pull circuit with a fixed level of switching transistor. The switching level of transistors 4 and 5 of the converter is proportional to the input voltage and is formed using voltage dividers 6, 7, resistors 12, 13, 21 and two comparators 14 and 15. By selecting the switching level of the threshold device 19, the transfer ratio of one of the dividers, which allows the switching path of the transistors 4 and 5 of the converter to change, thereby reducing the output voltage at low load currents. 4 il. Q 9

Description

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The invention relates to a conversion technique, can be used in the development of high voltage power sources and is the improvement of the converter according to the authors. ev No. 1153384.

The purpose of the invention is to improve the quality of the output / output voltage by reducing the instability of the output voltage in a wide range of variation of the load current.

FIG. 1 shows a block diagram of a high-voltage high-frequency voltage converter; in fig. 2-4 are voltage and current diagrams at various points in the circuit for two modes of operation of the high-voltage high-frequency voltage converter, as well as its output characteristic.

The high-voltage high-frequency voltage converter contains a formative1 1 pulse, the first logical 11 element AND 2, the second logical element AND 3, the first transistor 4, the second transistor 5, the first divider 6 voltage, the second de: voltage 7, the capacitor 8, the first diode 9, the transformer 1U, the second diode 11, the first resistor 12, the second resistor 13, the first comparator 14, the second comparator 15, the rectifier 16, capacitive fil) Tr 17, current sensor 18, threshold device 19, switch 20.

Direct output of shaper 1 IMP. p. ssov connected to the first input of the second element And 3. The output of the first element 1 2 is connected to the base of the first transistor 4, and the output of the second element And 3 is connected to the base of the second transistor 5. The emitters of the first 4 and second 5 transistors are combined and connected The modules are connected to the first inputs of the first 6 and three direct voltage dividers, with the first output of the capacitor 8 and are connected to the common input output. The collector of the first transistor 4 is connected to the second input of the first voltage divider 6, with the anode of the first diode 9 and with the start of the primary winding of the transformer 10. The collector of the second transistor 1) 5 connects to the second input of the second divider 7 voltage with the anode of the second diode 11 and the end of the primary winding of the transformer. The cathodes of the first 9 and second 1 1 diodes are disconnected, and through the first resistor 12 are connected to the second terminal

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Sensor B, 1: The first output of the second resistor 13 and the inverter are the lean inputs of the first 14 and second 15 comparators. The non-inverting input of the first comparator 14 is connected to the output of the second voltage divider 7. The non-inverted I1II input of the second comparator 15 is connected to the output of the first voltage divider 6. The output of the first comparator 14 is connected to the second input of the first element 2, and the output of the second comparator 15 is connected to the second input of the second element 3. The secondary winding of the transformer 10 through the rectifier 16 and the capacitive filter 17 is connected to the terminals for connecting the load. The input of current sensor 18 is connected between the midpoint of the primary winding of the transformer 10 and the input terminal. The output of the current sensor 18 through the threshold device 19 is connected to the key input 20. The key output shunts a portion of the second resistor 21 installed between the common terminal and the combined inverting inputs of the comparators 14 and 15.

The Converter operates as follows.

The pulse former 1 provides, at its outputs, two para-phase square-wave signals with a duty cycle of 2 (Fig. 2, charts 22 and 23). At the output of the first element And 2, control pulses are generated by the first transistor 4 (Fig. 2, diagram 24). Moreover, the moment of locking the transistor coincides with the front of the pulse of the pulse shaper, and the moment of unlocking the transistor is delayed relative to the pulse front of the pulse shaper. Voltage diagram 25 at the collector of the first transistor 4 is shown in FIG. 2. Diagrams 24 and 25 (Fig. 2) are shown without taking into account the time of dissipation of minority carriers and the recovery time of the diodes of rectifier 16, since this does not affect the quality of the processes occurring. On the second element And 3 and on the second transistor 5, the diagrams for the voltage are similar to that of the 4 curse, but shifted by 180 relative to the diagrams 24 and 25 (Fig. 2).

The unlocking of the first transistor 4 occurs in the presence of a logic level of 1 1 units on nf.ix (; i.e. the first element I 2, the power factor ::. Hg is at

there are two logical units at the entrance. The level of the logical unit at the comparator output appears if the signal at the non-inverting input exceeds the signal at the inverting input The voltage plots at the input of the first comparator 14 are shown in diagram 26 (Fig. 2). On the inverting input of both comparators 14 and 15, a threshold voltage is applied through the voltage divider on the first 12 and second 13 {JSistors, filtering the capacitor

8 and push pull rectifier on ground

9 and the second 11 diodes, which is proportional to the double value of the input voltage. The non-inverting input of the first comparator 14 supplies the measured voltage from the collector of the second transistor 5 through the second voltage divider 7, and the non-inverting input of the second comparator 15 supplies the measured voltage from the collector of the first transistor 4 through the first voltage divider 6 . Thus, the switching time of the comparators is determined by the nature of the processes at the collectors of the transistor of the voltage converter.

Consider the stress plot

the collector of the first transistor shown in diagram 25 (Fig. 2). At stage I, the first transistor is open, and the second is closed and energy is transferred from the input to the load. At stage II, both transistors closed and closed the diodes of the output voltage of the transistor, which disconnect the load and the capacitive filter from the secondary winding of the transformer. A high-voltage transformer is characterized by a large value of the capacity of the secondary winding, reduced to the primary winding. At this stage, the recharge of the secondary winding capacity of the transformer by its magnetizing current occurs. At step III, the second transistor is opened and the capacitance of the transformer secondary winding is charged, which is disconnected from the output-Hbw load by the rectifier, as it has a lower voltage than the output filter capacitance. At stage IV, the second transistor is open, and the first is closed and the power from the input is transferred to the load. The stages of work V and VI correspond to the stages of work P and ni. Further, all steps are repeated. The plot of the current through the collectors of the first and second transistors is shown in diagram 27 (Fig. 2).

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The optimal form of the current through the transistors, which allows to obtain the maximum efficiency value with the minimum ripple of the output voltage, is achieved if the transistor is turned on with a voltage on it (0.4-0.8), and the duration of the pause in the current is (5 -15)% of the duration of the period. This transistor switching mode is set at nominal load conditions. At the same time, the threshold level of the threshold device 19 is selected so that, at a nominal input current through the current sensor 18, the switch 20 is open and the part of the second resistor 13 is shorted. The first 12 and second 13 resistors expose the required level of switching transistors. The voltage plots for this mode on the first transistor and the first comparator are shown in diagrams 25 and 26 (Fig. 2), respectively. On the second transistor and the second comparator, the diagrams are similar and shifted by 180.

When the load current changes, the output voltage changes. The output characteristic of the voltage converter is shown in FIG. 4 (dashed line for a known transducer, solid line for the proposed one). An increase in the output voltage at low load currents is due to the fact that the selected switching mode of the converter's transistors ensures the connection of a capacitive filter through the rectifier to the secondary winding under non-zero initial conditions of the current through the transformer secondary winding. In diagram 27 (Fig. 2), the current through the transistors in the III and VI stages is the current through the inductance of the dissipation of the secondary winding of the transformer. The current through the transistor at the end of the III and VI stages is the initial value of the charging current of the capacitive filter. Therefore, the dissipation inductance of the secondary winding of the transformer is the source of the charge current of the capacitive filter. The speed of discharge of the capacitive filter at low load currents is small. Consequently, the output voltage of the voltage converter is the lower, the lower the charge rate of the capacitive filter, i.e. Negative at low load currents 1 initial

value of the charge current of the capacitive filter.

In the proposed converter, when the load current decreases, the signal at the output of the current sensor decreases, which leads to the triggering of the threshold device and locking the key. Using a part of the resistor 13, the switching time of the transistors is set in such a way that the switching on of the transistor takes place at a practically zero voltage across it. The voltage plots on the first transistor and the first comparator are shown in diagrams 28 and 29 (Fig. 3), respectively. In this mode, the duration of the III and VI stages is reduced to zero by increasing the duration of the II and V stages. The current through the transistors of the converter in this mode is shown in diagram 30 (Fig. 3). Its value at the beginning of stages I and IV is much less than at nominal load and is approximately equal to the no-load current of the transformer at a given time. Due to the fact that when the switching mode of the transistors of the voltage converter is changed, the charge current of the capacitive filter decreases, the output voltage decreases. The solid line (Fig. 4) shows the output characteristic of the proposed converter

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l The moment of changing the switching mode of the transistors of the converter is chosen, as a rule, at a current of (0.1-0.2) 1.0.

Thus, the proposed high-voltage high-frequency voltage converter has an improved output characteristic due to a decrease in the output voltage at low load currents.

Claims (1)

Invention Formula High-voltage high-frequency voltage driver for aut. St. No. 1153384, characterized in that, in order to improve the quality of the output voltage by reducing the instability of the output voltage in a wide range of load current, a threshold element, a key and a current sensor connected between the input terminal and the outlet from the midpoint of the primary output winding are introduced transformer, the output of the current sensor through the threshold element is connected to the control input of the key, the output of which bypasses a part of the resistor installed between the common terminal and the combined inverting inputs of the computer aratorov. 23 gb (out thirty Fig 3 GM 1n