JPS5940542A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS5940542A
JPS5940542A JP57149274A JP14927482A JPS5940542A JP S5940542 A JPS5940542 A JP S5940542A JP 57149274 A JP57149274 A JP 57149274A JP 14927482 A JP14927482 A JP 14927482A JP S5940542 A JPS5940542 A JP S5940542A
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
tape
pellets
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57149274A
Other languages
English (en)
Inventor
Toru Abe
亨 阿部
Shigetaka Kawai
川井　重威
Eiichi Murata
栄一 村田
Satoshi Iida
智 飯田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Eastern Japan Semiconductor Inc
Hitachi Iruma Electronic Co Ltd
Original Assignee
Hitachi Tohbu Semiconductor Ltd
Hitachi Iruma Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tohbu Semiconductor Ltd, Hitachi Iruma Electronic Co Ltd filed Critical Hitachi Tohbu Semiconductor Ltd
Priority to JP57149274A priority Critical patent/JPS5940542A/ja
Publication of JPS5940542A publication Critical patent/JPS5940542A/ja
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。半導体装１α
、たとえばＩＣチップあるいはトランジスタのマルチ笑
装方法として、従来、第１図（ａ）〜（（１）および第
２図（ａ）〜韓）に示す方法が採られている。
この実装方法は、半導体シリコンウニ・・−１ｔダイヤ
そンドカッターにて切溝８？Ｉ？入れた１表、粘着テー
プ２に貼シ合わせる。次に半導体シリコンウニ・・−１
上にゴムローラ？かけて分割して治具に粘着テープ２と
ともに固定する。次に固Ｗざｎた粘着テープ２の下から
、ニールビビン５ｒ突き上げて、シリコンウニ・・−１
より１個の半ｚ、ｒ、Ｌ捧ヘレット４を突起させて真空
吸溜治−Ｊ４３（コレットと称する）Ｖごて半導体ベレ
ット４ヶ吸い上げる。仄に吸い上げられた半導体ベレッ
ト４に、ハイブリッドエＣ（＃成果積回路）用基板６上
の所Ｗの位置に、Ａｕ−８Ｌ共晶（あるいに、半田、　
Ａ　ｇペーストなど）などによりＩ　１１Ｉｉ　１１１
ａ＋、確度良く接続ケ行なう。
しかし、この実装方法であると、尚精度ケ安求さｎる半
導体ベレット４のハイブリッドエＣ用基板６への俤続に
おいて、シリコンウェハー１から＋７）　半４　体ベレ
シト４盆取り出す時のニードルビン５による粘着テープ
２の伸縮、半導体ベレット４の突き上は角度、真空コレ
ット３お工ひ半導体ベレット４上の異物耐着等、精度的
にも９哩的にも難しいものとなっている。しかも高精度
要求のため１個づつ処理しなければならずマルチ処１里
が困難であった。この為、作業性が低く、生産コストも
高くなる欠点がある。
したがって、本発明の目的にベレットのマルチ実装が多
数個同時にかつ容易に、晶ｉ度Ｖこ行なえる生産コスト
の安価な半導体装置の製造方法？提供することにある。
このような目的を過酸するために本発明は、平板治具表
面上の任意の付置に形成された粘着性ｒ有する粘潰物層
により、半導体シリコンウニ・・−から半導体ベレット
？少なくとも１個以上同時に取り出した後、上記半纏体
ベレットケＨ［望の基体（回路基板）上に少なくとも１
ｉｌｉ！ｉｆ以上、同時に１４度よく接続することｔ特
徴とする半導体装置の製造方法である。以下、図面ｒ用
いて本発明ケ具体的に説明する。
第３図（ａ）〜（ｅ）および＠５図（ａ）はそれぞｎ本
発明による半導体装置の製造工程の１実施例ケ示す斜視
図および平面図である。１ず、第３図匹）訃よひ第４図
（ａ）に示すように、半導体シリコンウェハー１ヶ粘着
テープ９に貼υ合わゼーた俊、上６己粘宥テープ９の伸
縮防止用の粘鳥テーノ′ＩＯを貼り合わせる。次にダイ
ヤモンドカッターＶこて半導体シリコンウェハー１の表
面から粘層テーノ９の半分１での深さまで切＃４８ケ入
れ、半導体シリコンウェハー１を完全に切断、分割する
。仄に第５図（ａ）（ｂ）に示したように表面にスクリ
ーン印刷めるいはボッティングによジ半導体シリコーン
ウェハ１内の取シ出したい位置の半導体ベレット４に対
応する位Ｗに粘着性を有する粘着、ＷＪ層１４（ホット
メルト系の粘着剤など）が板層きれた平板出兵１１（ス
テンレス板など）ｒ第３図（ｂ）および第４図（ｂ）に
示すように完全切断光子したシリコンウェハー１に対し
て治具あるいは位置合せ装置により粘屑物層１４と取り
出したい半導体ベレット４の位置が合うように貼シ合わ
せる。仄に基板１１ｉシリコンウエハー１より取９上げ
ると第３図（ｃ）および第４図（０）に示す如く、取り
出しだい位置の半導体ベレット４は粘宥′１勿１−１４
にＬり多１１回、同時に精度よく基板１１上に取り出は
れる。次に、第３図（ｄ）および第４図釦に示す如く、
前記の基板ｌｌ上に取シ出された半導体ベレット４ケバ
イブリッドＩＣ用基板１２上に半導体ベレット４と同位
鰺に形成された半田１３（あるいｔａ、Ａ　ｇペースト
）上に位置ケ合わせし加熱することにより、第３図（θ
）および第４図（ｅ）に示す如く半導体ベレット４にハ
イブリットエＣ用基板１２上に多砂個同時に精度よく接
続勿完成式ぜる。
ル上、本発明によｎば、従来の個別処理によるシリコン
ウェハー１からの半導体ベレット４の取り出しおよび取
り出きれた半導体ベレット４の基体６への接続が、安価
な粘着物Ｍｌ　４に形成した基体１１によジ多数同時（
マルチ処理）に処理できることにより、従来の如き、個
別処理による生理コストの高い、＃Ｅ顆性も惑い実装作
業は不要となり、マルチ処理による一賀した作業による
生理コスト低減が可能となる。また従来の如き、釉層′
テープの伸縮による位ｒｔ、　梢反不艮、ニードルビン
。
Ｘ空コＬ’ッｈ［よる牛４体ベレットのカケ不良等の恐
れはなく、歩留の向上ヲ因−リ、しかも高価格の装置を
使用することなく容易に安価な装置、治具で実装が司能
となり設備投Ｉもはるかに安くすることかできる。
箇だ、本発明は、多数の半導体ベレッＨ−同時、に処理
できることにより、第６図（ａ）（ＬＩＪ　＆こ示す半
導体装ｔｘｔ、（一般にフリップチップと呼ぶ）紫製造
する場合に効果が大となる。第７は１（ａ）〜（０）に
上記フリップチップタイプ半導体装値の製造工程のｌ実
施し１１を示す斜視図である。本方式に、第７図（ａ）
に示す如く小（Ｍ号トランジスタの半導体ベレン）１５
を本発明によるマルチ実装方式にて導電性基体”１８上
に精度よく多数（１０００〜２００　Ｕｉ固）接続した
後、前記、半害体ベレン）１５および導電性基体１８上
にポリイミド樹脂溶緻ヲコーティングし第７図（ｂ）に
示す如く絶縁物Ｌｍ　ｌ　６　ｉ形成し、然る後、’Ｍ
ＪＢ己杷緑吻層１６紮ホトエツチングにより部分的に除
去して開口２１を形成する。（開口は、工ばツタ、ベー
ス、コレクタ用の成極取り出し口？示す。９次に一ロ２
１ケ介して半祷体ベレット１５０送検ケとジだ丁ために
、配線下地金１屯（ＴｉＯｕ−ＴＬ）１９に蒸着にて形
ＭＬ　Ｌ、最終的に外部リードと接続させるための半田
電極ｊｌ−蒸着あるいは、ディップにより形成する。仄
にこれ？切断、分離して第６図（ａＪに示す如き半導体
装置を完成する。本半導体装置の叩く、多数の半導体ペ
レツｈ２基体上に接続する場合、従来の叩き個別処理に
よる接続でば、生産コストが上がり作業性も非常に悪い
ものとなる。これに対し、本発明による実装方式全適用
すれば、多くの半導体ベレットが同時に精度よく接続す
ることか可能となり作業性は非常によくなり、大幅な生
産コストの低−減か図ｎ１芥易にかつ安価な半導体装置
を生産することかできる。
なお、本発明に、前記実施例に限定されず、トランジス
タ以外の半導体装置、たとえはＩＣ（集積回路）、ＬＳ
Ｉ（大規模集積回路）にも適用できる。！ｉた基体は、
一般絶縁体基板、導体基板。
千尋体素子用リードフレームあるいｈ　　ｆ４にパッケ
ージであってもよい。
以上のように、本発明によれは実装が多曲個同時にかつ
容易に、高精度に竹なえる生産コストの安価な半導体装
置の製造方法ケ提供することができる。
【図面の簡単な説明】
第１図（ａ）〜（（１）および第２図（ａ）〜（＠）に
それぞれ従来の千尋体べｌノットの実装方法勿示す斜視
図および断面図である。 第３図（ａ）〜はうおよび第４図（ａ）〜（ｆ３）に、
それぞｎ本発明の一実施例による半導体装ＩＨの製造工
程ケ示す斜視図および断１図である。 第５図（ａ）は本づへ明の半導体装置の製造工程で使用
される平板治具の平面図、 第５図＜ｂ）は第５因（ａ）のＡ−Ａ’切断断面図であ
る。 第６図（ａＪ　Ｕ本発明に係るフリップチップタイプ半
導体装置の斜視図、 第６図（ｔｌＪに第６図←）のＢ−Ｂ’切断断面図での
る。 第７図（ａ）〜（Ｃ）は本発明の他の実施例でるり、上
記フリップチップタイプ半導体装置の製造工程ｒボす斜
視図である、。 ｌ・・・千尋体シリコンウェハー、２・・・粘着テープ
、３・・・真空コレット、４・・・半導体ベレット、５
・・・ニードルピン、６・・・ハイブリッドｌＣ用基板
、７・・・Ａｕ−８ｉ共晶（半田あるいはＡｇペースト
）、８・・・ダイシングの切溝、９・・・粘着テープ、
ＩＯ・・・伸縮防止テープ、１１・・・基板、１２・・
・・＼イブリッドＩＣ用基板、１３・・・半田あるいは
Ａｇペースト、１４・・・粘Ｎ物層、１５・・・トラン
ジスタベレット、１６・・・絶縁物層、１８・・・導ｉ
ｉｉ性基板、１９・・・蒸治配線、２０・・・半田ある
いはＡｇペースト。 第　　１　　図 ｆ 第　　２　図 第　　３　　図 １９ 第　　５　図 （θ巳）　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　と、ビ＝、ン第　　６　　図 第　　７　図 １９３−

Claims (1)

    【特許請求の範囲】
  1. １、等間隔で切断、分割された十停体シリコンウェハよ
    ジ半婆体ベレット？取り出し、該半導体ベレット２基体
    表面に精度よ〈取り付りしＭｉ豆する半導体装置の！！
    １ａ方法において、前記半導体シリコンウェハーからの
    前記半導体ベレットの取ジ出しｔ１平根治真の一表面上
    の任意の位置に形成でれた粘着性を有する粘着物層によ
    シ少なくとも１個以上同時に取り出した後、前記の治具
    表面上に取り出式ｎ７ｃ前配半導体ベレットｒ１所望の
    基体上に少なくとも１個以上、同時に精度よく取り付け
    ること？特徴とする半導体装置の製造方法。
JP57149274A 1982-08-30 1982-08-30 半導体装置の製造方法 Pending JPS5940542A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57149274A JPS5940542A (ja) 1982-08-30 1982-08-30 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57149274A JPS5940542A (ja) 1982-08-30 1982-08-30 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS5940542A true JPS5940542A (ja) 1984-03-06

Family

ID=15471630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57149274A Pending JPS5940542A (ja) 1982-08-30 1982-08-30 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5940542A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1526574A2 (en) * 2003-10-22 2005-04-27 Oki Data Corporation Semiconductor device, light emitting diode print head and image-forming apparatus using same, and method of manufacturing semiconductor device
WO2012152672A3 (fr) * 2011-05-06 2013-05-30 3D Plus Procede de fabrication de plaques reconstituees avec maintien des puces pendant leur encapsulation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1526574A2 (en) * 2003-10-22 2005-04-27 Oki Data Corporation Semiconductor device, light emitting diode print head and image-forming apparatus using same, and method of manufacturing semiconductor device
EP1526574A3 (en) * 2003-10-22 2011-04-27 Oki Data Corporation Semiconductor device, light emitting diode print head and image-forming apparatus using same, and method of manufacturing semiconductor device
US8343848B2 (en) 2003-10-22 2013-01-01 Oki Data Corporation Semiconductor device, LED print head and image-forming apparatus using same, and method of manufacturing semiconductor device
WO2012152672A3 (fr) * 2011-05-06 2013-05-30 3D Plus Procede de fabrication de plaques reconstituees avec maintien des puces pendant leur encapsulation

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