JPS594034A - Wire bonding - Google Patents

Wire bonding

Info

Publication number
JPS594034A
JPS594034A JP57111680A JP11168082A JPS594034A JP S594034 A JPS594034 A JP S594034A JP 57111680 A JP57111680 A JP 57111680A JP 11168082 A JP11168082 A JP 11168082A JP S594034 A JPS594034 A JP S594034A
Authority
JP
Japan
Prior art keywords
bonding
wire
chip
lower plate
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57111680A
Other languages
Japanese (ja)
Inventor
Kenichi Yamamoto
憲一 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57111680A priority Critical patent/JPS594034A/en
Publication of JPS594034A publication Critical patent/JPS594034A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To drastically reduce a failure rate caused by bonding, by providing an electrically insulating film to the wire extended in case of extending a bonding wire between a bonding pad and a lead of semiconductor chip. CONSTITUTION:After mounting an LSI chip 4 on an LSI chip mount section 2, a bonding wire 5 is extended by bonding between a bonding pad provided at the upper surface of the chip and the inside part of lead 3. A lead frame 1 is fixed to the specified area of a lower plate 16 of a mask jig 6 using a perforation 1b provided to the side end of a tape 1a. At this time, a mount part 2 is aligned with an aperture 16b of the lower plate 16 in conjunction with a positioning protrusion 16a at the upper surface of the lower plate 16. Thereafter, a chip 4 is mounted to the mask jig so that the mount part 2 is placed in the lower side, an electrically insulated resin is sprayed thereon together with a solvent in order to execute insulating processing to a wire 5.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体製造工程におけるワイヤボンディング
工程の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a wire bonding process in a semiconductor manufacturing process.

〔発明の背景技術とその問題点〕[Background technology of the invention and its problems]

近頃、大規模集積回路（ＬＳＩ）の進歩によシその信号
の入出力端子の数が急増するのに伴なって、半導体チッ
プとリードとの間に架張されるボンディングワイヤが顕
著に近接する傾向にある。Recently, as the number of signal input/output terminals has rapidly increased due to advances in large-scale integrated circuits (LSI), bonding wires strung between semiconductor chips and leads have become noticeably closer together. There is a tendency.

このため、特しこボンディング工程後に施される樹脂モ
ーヤド工程でモーｔレド樹脂注入時にボンディングワイ
ヤに変形を生じ、隣接のボンディングワイヤ間、または
ボンディングワイヤがチップに下葉 所望に接触するなどの問題があった。この対冑として絶
縁被すされたボンディングワイヤを用いることが考えら
れるが、現状の高速全旨とするボンディング方式ではボ
ンディング部外の絶縁被膜全除去するのに著しい障害が
あｐ不可能である。For this reason, in the resin molding process performed after the special bonding process, deformation occurs in the bonding wire when resin is injected, causing problems such as contact between adjacent bonding wires or the bonding wire coming into contact with the chip in the lower layer. was there. As a countermeasure to this problem, it is possible to use an insulated bonding wire, but with the current high-speed bonding method, it is difficult to completely remove the insulating coating outside the bonding area.

〔発明の目的〕[Purpose of the invention]

この発明はＬ記従来の問題点Ｖｃ５ｉＩｉみてなされた
もので、ボンディングワイヤのイ気絶縁金はかるように
改良されたワイヤボンディング方法を提供するものであ
る。This invention has been made in view of the problems of the prior art described in L. It is an object of the present invention to provide a wire bonding method that is improved in that the gold insulation of the bonding wire is improved.

〔発明の概要〕[Summary of the invention]

この発明は半導体チップのポンディングパッドとリード
間にボンディングワイヤを架張するワイヤボンディング
工程と、前記架張されたボンディングワイヤに暖気絶縁
被膜を被覆する工程とを具備したワイヤボンディング方
法である。The present invention is a wire bonding method comprising a wire bonding step of stretching a bonding wire between a bonding pad and a lead of a semiconductor chip, and a step of coating the stretched bonding wire with a warm insulation coating.

〔発明の実施例〕[Embodiments of the invention]

次にこの発明を１実施例につき図面を参照して詳細に説
明する。Next, one embodiment of the present invention will be explained in detail with reference to the drawings.

一例のＬ　Ｓ　Ｉの組立ＶＣあだυ第１図に一部を示す
リードフレーム（１）が用いられている。図の（２）。A lead frame (1), a part of which is shown in FIG. 1, is used in an example of an LSI assembly VC adapter. (2) in the diagram.

（２）・・・はＬ　Ｓ　Ｉチップマウント部（ｉＰ；　
ｉ図にはその１個が示される）でこれを取囲む多数のリ
ード（３）、（３）・・が設けられており、チップマウ
ント部にＬ・ＳＩチップ（４）をマウントシたのち、そ
のと面のポンディングパッド（４ａ）、（４ａ）・・・
（図示省略）とリード（３）、（３）・・・の内端部と
をボンディングワイヤ（５）、（５）・・・でボンディ
ングして架張させる。ついで第２図に示すようなマスク
治具（６）の下板ａωＬに、リードフレーム（１）をそ
の側端のバンド部（ｌａ）、（ｌａ）（８８１図）Ｋ設
けられた送り孔（ｔｂ）、（１ｂ）・・（第１１貨）に
よって定位取着する。丘記定位城着のために、下板＋ｔ
ｔｐのと面には位置決め用突起（１６ａ）。(2) ... is the LSI chip mount part (iP;
There are many leads (3), (3), etc. surrounding this (one of which is shown in Figure i), and after mounting the L/SI chip (4) on the chip mount section, Pounding pads (4a), (4a)...
(not shown) and the inner ends of the leads (3), (3), . . . are bonded and stretched using bonding wires (5), (5), . Next, the lead frame (1) is inserted into the lower plate aωL of the mask jig (6) as shown in FIG. tb), (1b)... (11th coin) to fix the position. Lower plate + t for positioning on the hill
A positioning protrusion (16a) is provided on the opposite side of tp.

（１６ａ）・・・が設けられており、これＶＣリードフ
レーム全定位取着したとぎ第３１２１に示！ようにＬＳ
Ｉチツ７−　マ’ｉ　ン）　部（２）カ下板（ＵａＯ開
孔（１６ｂ）　、　（１６ｂ）・・に位置合わせされる
。なお、ト記開孔はＬＳＩチップマウント部とこれを取
囲む多数のリードの各先端を露出できる大きさに形成さ
れている。さらに、マスク治具にはＪ：記下板に重ね合
わされる上板００がある。この七板弼には上記下板の位
置決め用突起（１６ａ）　、（１６ａ）・・・に押通さ
れて位置決めされる孔（２６ａ）、（２６ａ）を備え、
Ｌ記位置決め手段（位置決め用突起を孔に挿通させる）
によって取着されたとき、下板の開孔（１６ｂ）　、　
（１６ｂ）・・・に夫々対向させてと板の開孔（２６ｂ
）　、（２６ｂ）・・・が設けられている。上記上板の
開孔も下板の開孔とほぼ同じ大きさ、形状でよい。(16a)... is provided, and this is shown in No. 3121 when the VC lead frame is fully installed! Yoni LS
The part (2) is aligned with the lower plate (UaO hole (16b), (16b)...). The mask jig is formed in a size that can expose the tips of each of the many surrounding leads.Furthermore, the mask jig has an upper plate 00 that is superimposed on the lower plate J. Positioning protrusions (16a), (16a)... are provided with holes (26a), (26a) that are pushed through and positioned,
L positioning means (inserting the positioning protrusion into the hole)
When attached by the opening (16b) in the lower plate,
(16b)... and the openings in the plate (26b) facing each other.
), (26b)... are provided. The apertures in the upper plate may have substantially the same size and shape as the apertures in the lower plate.

蒸上のマスク治具にマウントの完了したり一ド７レーム
をチップマウント部が下向になるよう装着する。ついで
、Ｌ方から電気絶縁性樹脂を溶剤で溶解した溶液をスプ
レーする。ｋ、配電気絶縁性樹脂のスプレィ用溶液とし
て、−例のトレニース（商品名、東し製品）をキシレン
で１０倍に希釈したものが好適し、スプレーはスプレー
ガフ　Ｑｆｌ）　（＠３図）被コーテイング部材から２
０〜３０α離れて施して良好に達成された。叙りのスプ
レーコーテイング後にはボンディングキャリヤに収納し
、室温で乾燥させたのち窒素雰囲気のオープンでキユア
リングを施して強固な電気絶縁被膜被覆の施されたボン
ディングワイヤが得られる。Once mounted, attach the 7-frame frame to the vaporizer mask jig with the chip mount section facing downward. Next, a solution of an electrically insulating resin dissolved in a solvent is sprayed from the L side. k, Electrical distribution As a solution for spraying insulating resin, it is preferable to dilute the example Trenise (trade name, Toshi product) 10 times with xylene. 2 from parts
Good results were obtained by applying the distances of 0 to 30 α. After the above spray coating, the wire is stored in a bonding carrier, dried at room temperature, and then cured in an open nitrogen atmosphere to obtain a bonding wire coated with a strong electrically insulating film.

なお、叙とのスプレーコーティングはチップマウント部
の下面（ＬＳＩのチップがマウントされた面の反対側の
面）よシ施す方法を例示したが、これに限られるもので
ない。Although the spray coating described above is applied to the lower surface of the chip mounting portion (the surface opposite to the surface on which the LSI chip is mounted), the present invention is not limited to this method.

〔発明の効果〕〔Effect of the invention〕

この発明によればボンディングに係る不良発生率が従来
約２チであったの全０．１−以下に低減することができ
た。また、ワイヤボンディング工程後から外囲器形成の
だめの樹脂モールドを終了するまでの工程における加工
で、ボンディングワイヤの変形防止のための大きな労力
が不要゛とな９、製品の品質信頼性の向Ｊ：に￥を与す
る。さらに、今後多ピンのフラットノくツケージ品種か
増大する傾向にあるので、この発明はますま”す有効に
なるものと見られる。According to this invention, the defectiveness rate associated with bonding can be reduced from the conventional rate of about 2 to less than 0.1. In addition, it eliminates the need for large amounts of labor to prevent deformation of the bonding wire during the process from the wire bonding process to the end of the resin molding process for forming the envelope.9 This also improves product quality and reliability. : Give ¥ to. Furthermore, since there is a tendency for the number of flat-head cages with multiple pins to increase in the future, this invention is expected to become even more effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はリードフレームの一部の正面図、第２図はこの
発明の１実施例に用いられるマスク治具を説明するため
の斜視図、第３図は１実施例を説明するためのスプレー
コーティングを示す断面図である。 １　　　　　　リードフレーム ２　　　　　　ＬＳＩチッグマウント図３　　　　　　
リードフレームのリード４　　　　　　ＬＳＩチップ ５　　　　　ボンディングワイヤ 旦　　　　　マスク治具 １０　　　　　　スプレーガン １６　　　　　　マスク治具の下板 １６ａ（下板の）位置決め用突起 １６ｂ　　　　　下板の開孔 ２６　　　　　　マスク治具のＬ板 ２６ａ　　　　　ｋ、板の位置決めされる孔２６ｂ　　
　　　ｈ板の開孔 代理人　弁理士　　井　と　−男 第１図 第　　２　　図 第　　３　　図 ｔ（、、−ｔｒFig. 1 is a front view of a part of the lead frame, Fig. 2 is a perspective view for explaining a mask jig used in one embodiment of the present invention, and Fig. 3 is a sprayer for explaining one embodiment. FIG. 3 is a cross-sectional view showing the coating. 1 Lead frame 2 LSI chip mount diagram 3
Lead frame lead 4 LSI chip 5 Bonding wire mask mask jig 10 Spray gun 16 Mask jig lower plate 16a (lower plate) positioning protrusion 16b Lower plate opening 26 Mask jig L plate 26a k, plate hole 26b to be positioned
H board hole opening agent Patent attorney I and -man Figure 1 Figure 2 Figure 3 T (,, -tr

Claims (1)

【特許請求の範囲】[Claims] 半導体チップのポンディングパッドとリード間にボンデ
ィングワイヤを架張するワイヤボンディング工程と、前
記架張されたボンディングワイヤＶｃ［気絶縁被膜を被
覆する工程とを具備したワイヤボンディング方法。A wire bonding method comprising a wire bonding step of stretching a bonding wire between a bonding pad and a lead of a semiconductor chip, and a step of coating the stretched bonding wire Vc [with a gas insulating film.
JP57111680A 1982-06-30 1982-06-30 Wire bonding Pending JPS594034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57111680A JPS594034A (en) 1982-06-30 1982-06-30 Wire bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57111680A JPS594034A (en) 1982-06-30 1982-06-30 Wire bonding

Publications (1)

Publication Number Publication Date
JPS594034A true JPS594034A (en) 1984-01-10

Family

ID=14567453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57111680A Pending JPS594034A (en) 1982-06-30 1982-06-30 Wire bonding

Country Status (1)

Country Link
JP (1) JPS594034A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288330A (en) * 1995-04-20 1996-11-01 Nec Corp Method for preventing short circuit between wire and lead frame
KR20010111438A (en) * 2000-06-10 2001-12-19 마이클 디. 오브라이언 method for detecting orientation of lead frame and heat block clamp for using thereof
CN113808965A (en) * 2021-09-23 2021-12-17 华东光电集成器件研究所 High-impact-resistance lead assembling method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288330A (en) * 1995-04-20 1996-11-01 Nec Corp Method for preventing short circuit between wire and lead frame
KR20010111438A (en) * 2000-06-10 2001-12-19 마이클 디. 오브라이언 method for detecting orientation of lead frame and heat block clamp for using thereof
CN113808965A (en) * 2021-09-23 2021-12-17 华东光电集成器件研究所 High-impact-resistance lead assembling method

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