JPS5938731Y2 - phase detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase detector, and particularly to a phase detector suitable for use in a method for measuring capacitance and loss coefficient of a capacitor, which has already been proposed by the applicant.

As a method for measuring the capacitance and loss coefficient of a capacitor, the present applicant proposed a method in Japanese Patent Application No. 1129-1983 (Japanese Patent Publication No. 40500-1982).

This is related to a capacitance measurement method in which the capacitance and loss coefficient of a capacitor are determined simultaneously.This new capacitance measurement method is based on the series equivalent method, and the configuration of the measuring instrument is Although it is quite simple, it has the advantage of being quite accurate and automatable.

Generally, when measuring the capacitance and loss factor of a capacitor, standards specify that a 120 Hz AC signal should be used.

Therefore, the above-mentioned Japanese Patent Application No. 1129-1983 (Patent Application No. 1129-1983)
0500) also uses 120 Hz.

As mentioned later, the above-mentioned Japanese Patent Application No. 1129-1983
3-40500) is a measurement method using a measurement reference signal (12
The in-phase component of 0 Hz and the 7-phase components are phase-detected, and the in-phase signal among these signals indicates the magnitude of the capacitance and serves as a feedback signal for the measurement system.

In this case, since the phase detection described above is performed by the sampling method, the measurement system is stabilized with 120 sampling signals per second, and measurement results are obtained.

Usually, the measurement results are obtained within about 1 second.

However, on a mass production line, the time required to obtain a measurement result of 1 second or more often becomes a hindrance to improving productivity, and there is a desire to further shorten this time.

Therefore, it is an object of the present invention to propose a measuring method that allows capacitance and loss factor measurements to be carried out in the conventional V2 time, and in particular to propose a phase detector implementing the measuring method.

In accordance with the above-mentioned purpose, the present invention performs synchronous detection on the positive polarity (or negative polarity) signal portion of the AC signal to be phase-detected, and synchronously detects the bipolar signal portion of the AC signal. It is characterized by:

The present invention will be explained below according to the drawings.

First, before explaining the present invention, a general method and a measuring method according to the above-mentioned Japanese Patent Application No. 49-1129 (Japanese Patent Publication No. 53-40500) will be described.

The capacitance and loss of a capacitor can be measured using, for example, a bridge circuit shown in FIG.

That is, when the output of the oscillator O8C with the frequency f is applied to the bridge circuit and the balanced state is detected by the detector A, the capacitance Cx and the equivalent resistance Rx of the capacitor to be measured can be determined as follows.

Also known are transformer bridge circuits shown in FIGS. 2 and 3.

In Figure 2, In Figure 3, becomes.

Note x is the loss coefficient of the capacitor to be measured, and Ds is the standard loss coefficient.

Instead of the manually balanced bridge circuit as described above, measuring instruments have been developed that can automate the balancing of the bridge circuit and obtain data in digital quantities for automated measurement and data collection.

For example, a measuring instrument as shown in FIG. 4 is known which is based on the transformer bridge circuit described above.

In the figure, O20 is an oscillator, 1, 4, 5.6 are operational amplifiers, 2, 3 are multipliers, 7, 8 are phase detectors, 9°10 is an integrator, and phase detector 8 9(lf(
Different f-phase signals are added.

Such a measuring device synchronously separates the unbalanced current or voltage of the bridge circuit into an in-phase component and a π/2 phase component with respect to the oscillator output, and uses a reference element so that the separated outputs become zero. It adjusts the flowing current or voltage, and obtains the capacitance Cx of the capacitor to be measured based on the output of the integrator 9, and the loss coefficient based on the output of the integrator 10.

There are a series equivalent method and a parallel equivalent method to measure the loss of a capacitor, and the series equivalent method is generally used.

Figure 5 shows the relationship between current and voltage in the series equivalent method and the parallel equivalent method, and Figure 5a.

b is the case when considering the voltage as a reference, and when v=Vsinwt, it becomes as follows.C and d in FIG.

Since the transformer bridge circuit is considered based on voltage, (
1) and (2).

In this case, the series equivalent method is essentially impossible if the current it is separated into an in-phase component and a π/2 phase component, since the coefficient is in the denominator and the resistance component and capacitance component influence each other. It is.

Therefore, the parallel equivalent method will be adopted.

To convert the unknown capacitance Cxp into a series equivalent value Cxs, the loss coefficient is calculated as follows.

The above-mentioned patent application No. 1129/1983
Figure 6 shows an example of the floc structure of No.

In this figure, 11 is a multiplier, 12, 13° and 14 are operational amplifiers, 15 and 16 are subtracters, 17° and 18 are phase detectors, 19 and 20 are first and second integrators, and R3 to P6 are A resistor, C8 is a reference capacitor, O20 is an oscillator, a is a signal in phase with the output of the oscillator O8C, and b is a signal with a 90° phase difference.

The output voltage vsinwt of the oscillator O8C becomes Kv sin wt by the multiplier 11, the output VX of the first operational amplifier 13 becomes, and the output V8 of the second operational amplifier 14 becomes.

Therefore, the subtracter 15 obtains an output of (vX v 3 ), which is detected by the phase detector 17 by coswt, integrated by the first integrator 19, and fed back to the multiplier 11.

At this time, the steady value is such that the input to the integrator 190 is O, and therefore the π/2 phase component of the output of the subtractor 15 is zero.

The output VX of the operational amplifier 13 is also applied to a subtracter 16, and the difference between it and the output of the second integrator 20 is determined.
is detected and integrated in the second integrator 20.

Since the steady-state value at this time is the input of the integrator 20 being O, and since it is CX5ooK1 as shown in the α0 formula, if the voltage V is constant, the loss coefficient DX is D X= w-Cxs wK2 ”-46).

Therefore, by selecting appropriate values for the resistors R3yR4+R5+p6'i, CX5=1 v D X- can be set to 2, and measurement is performed by the series equivalent method.

As can be seen from formulas (15) and (16), the loss coefficient DX must be measured with the voltage V constant, and generally it is easy to keep this voltage V constant within an error range of 0.05%. be.

Furthermore, in a double-integrating digital voltmeter, if the reference voltage is v8 and the input voltage is vX, the measured value
=<, so 2 is set to the output as the input voltage V
In addition, the reference voltage v8 may be a voltage proportional to the voltage V, and digital display can be performed so that fluctuations in the voltage V can be ignored.

Alternatively, this digital quantity can be input to a processing device such as a data recorder.

Thus, the above-mentioned Japanese Patent Application No. 1129-1983
No. 40500) can directly measure capacitance and loss coefficient using the series equivalent method, and the two expensive multipliers shown in Figure 4 are replaced by one in Figure 6. This has the advantage of being an economical configuration.

However, this patent application No. 1129-1983
40500), it takes about 1 second to obtain a measurement result, and it is difficult to shorten this time.

Therefore, the present invention focuses on the phase detectors 17 and 18 among the components shown in FIG. 6, and attempts to shorten the structure.

These phase detectors 17 and 18 have the same configuration except that they perform synchronous detection using different signals a and b and input different phase detected signals, so the following explanation will be given. will be described using the phase detector 17 as an example.

Conventionally, the configuration of the phase detector 17 used in the circuit of FIG. 6 is as shown in the block of FIG. 7A.

To explain this with reference to the waveform diagram in FIG. 7B,
The input Si in the figure is the difference signal of the equation (7) button and equation (8) above, and can be expressed simply as S i = A sin wt + B cos wt (
A w B is a constant).

In other words, Si is v'\” + B25in (wt+α
) (where tanα=α).

This is shown in FIG. 7B (1).

In the measurement system shown in FIG. 6, Si is a signal that gradually attenuates due to feedback, so the amplitude becomes smaller with time.

Since this signal S i k,coswt component is subjected to synchronous detection and this is performed by amplification, the switch 71f is turned on for each phase of the reference signal.

The reference signal is the same as the output of oscillator O8C in Fig. 6,
This is shown in (1) of FIG. 7B.

Further, the sample signal for synchronous detection is shown in FIG. 7B (3).

The switch 71 turns on every 7 phases, and the signal S at that time
i is held in sample held capacitor 2,
Phase detection output S via a buffer amplifier 73 for blocking leakage current from the capacitor 72.

becomes. Therefore, S.

becomes the waveform of the dashed line shown in FIG. 7B (2).

As is clear from FIG. 7B, in the conventional phase detector, only one polarity of the phase-detected signal Si is synchronously detected, and the output So gradually settles to a stable point accordingly.

Since the reference signal O8C is 12 Hz, this synchronous detection speed corresponds to 120 times/second.

Therefore, in the present invention, in order to increase this to 240 times/second, synchronous detection is performed using both polarities of the detection signal Si.

In this way, the time during which the output So of the same level is fed back (for example, t in FIG. 7B (2)) is shortened, and the stable point is quickly reached.

This will be explained with reference to Example 1 and (2).

FIG. 8A is a block diagram showing Embodiment I=e of the present invention, and FIG. 8B is a waveform diagram showing key parts thereof.

In FIG. 8A, the constituent elements 71, 72, and 73 are the same as in FIG. 7A, and newly added switches 71',
Sample hold capacitor 72', buffer amplifier 7
3', an inverter 81 and an adder 82 are further added.

The inverter 81 is for inverting the level of the signal Si, and the waveform P1. Create P2...

Then, the switch 71' is turned on by the synchronous detection signal b' (see FIG. 8B (3)).

Note that the adder 82 combines the respective signals from the buffer amplifiers 73 and 73', and outputs S.

(See Figure 8B (2)). As is clear from FIG. 8B, the output S.

is switched to two stages during time t, and the feedback response in the measurement system is S as shown in FIG. 7B.

This is approximately twice as large as in the case of .

FIG. 9A is a block diagram showing the embodiment (■) of the present invention,
FIG. 9B is a waveform diagram for the main part thereof.

In FIG. 9A, the components 71, 72, 73 are
8A, except that a synchronous rectifier 91 is newly added.

This synchronous rectifier 91 includes an operational amplifier 92 and a switch 93, and the switch 93 is turned ON in synchronization with the synchronous signal B.
t or OFF (see Fig. 9B (2)), and the signal Si
A signal Si' is obtained by synchronously rectifying the signal (see FIG. 9B (3)).

The synchronously rectified signal Si' is sampled by turning on and off the switch 71, and a synchronous detection output S is obtained.

get. At this time, the timing for turning on and off the switch 71 is given by the synchronous detection signal B' (see FIG. 9B (4)).

As explained above, according to the present invention, the above-mentioned patent application No. 49-
When applied to No. 1129 (Japanese Patent Publication No. 53-40500), a phase detector capable of halving the measurement time is realized.

[Brief explanation of the drawing]

Figure 1 is a general bridge circuit, Figures 2 and 3 are transformer bridge circuits, Figure 4 is a block diagram of a conventional capacitance and loss factor measuring instrument, Figure 5 is the series equivalent of axd. An explanatory diagram of the method and parallel equivalent method, Figure 6 is a patent application filed in 1978-11.
29 (Special Publication No. 53-40500), Figure 7A is a block diagram showing the actual configuration of the phase detector (17, 18) in Figure 6, and Figure 7B is the main waveform of Figure 7A. figure,
FIG. 8A is a block diagram showing the first embodiment of the present invention, and FIG. 8B is a block diagram showing the first embodiment of the present invention.
9A is a block diagram showing the embodiment (2) of the present invention, and FIG. 9B is a waveform diagram of the main parts in FIG. 9A. In the figure, buttons 17 and 18 are phase detectors, buttons 7 and 18 are phase detectors, respectively.
1.71' is a switch, 72.72' is a sample hold capacitor, 81 is an inverter, 82 is an adder, 91
93 is a synchronous rectifier, 93 is a switch, O8C is an oscillator reference signal, and Si is a phase-detected input signal.

Claims (1)

[Scope of utility model registration request] Signal A sin w in phase with reference signal K sin wt
t, and B s different from the reference signal Ksinwt in 7 positions.
A phase detector for synchronously detecting a sin wt component or a cos wt acid component from a composite signal obtained by combining in wtl, comprising a polarity inverting means for selectively inverting the polarity of the composite signal to unify the polarity; It has a switch means that turns on and off in order to sample the composite signal whose polarity has been unified by the inverting means, and a sample hold means that is connected to the switch means and holds the sampled composite signal, wherein the switch A phase detector characterized in that the means is turned on and off at a constant cycle that is twice the cycle of the reference signal.