JPS5937797B2 - alarm sound generator - Google Patents

Description

[Detailed description of the invention] The present invention relates to an alarm sound generating device.

Conventional clocks that generate alarm sounds have a function of generating alarm sounds continuously and a function of generating alarm sounds at regular intervals, and are provided with set switches for activating both functions.

Further, when generating an alarm sound at regular intervals, for example, every few minutes, the indicator switch is mechanically closed every few minutes.

As a result, the structure becomes large and various problems arise due to wear and the like, which is not desirable.

Therefore, the present invention uses one switch mechanism to generate the alarm sound continuously or intermittently by gradually shortening the generation interval with a simple circuit configuration, and also to stop the alarm sound, thereby solving the above-mentioned drawbacks. It is intended to remove.

An embodiment of the present invention will be described below based on the drawings.

In FIG. 1, 1 is a crystal oscillator and 2 is a frequency divider, whose output terminals a, l) generate an alarm signal of several KHz and a signal of IHz, respectively.

3 is a drive device such as a motor, and the IHz from frequency divider 2 is
The display section 4 is driven in response to the signal.

5 is a clock circuit, and its output terminal Cl ci. e, f
, g have a period of 20' seconds, a period of 1 minute, a period of 2 minutes, respectively.
Tutee 1/2 pulses are generated at a period of 4 minutes and a period of 64 minutes.

2nd A shows the pulses generated at terminals c, d, e, and f, respectively.

Figures B, C, and D.

6, 7...18, 18a are gate circuits, and the output pulses of the gate circuits 7, 8 are shown in Figures 2E and 2F, respectively.

The gate circuits 7, 8, . . . 11 and the clock circuit 5 constitute a selection circuit.

19, 20... 23 is a flip-flop circuit, 24. 25° 26 is a differentiation circuit that differentiates the falling edge of a pulse, and is of a well-known mechanism consisting of an OR gate and an inverter, and its output is normally “’1”, the input is “1”
A narrow pulse of "0" is generated only when the pulse falls from "0" to "0".

27, 28 and 29 are differentiating circuits for differentiating the rising edge of the pulse, and 30 and 31 are inverters.

Differential circuit 24, 27, flip-flop circuit, 19, 2
0 and gate circuit 12 constitute a detection circuit, and flip-flop circuits 21, 22, 23 and gate circuits 13, 14, . . . 17 constitute a memory circuit.

32 is a transistor, and 33 is a speaker, which constitutes a sound generation device.

34 is a resistor, and 35 is a reference switch.

36 is a switch, and its detailed configuration is shown below.
3 and 4. FIG.

In FIG. 3, reference numeral 37 denotes a suppression knob, which is fixed to a shaft 38.

Reference numeral 39 is a cylindrical body, and the upper half and the lower half of the inner surface thereof have a stepped portion 39c of different thickness, and recesses 39 a and 39 b are formed in the thicker portion of the upper half.

A convex portion 38a formed on the shaft 38 is provided in the concave portions 39a and 39b.

38b was inserted.

40 is a magnet, and 41 is a reed switch, each of which is fixed to a fixing member (not shown).

The reed switch 41 constitutes the switch 36 in FIG.

The cylindrical body 39 is screwed to a fixed plate 42 as shown in FIG. 4, and one end of a spring 43 is fixed to the lower end of the inner surface thereof.

The other end of the spring 43 is fixed to the shaft 38.

Therefore, in the normal state, the shaft 38 is pushed upward by the spring 43, and in this state, the reed switch 41 shown in FIG. 3 is shielded by a shielding plate 44 fixed to the shaft 38, and is opened.

45 is the outer frame of the clock. Next, the operation will be explained.

First, in FIG. 1, it is assumed that flip-flop circuits 19 and 20 are set, and flip-flop circuits 21, 22 and 23 are reset.

Therefore, when the switch in FIG. 3 is in the normal state, the reed switch 41 is open, and the switch 36 in FIG. 1 is in the open state, the gate circuit 6 in FIG. The wake-up signal from terminal a passes through this and also passes through gate circuit 18 and is supplied to transistor 32 .

Therefore, when the guide switch 35 closes at the desired time,
A wake-up sound is generated from the speaker 33.

When the suppression knob 37 in FIG. 3 is pressed to temporarily stop the alarm sound, the shielding plate 44 is pushed down, the shielding is released, and the reed switch 41 is closed.

Therefore, the switch 36 in FIG. 1 is closed, and the differentiating circuit 24
A differential output is generated from the differential output, and the flip-flop circuits 19 and 20 and the clock circuit 5 are reset.

By resetting the flip-flop circuit 19, its output Q
is inverted to a low level, gate circuit 6 closes and the alarm sound stops, and gate circuits 7 and 8 are opened by the output page.

To close the switch 36 to temporarily stop the alarm sound, simply press the pressure knob 37 in Fig. 3, and it will open again when you release your hand, so the closing time is usually extremely short ( In this example, when this closing time is within 10 seconds, 3 minutes 3 minutes
The alarm sound is generated again after 0 seconds.

Now, by resetting the flip-flop circuit 20 by closing the switch 36, its output is inverted to a high level and the gate circuit 12 is opened, but after 10 seconds, a pulse a1 is sent from the terminal C of the timing circuit 5 as shown in FIG. 2A. occurs, and the flip-flop circuit 20 is set by its rise.

Therefore, the gate circuit 12 is 10
If the switch 36 is opened for only a second and the switch 36 is opened during that time, that is, if the press knob 37 in FIG.

On the other hand, since the flip-flop circuits 21, 22 and 23 have all been reset, the output of the gate circuit 13 is held at a high level.

Therefore, when the pulse from the gate circuit 12 passes through the gate circuit 17 and triggers the flip-flop circuit 21, its output Q is inverted to a high level.

As a result, the power of the gate circuit 11 is maintained at a high level, and the output of the gate circuit 13 is inverted to a low level.

Now, 3 minutes and 30 seconds after the above-mentioned closing of the switch 36, when a pulse f1 having a width of 30 seconds as shown in the second F is generated from the gate circuit 8 by the output of the clock circuit 5, an alarm signal from the frequency divider 2 is transmitted to the gate circuit 11. pass through.

This further passes through the gate circuit 18 and the speaker 33
An alarm sound is generated.

Here, in order to temporarily stop the alarm sound again, close the switch 36 for less than 10 seconds in the same manner as above.
The flip-flop circuits 19 and 20 and the clock circuit 5 are reset, and a pulse is generated from the gate circuit 12 in the same manner as above, which is transmitted to the flip-flop circuits 21 and 22.
．． Trigger 23.

Therefore, the outputs of the flip-flop circuits 21 and 220 are inverted to low and high levels, respectively, and the output Q of the flip-flop circuit 22 inverts the output of the gate circuit 10 to a high level.

When a pulse e1 having a width of 30 seconds as shown in the second E is generated from the gate circuit 7 1 minute and 30 seconds after the above-mentioned closing of the switch 36, the wake-up signal from the frequency divider 2 passes through the gate circuit 10.

Therefore, a wake-up sound is generated from the speaker 33 in the same manner as above.

By the way, if the switch 36 is not closed when the wake-up sound is generated by the pulse f1 shown in the second F diagram, the following operation is performed.

When the pulse f1 stops, the gate circuit 11 closes and the alarm sound stops.

On the other hand, the falling edge of the pulse f1 is differentiated by the differentiating circuit 26, triggering the flip-flop circuit 21 via the inverter 31 and the gate circuit 17, and also triggering the flip-flop circuit 22 via the gate circuit 14.

Therefore, the outputs Q of the flip-flop circuits 21 and 22 are inverted to low level and high level, respectively, and the gate circuit 1
The single-handed power of gate circuit 10 is maintained at a low level, and the single-handed power of gate circuit 10 is maintained at a high level.

When the pulse e2 shown in FIG. 2E is generated from the gate circuit 7 after 1 minute and 30 seconds, the wake-up signal from the frequency divider 2 passes through the gate circuit 10 and an wake-up sound is generated.

At this point, turn the switch 36 to 1 again to temporarily stop the alarm sound.
When the circuit is closed for a period of less than 0 seconds, the output Q of the flip-flop circuit 23 is inverted to a high level, and the output of the gate circuit 15 is held at a high level, and the power of the gate circuit 9 is held at a high level.

Therefore, the pulse b in FIG. 2B from the terminal d of the timing circuit 5
1, the wake-up signal passes through the gate circuit 9 after 30 seconds, and the wake-up sound is generated from the speaker 33.

By the way, if the switch 36 is not closed when the wake-up sound is generated by the pulse e2 shown in 2E, the stop of the pulse e2 closes the gate circuit 10 and stops the wake-up sound.

On the other hand, a differential output is generated from the differentiating circuit 25 due to the fall of the pulse e2, which is transmitted to the inverter 30 and the gate circuit 1.
triggers the flip-flop circuit 22 via 4.

Further, the differential output via the inverter 30 triggers the flip-flop circuit 23 via the gate circuit 16.

Therefore, the outputs Q of the flip-flop circuits 22 and 23 are inverted to low level and high level, respectively, and the gate circuit 1
0 and 9 close and open, respectively.

Therefore, after 30 seconds, the second B from the terminal d of the timing circuit 5
A wake-up signal is generated from the gate circuit 9 by the pulse b2 in the figure, and a wake-up sound is generated.

After this, the output Q of the flip-flop circuit 23 remains at a high level, so that the wake-up sound force is generated every 30 seconds by the pulse shown in FIG. 2B.

Therefore, in order to completely stop the alarm sound, press the pressure knob 37 shown in FIG.

The suppression knob 37 is rotated while the upper end of the cylinder 38b is pressed down below the lower ends of the recesses 39a and 39b of the cylindrical body 39.

Even if you release your hand there, the convex portion 38a remains. The upper end of 38b is the cylinder 3
9, the shaft 38 is held in a pressed state, the shielding plate 44 remains pressed downward, and the reed switch 41 is held in a closed state.

Therefore, switch 36 in FIG. 1 is held closed,
Gate circuits 9, 10, and 11 are closed, and no alarm sound is generated.

When a pulse with a period of 64 minutes is generated from the terminal g of the clock circuit 5, the differential output resets the flip-flop circuits 19, 21, 22.degree. 23, and returns to the initial state.

The gate circuit 18a is closed by the above-mentioned 64-minute period pulse, and the timer circuit 5 does not operate until it is reset next time.

As described above, by operating one switch mechanism, the alarm sound can be generated continuously or intermittently by gradually shortening the generation interval, and it can also be stopped, so there is only one switch other than the alarm switch. Moreover, since the circuit configuration can be extremely miniaturized by integrating it, it is effective in miniaturizing the clock device.

In the above embodiment, the reference switch 35 is the speaker 33.
is connected in series to control the generation of the alarm sound, but the invention is not limited to this, and the logical T'Lffl level can be selected using a reference switch to control the opening and closing of the gate circuits 6, 9, 10° 11. Good too.

Further, in the above embodiment, when the switch 36 is left open, the interval between alarm sounds is automatically shortened, but if there is no need to automatically shorten the interval between alarm sounds, it is possible to In place of the circuits 21, 22, 23 and the gate circuits 13, 14, 15, 16, a 3-bit shift register may be used to control opening and closing of the gate circuits 9, 10, 110.

Further, the generation interval of the alarm sound is not limited to the time in the above embodiment, but can be arbitrarily set by using an appropriate output of the timer circuit.

Further, in the above embodiment, the wake-up signal from the frequency divider 2 is supplied to the sound generation device to generate the sound, but the invention is not limited to this, and the wake-up signal and the wake-up sound may be generated from the sound generation device itself.

For example, the alarm signal from the frequency divider 2 in FIG. It may also be supplied to a speaker or the like to generate sound.

Further, in the above embodiment, the output of the timing circuit 5 is used to detect the output of the switch corresponding to the temporary stop, but the present invention is not limited to this, and a one-shot pulse generator is used to detect the switch closing time as desired. Alternatively, it may be determined whether the time is within the time limit.

As described in detail above, according to the present invention, a switch mechanism is provided in which the opening/closing mode of the contact corresponding to setting the alarm, temporarily stopping the alarm sound, and completely stopping the alarm sound is set by manual operation of the same actuating piece. , we made the alarm sound generation interval different each time a temporary stop is performed, so
A single switch mechanism can selectively set the alarm, temporarily stop the alarm sound, and completely stop the alarm sound, making it easy to operate, simplifying the configuration, and making the clock device more compact. It is valid.

Further, each time a temporary stop is performed, a wake-up sound is generated repeatedly, and the interval between generation of the wake-up sounds gradually changes, so that the user can be woken up gradually and reliably.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a partially cutaway perspective view showing an example of a switch mechanism. FIG. 4 is a partially omitted sectional view showing the switch mechanism shown in FIG. 3 in an attached state. 5...Clock circuit, 7-17...Gate circuit, 19-23...Flip-flop circuit,
24゜27...Differential circuit, 32...Transistor, 33...Speaker, 35...
・・Guideline switch 36 ・・・Switch 41
······Reed switch.

Claims (1)

[Claims] 1 A switch mechanism that sets the opening and closing of the contacts corresponding to setting the alarm, temporarily stopping the alarm sound, and completely stopping the alarm sound by manual operation of the same actuating piece, and an output of the switch mechanism corresponding to the temporary stop. a detection circuit for detecting;
A memory circuit stores the number of times the actuating piece is operated to set a temporary stop based on the output of the detection circuit, a selection circuit selectively generates control outputs of different cycles according to the output of the memory circuit, and A timer that operates, a sounding device that intermittently generates an alarm sound through the cooperation of the control output of the selection circuit, the output of the switch mechanism, and the timer, and the cooperation of the output of the switch mechanism corresponding to the set and the timer. A wake-up sound generating device comprising: a control circuit that operates a sound-producing device to generate a wake-up sound; and a device that completely stops the wake-up sound from the sound generating device by an output of a switch mechanism corresponding to a complete stop.