JPH0132689B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an all-electronic timer, and in particular, to a device that allows the timer time to be set with extremely simple operations.

Conventional electronic timers, which count signals from a reference signal source using a counter and turn on or off external devices connected to the timer or issue an alarm when a preset time elapses, are mechanical. It has various advantages compared to other timers, such as very high precision in setting time and small size. However, on the other hand, it has the disadvantage that setting the timer time is time consuming. In other words, in the conventional mechanical timer, the timer time can be set simply by rotating the knob for setting the timer time. On the other hand, with an electronic timer, the timer time has to be operated without operating multiple switches, such as a switch to change from the normal state to a correctable state, a switch to change the correction digit, and a switch to generate correction pulses. cannot be set,
This was extremely troublesome for the user.

The present invention eliminates the above-mentioned conventional drawbacks, and aims to provide an electronic timer that can set the timer time with a much simpler operation than the conventional one.

By the way, the timer time varies depending on the purpose of the timer, but it is 3 minutes,
It is known that the values are somewhat fixed, such as 4 minutes, 5 minutes, 10 minutes, 15 minutes, 20 minutes, etc. The present invention makes use of this fact, stores the number of times the timer time changeover switch is operated, and supplies the corresponding number of pulses to the timer counter according to the stored number of times the switch is operated. The timer time can be set by operating a single external operation switch.

Examples will be described below based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In this embodiment, the counter that counts the timer time is configured to be an up-down counter, and when setting the initial value to the counter, it becomes an addition counter, and when counting the timer time, it becomes a subtraction counter, and is configured to subtract the initial value. has been done. Each time you press the external switch, the timer time changes to 3 minutes, 4 minutes, 5 minutes, 10 minutes, 15 minutes, etc.
It is structured to vary over 20 minutes.

The reference signal source 2 includes a reference signal generator 4, a frequency dividing circuit 6, and a one-minute counter 8, and generates a signal every minute. A minutely signal from the reference signal source 2 is applied via an OR gate 10 to a counter 12 that counts the timer time. In this embodiment, the counter 12 is composed of an up-down counter that can add and subtract. The output signal of counter 12 is applied to a NOR gate 14, and the output signal of NOR gate 14 is applied to a set input S of flip-flop 16. The signal of the output Q of the flip-flop 16 is output from an external device connected to the outside of the timer or an alarm.
It is applied to the external device control circuit 20 that controls ON and OFF. The NOR gate 16, flip-flop 18, and external device control circuit 20 constitute an operation control circuit 22.

The timer set/unset switch 24 is connected to a flip-flop 26 whose output signal is applied to the reset input R of the one-minute counter 8 and to the U/D input of the counter. This output signal is transmitted to the flip-flop 28,
30 and an AND gate 32 to the reset input R of the flip-flop 18. The timer set/unset switch 24, flip-flops 26, 28, 30, and AND gate 32 constitute a timer start circuit 33.

The timer time changeover switch 34 is applied to the clock inputs φ of the flip-flops 38a, 38b, . . . , 38f via an anti-chattering flip-flop 36. These flip-flops 38a, 38b, . . . , 38f constitute a storage circuit 38 that stores the number of times the switch 34 has been operated.

The signal of switch 34 via anti-chattering flip-flop 36 is also applied to input D of flip-flop 40 and to AND gate 42. The flip-flops 36, 40 and AND gate 42 constitute a one-shot pulse generating circuit. The output signal of AND gate 42 is then applied to one of the inputs of AND gates 46 and 48, respectively. With this switch 34, flip-flops 36, 40 and AND gate 42,
A timer time changeover switch circuit 43 is configured.

The signals of the outputs Q of flip-flops 38b and 38c are applied to the other input of the AND gate 46 via an OR gate 50, and the signal of the output Q of the flip-flops 38b and 38c is applied to the other input of the AND gate 48.
The output Q signals of d, 38e and 38f are applied via OR gate 52. The AND gates 46 and 48 and the OR gates 50 and 52 constitute a selection gate circuit 53. An inverter 56 is connected to the clock input φ of the flip-flop 54.
The output signal of the AND gate 32 is applied directly to the reset input R of the flip-flops 38a, 38b, . . . , 38f. The signal at the output Q of the flip-flop 54 is passed through a one-shot pulse generation circuit composed of flip-flops 58 and 60 and an AND gate 62 to the set input S of the flip-flop 38a and the counter 1.
2, the reset input R of flip-flop 54, and NOR gate 64. The initial clear circuit 65 is formed by the flip-flops 54, 58, 60, the inverter 56, and the AND gate 62.
Configure. The output signal of the AND gate 48 is also applied to the NOR gate 64, and the output signal of the NOR gate 64 is applied to the flip-flop 66.
is applied to the clock input φ. The signal at the output Q of this flip-flop 66 is connected to the AND gate 6
The output signal is applied to one of the inputs of the flip-flop 70, 7, which constitutes an octal counter.
It is applied to the reset input R of 2.74. A 32 Hz signal 76 from the frequency divider circuit 6 is applied to the clock input φ of the flip-flop 70 via an AND gate 68. flipflop 70,
The signals of the outputs Q of the flip-flops 72 and 74 are applied to AND gates 78 and 80, respectively, and the signal of the output Q of the flip-flop 38a is applied to the AND gate 78, and the output signal of the OR gate 52 is applied to the AND gate 80. has been done. The output signals of AND gates 78, 80 are applied to reset input R of flip-flop 66 via OR gate 82.

The output signal of AND gate 46 is applied via OR gate 10 to the clock input of counter 12, and the output signal of AND gate 68 is also applied via OR gate 10 to the clock input φ of counter 12. The NOR gate 64, flip-flops 66, 70, 72, 74, AND gates 68, 78, 80, and OR gate 82 constitute a correction pulse generating circuit 84.

The operation of this circuit will be explained below.

If the contact piece of the timer set/unset switch 24 is closed to the contact 24a side, the signal of the output Q of the flip-flop 38a of the memory circuit 38 becomes H, and the other flip-flops 38b, 38c, . . . 38
The signal of the output Q of f is L. In this state, the count content of the counter 12 is "3". Here, when the user presses the timer time changeover switch 34 once, an H signal is shifted to the output Q of the flip-flop 38b, and the AND gate 46 is opened. At the same time, and gate 42
A single positive pulse is generated from , which is applied to the clock input φ of the counter 12 via an AND gate 46 and an OR gate 10 . At this time, the timer is in a non-set state with the switch 24 closed to the side 24b, and the flip-flop 26 is closed.
Since the output signal of is H, the counter 12 becomes an addition counter, and the count content of the counter 12 is incremented by 1 and becomes "4". When the timer set/unset switch 24 is closed to the contact 24a side, the output signal of the flip-flop 26 goes low.
Therefore, the counter 12 becomes a subtraction counter. At the same time, the 1-minute counter 8 is released from reset and starts counting the 1Hz signal from the frequency divider circuit 6, and sends a carry signal every minute to the clock input φ of the counter 12.
Output to. The counter 12 is decremented by this carry signal, and when four minutes have elapsed since the timer was set, the contents of the counter become "0" and the output signal of the NAND gate 16 rises from L to H.
Due to this rising signal, the signal of the output Q of the flip-flop 18 becomes H, and the external device control circuit 20
This can be used to generate an alarm sound or control the ON/OFF operation of external equipment. Thereafter, when the user closes the timer set/unset switch 24 to the contact 24a, the signal at the output Q of the flip-flop 26 changes from L to H. As a result, a positive single pulse is generated from the AND gate 32,
This pulse resets the flip-flop 18 and the signal at the output Q returns to L, stopping the operation of the external equipment or alarm. Also, the single pulse from the AND gate 32 temporarily resets the flip-flops 38a, 38b, . Let it be H.
Due to the H signal, a positive single pulse is generated from the AND gate 62. This pulse sets only the flip-flop 38a and outputs Q.
The flip-flop 54 is temporarily reset, and its output Q signal is set to L. This single pulse is also applied via NOR gate 64 to the clock input φ of flip-flop 66. Then, as the pulse rises, the output signal of the flip-flop 66 changes from H to L, releasing the reset of the flip-flops 70, 72, and 74, and the output Q signal changes from L to H, which opens the AND gate 68 and divides the frequency. 32Hz signal 76 from circuit 6
is applied to the clock input φ of the counter 12 via the clock input φ of the flip-flop 70 and the OR gate 10. The octal counter consisting of the counter 12 and flip-flops 70, 72, and 74 counts the 32Hz signal, and when the count reaches "3", the output signal of the AND gate 78 changes from L to H, and the H The signal is OR gate 8
2 to the reset input R of flip-flop 66 to reset flip-flop 66. As a result, the output Q signal of the flip-flop 66 returns to L, the output signal returns to H, and the AND gate 68 closes and the flip-flops 70, 72,
74 is reset, and only the count content of the counter 12 remains at "3". Therefore, in this state, if the timer set/unset switch 24 is again closed to the contact 24b side to set the timer, the timer starts operating, and after 3 minutes, the external equipment or alarm is operated. In this way, when the timer time changeover switch 34 is pressed once, the timer time changes from 3 minutes to 4 minutes, and when the timer is brought to a non-set state, the timer time returns to 3 minutes.

Next, the case where the timer changeover switch 34 is pressed twice will be explained. First, when the timer changeover switch 34 is pressed once, the count content of the counter 12 is incremented by 1 and becomes "4" as described above.
becomes. Then, when you press switch 34 again,
An H signal is shifted to the output Q of flip-flop 38c, and AND gate 46 remains open. Then, by pressing the switch 34, a positive single pulse generated from the AND gate 42 is applied to the clock input φ of the counter 12 via the AND gate 46 and the OR gate 10, and the count content of the counter 12 is set to "5". . Therefore, if you set the timer here, the external device will start operating after 5 minutes, and if you then set the timer to non-set state, the external device will stop operating as described above, and the count contents of counter 12 will change. It becomes "3" again.

Next, the case where the timer time changeover switch 34 is pressed three times will be explained. When the timer time changeover switch 34 is pressed twice, the counter 12 is set to "5" as described above, and the timer time becomes 5 minutes. After that, when the switch 34 is pressed again, the signal of the output Q of the flip-flop 38d becomes H, and the AND gate 48 is opened.
The single pulse generated in the AND gate 48,
It is applied via NOR gate 64 to the clock input φ of flip-flop 66. As a result, the 32 Hz signal 76 from the frequency divider circuit 6 is applied to the flip-flops 70, 72, and 74 via the AND gate 68 as previously described. Then, when the count content of the counter 12 is incremented by "5" and becomes "10", the output signal of the AND gate 80 changes from L to H, and the flip-flop 66 is reset via the OR gate 82. When the timer time changeover switch 34 is pressed three times in this manner, the timer time becomes 10 minutes.

Furthermore, when the timer time changeover switch 34 is pressed four times, the output Q of the flip-flop 38e is
The signal becomes H, and the positive single pulse generated at the AND gate 42 is again applied to the clock input φ of the flip-flop 66 via the AND gate 48 and the NOR gate 64. Therefore, "5" is added to the counter 12 again, and the count content is 3.
When you press the button twice, the number becomes 15, including the 10 counted. As a result, the timer time becomes 15 minutes.

When the timer time changeover switch 34 is pressed five times, the H signal is shifted to the output Q of the flip-flop 38f, and the AND gate 4 is pressed as before.
The positive single pulse generated at 2 is applied to the clock input φ of the flip-flop 66 via the AND gate 48 and the NOR gate 64. Therefore, as before, "5" is added to the counter 12, and the count becomes "20", including the "15" counted by pressing the switch 34 four times. As a result, the timer time becomes 20 minutes.

In this way, the timer time changeover switch 34
Each time you press , the timer time changes from 3 minutes to 4 minutes.
minutes, 5 minutes, 10 minutes, 15 minutes, and 20 minutes, and when the timer is returned from set to non-set using the timer set/non-set switch 24, the timer time returns to 3 minutes. Also, since the flip-flops 38a, 38b, ..., 38f of the memory circuit 38 constitute a ring counter, if the timer time changeover switch 34 is pressed six times or more, the timer time changes again to 3 minutes, 4 minutes, 5 minutes, etc. do.

In this way, according to this embodiment, the most used timer times are 3 minutes, 4 minutes, 5 minutes, 10 minutes, and 15 minutes.
Now you can easily set the time for 20 minutes or 20 minutes by pressing a single switch, eliminating the hassle of operating multiple switches to set the timer time as in the past. Furthermore, in this example,
The counter 12 that counts the timer time is composed of an up-down counter, and when setting the timer time, it adds and counts, and when measuring the timer time, it subtracts from the initial value, which is conventionally used. A matching circuit for comparing the timer time storage counter and the timer time integration counter with the timer time storage counter is unnecessary, and the circuit can be simplified.

In this example, the timer time is 3 minutes, 4 minutes,
It is set to minutes, 5 minutes, 10 minutes, 15 minutes, and 20 minutes.
It is also possible to set other times depending on the purpose of use. Further, in this embodiment, the timer time is changed depending on the number of times the timer time changeover switch 34 is opened and closed, but it is also possible to change the timer time by changing the opening and closing time of the switch.

As described above, according to the present invention, it is now possible to easily set frequently used timer times by simply changing the number of operations of one external switch, making the all-electronic timer extremely easy to use. can be provided.

[Brief explanation of drawings]

The drawing is a circuit diagram showing an embodiment of the present invention. 2... Reference signal source, 12... Counter, 22...
...Operation control circuit, 33...Timer start circuit, 38...Memory circuit, 43...Timer time changeover switch circuit, 53...Selection gate circuit,
65... Initial clear circuit, 84... Correction pulse generation circuit.

Claims (1)

[Claims] 1. A reference signal source that generates a reference signal, a timer counter that can add and subtract the reference signal from this reference signal source, and when the count value of this timer counter reaches "0", controls the operation of the connected external equipment. and a timer that outputs a signal for selecting either a timer operation mode in which the timer counter is enabled to perform subtraction counts by external operation, or a timer setting mode in which the timer counter is enabled to perform addition counts and stops the operation of the reference signal source. In an electronic timer having a start circuit and a timer time changeover switch circuit that outputs a pulse signal that increments the count value of the timer counter by external operation, the number of occurrences of the pulse signal from the timer time changeover switch circuit is determined. a memory circuit for storing data; an initial clear circuit for clearing the memory circuit when the timer start circuit selects a timer setting mode; a correction pulse generation circuit that generates a number of pulse signals corresponding to the count output of the storage circuit; and a correction pulse generation circuit that generates a pulse signal from the timer time changeover switch circuit in response to the count output from the storage circuit; a selection gate circuit that selects whether to supply the signal to the circuit or the timer counter; an OR gate that supplies the pulse signals from the reference signal source, the correction pulse generation circuit, and the selection gate circuit to the clock input of the timer counter;
An electronic timer characterized by the provision of.