JPS6026190B2 - alarm clock - Google Patents

Description

[Detailed description of the invention] The present invention relates to a self-aware clock.

Conventionally, there are various types of electronic watches that take out the output of the frequency division stage and generate a sound, and most of these devices have integrated circuit configurations.

However, as the number of integrated circuits increases, the possibility of failure increases, and if we want to provide various functions such as self-aware functions such as temporarily stopping sound, it is necessary to provide a switch for this purpose. Since an integrated circuit requires an input terminal to receive a signal from the switch, there has been a problem in that the number of terminals of the integrated circuit increases as the functions increase. Therefore, the present invention supplies a pulse signal from a frequency dividing means to a switching means consisting of a switch that operates at a set time, a Q island stop switch, and a resistor, and generates one of two types of logic output and a pulse signal from an output terminal. ,
This allows the switching state of each switch to be detected and recognized, and the generation of sound to be controlled, thereby eliminating the drawbacks of the prior art. An embodiment of the present invention will be described below based on the drawings.

1 is a crystal oscillator, 2...6 is a frequency divider, and from each output several KH2, 16 days 2, 8Hz, 4Hz, I
A pulse of H2 is generated.

Reference numeral 7 denotes a clock circuit, which produces an output when 5 minutes have been counted.

Reference numeral 8 denotes a drive device such as a motor, which moves the pointer forward.

9...21 are gate circuits, 22...29 are inverters, and 30...37 are flip-flop circuits.

Flip-flop circuit 30...33, gate circuit 9...
12 and inverters 24 and 25 constitute a detection means. The gate circuits 19, 21, flip-flop circuits 36, 37, etc. constitute a control means. 38 is an amplifier, and 39 is a speaker, which constitutes a sound generation device.

40 and 41 are resistors, and the resistance value of resistor 41 is equal to resistor 40.
It is set sufficiently larger than that of .

42 and 43 are a guide switch and a manual Q island stop switch, respectively.

FIGS. 2 and 3 show the detailed configuration of the switch 43. In FIG. 2, 44 is a pressing knob, which is fixed to a shaft 45. 46 is a cylindrical body, the upper and lower halves of which have different thicknesses to form a stepped portion 46C, and the thicker portion of the upper half has recesses 46a and 46b.
has been formed.

Convex portions 45a formed on the shaft 45 are provided in the concave portions 46a and 46b.
45b has been inserted. 47 is a magnet, 48 is a reed switch, and each has a fixing member (not shown).

) is fixed. The reed switch 48 constitutes the switch 43 in FIG. The cylindrical body 46 is screwed to a fixed plate 49 as shown in FIG. 3, and one end of a spring 50 is fixed to the lower end of the inner surface thereof. Further, the spring end of the spring 50 is fixed to the shaft 45. Therefore, in the normal state, the shaft 45 is pushed upward by the spring 501, and in this state, the lead switch 48 in FIG. 3 is shielded by the shielding plate 51 fixed to the shaft 45. 52 is the outer frame of the clock.

Next, the operation will be explained. It is assumed that the flip-flop circuits 34, 36, and 37 are reset in the initial state. First, as a guide, switch 42 and switch 43
2 and 3 are held in the normal state, and when the reed switch 48 is engaged by the shielding plate 51 of FIG. A 4Hz pulse from the frequency divider 5 is generated at the connection terminal P via the resistor 40, and is supplied to the gate circuit 9, and further inverted via the inverter 23 and supplied to the gate circuit 101. On the other hand, the 4Hz pulse is inverted and supplied to the gate circuit 9 via the inverter 22, and the gate circuit 10 is supplied with the 4Hz 2 pulse.

Therefore, both inputs of gate circuits 9 and 10 are supplied with pulses having the same period and whose levels are inverted to each other, their respective outputs are held at a high level, and the inputs of flip-flop circuits 30 and 32 are held at a high level. On the other hand, the following pulses are supplied to the clock inputs of the flip-flop circuits 30 and 32. The 16Hz pulse shown in FIG. 4A from the terminal a of the frequency divider 3 is inverted by the inverter 26 and supplied to the gate circuit 2, and the 16Hz pulse shown in FIG. Pulses are also supplied to the gate circuit 20. Therefore, the pulse shown in FIG. 4C is generated at the output of the inverter 27, and this pulse is supplied to the gate circuits 11 and 12. The gate circuits 11 and 12 each receive an inverted pulse of the 4Hz pulse shown in FIG.
pulses are being supplied. Therefore, the inverter 24,
25, the pulses E and F in FIG.
, 32, and a flip-flop circuit 31 and a flip-flop circuit 33, 3.
It also serves as the clock pulse of 6. Therefore, as mentioned above, when the outputs of the gate circuits 9 and 10 are held at a high level, the outputs Q of the flip-flop circuits 30 and 32 are held at a low level by the clock pulse. The gate circuit 19 is closed by the output Q of the flip-flop circuit 32, and no output pulse is generated and no sound is generated from the speaker 39. Furthermore, since the output Q of the flip-flop circuit 32 holds the output of the gate circuit 13 at a low level, the flip-flop circuit 37
is held in a reset state, and its output Q also closes the gate circuit 19. On the other hand, since the output Q of the flip-flop circuits 30 and 32 is at a low level, the output Q of the flip-flop circuits 31 and 33 is held at a high level by the above clock pulse, and the output Q of the flip-flop circuit 31 and 33 is held at a high level by the above clock pulse.
When the output Q of 1 is held at a high level, the above Q. Flip flop due to clock pulse. The output Q of circuit 35 is held at a high level. Output Q of flip-flop circuit 35
The gate circuit 16 opens, and a pulse from the inverter 22 passes through it to set the flip-flop circuit 34, keeping its output Q at a high level. Then, when the desired reference switch 42 is closed, the connection terminal P is held at a high level since the resistor 40 is set sufficiently smaller than the resistor 41. Therefore, one input of the gate circuit 9 is held at a high level, and a pulse from the inverter 22, that is, a pulse shown in FIG. 4D is generated at its output. On the other hand, the output of the gate circuit 10 remains at a high level due to the output of the inverter 23. When the above-mentioned pulse is generated from the iron gate circuit 9 and the input of the flip-flop circuit 32 becomes low level, the pulse shown in FIG. , one input of the gate circuit 19 is held at a high level. Since the outputs of the flip-flop circuits 33 and 34 are currently held at a high level, the output of the gate circuit 13 is inverted to a high level. After the above-mentioned pulse is generated from the inverter 24, a fourth pulse is generated from the output of the inverter 25.
When the pulse shown in Figure F occurs, the flip-flop circuit 33
The output Q of is inverted to low level. Therefore, gate circuit 1
One pulse will be generated at the output of No.3. This pulse passes through the gate circuit 17 to the flip-flop circuit 36.
Then, the clock circuit 7 is reset and the flip-flop circuit 37 is set, its output Q is inverted to high level, and the gate circuit 19 is opened. Therefore, gate circuit 1
A pulse of several KHz is supplied to the amplifier 38 via the inverter 28, the gate circuit 19, and the inverter 29 at a period of 1/4 second from 8, and a perceptible sound is generated from the speaker 39. On the other hand, due to the above-mentioned reset of the flip-flop circuit 36, the gate circuit 21 becomes involved, and the I
The HZ pulse passes through this and is supplied to the clock circuit 7. When the timer circuit 7 counts five minutes, its output level is inverted, triggering the flip-flop circuit 37, and inverting the levels of its outputs Q, Q. Therefore, the gate circuit 19 is closed, the sound is automatically stopped, and the output Q of the flip-flop circuit 36 is inverted to a low level, which closes the gate circuit 21 and stops supplying pulses to the clock circuit 7. to stop. In this way, when the indicator switch 42 is closed, a sound is generated as a result of the user's awareness, and the sound is automatically recognized and stops after 5 minutes.

However, the time when the sound is generated is not limited to 5 minutes, and the timing circuit 7
It can be arbitrarily determined by setting . Next, the operation when the switch 43 is once closed after the reference switch 42 is closed and the switch 43 is closed again will be described.

When the switch 43 is opened while the reference switch 42 is closed and a sound is generated, that is, when the press knob 44 in FIG. 2 is pressed, the shielding plate 51 is pushed down and the shielding is released. When the reed switch 48 is opened, the connection terminal P is held at a low level, the output of the gate circuit 9 is held at a high level, and the inverted pulse shown in FIG. 4D is generated from the gate circuit 10. Therefore, when the pulse shown in FIG. 4E is generated from the inverter 24, the output Q of the flip-flop circuit 32 is inverted to a low level, the gate circuit 19 is closed, and the sound stops. On the other hand, gate circuit 1
0 to flip-flop circuit 30 by the above pulse.
When the input of the flip-flop circuit 30 is inverted to a low level, the pulse of FIG.
The output Q of is inverted to high level. Next, inverter 24
Since the output Q of the flip-flop circuit 31 is held at a high level until the pulse shown in FIG. The flip-flop circuit 37 is reset by this pulse, and its output Q is inverted to a low level, thereby holding one input of the gate circuit 19 at a low level. Further, the pulse resets the clock circuit 7 and the flip-flop circuit 36 via the gate circuit 17. Therefore, the clock circuit 7 starts counting time from this point. On the other hand, the gate circuit 15 is opened by the above-described bell inversion of the output Q of the flip-flop circuit 30, and when the pulse shown in FIG. 4D passes through this, the flip-flop circuit 34 is reset.
Its output Q is inverted to low level. Therefore, the gate circuit 13 is opened. When the switch 43 is engaged again, the connection terminal P is inverted to a high level, the outputs Q of the flip-flop circuits 30 and 32 are inverted to a low level and a high level, respectively, and one input of the gate circuit 13 is inverted to a high level. Invert. However, at this time, the output Q of the flip-flop circuit 34
Since the gate circuit 13 is closed, its output level is not inverted. Therefore, flip-flop circuit 37 is held in a reset state and gate circuit 19 is still closed. When the clock circuit 7 clocks 5 minutes, the flip-flop circuit 37
is triggered, the levels of its outputs Q and Q are inverted, the gate circuit 19 is involved, and a conscious sound is generated. On the other hand, the flip-flop circuit 36 is still held in the reset state, the gate circuit 21 is involved, and the clock circuit 7 continues to be supplied with pulses. If the switch 43 is not operated after this, the sound will continue to be generated, and when the clock circuit 7 measures the next 5 minutes, the output will trigger the flip-flop circuit 7 and close the gate circuit 19.
When you become aware of it, the past stops. On the other hand, the flip-flop circuit 36 is triggered by the output Q of the flip-flop circuit 37, and the gate circuit 21 is closed. By the way, when explaining the specifications of this device to a customer at a store, etc., if you set it to temporary stop, you will have to wait 5 minutes until the sound is generated, but if you want to immediately notice and hear the sound. The device immediately becomes aware of this and generates a sound by opening and closing the indicator switch as described below.

Once set to temporary stop, when the reference switch 42 is engaged, the flip-flop circuits 30...35 return to their initial states. Then, when the guide switch 42 is closed again, "the flip-flop circuit 3
2's output Q is inverted to high level and gate circuit 1
A pulse is generated from 3. Therefore, the flip-flop circuit 37 is set, the gate circuit 19 is opened, and a conscious sound is generated. As described above, by once closing the switch 43 and then engaging it again, the user becomes aware and stops the sound, and after 5 minutes, the user becomes aware again and generates the sound, and after setting the switch 43 temporarily, the reference switch 42 is turned on. When the device opens or closes, it “immediately becomes noticeable and generates a sound.

Furthermore, as described above, the timekeeping circuit 7 is used to set the temporary stop time and the generation time of the conscious sound, and only one timekeeping circuit is required, which simplifies the configuration. Next, when the user wants to completely stop the sound, the switch 43 is held in the closed state.

That is, by pressing the pressing knob 44 shown in FIG.
With the pressing knob 44 pressed down from the lower end of b.
Rotate. Even if you let go of your hand, the upper ends of the protrusions 45a and 45b will hit the step 46c of the cylinder 46, so the shaft 45 will remain pressed and the shielding plate 51 will remain pressed downward, causing the reed switch 48 is held closed. Therefore, the switch 43 in FIG. 1 is held open, the output Q of the flip-flop circuit 32 is held at a low level, the gate circuit 19 is opened, and no sound is generated. As described above, since the conscious control is performed according to the state of the connection terminal P, when integrating this device, it is necessary to derive only the hair connection terminal P as the terminal for conscious control. It's a good thing.

By the way, the reference switch used in conventional self-aware clocks is connected to the power supply, and when improving this self-aware clock like this device, most of the conventional reference switches can be used and the improvement can be easily made. It is something. As described in detail above, according to the present invention, one of two types of logic output and pulse signal is generated from one output terminal depending on the switching state of the switch operated at the time of setting and the Q island stopper switch. Since the above pulse signal uses the output from the frequency dividing means used for time display, there is no need to provide a new pulse signal generation means, and the frequency dividing means, detection means, etc. When the circuit configuration is integrated, a pulse signal can be supplied to the switching means within the integrated circuit, and one external input terminal for self-aware control is provided.
It is effective because it only requires a book and there is less risk of being affected by static electricity.

In addition, by providing a timer that generates an output after a certain period of time based on a specific output from the switching state detection means of each switch, and controlling the generation of sound using the power of this world, one terminal - By simply detecting the state, the system can be made aware of it and selectively generate a sound, temporarily stop, cancel the temporary stop, completely stop, etc.

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram showing an embodiment of the present invention, Fig. 2 is a cutaway perspective view of an example of the switch, and Fig. 3 is a diagram showing the switch shown in Fig. 2 installed. FIG. 4 is a cross-sectional view with parts omitted, and is a time chart for explaining the operation of FIG. 1. 2-6...Cylinder divider, 9-12...Gate circuit, 19
~21...Gate circuit, 22-29...Inverter, 3
0 to 33...Flip-flop circuit, 36, 37...
・Flip-flop circuit, 39... sound generating device, 42・
...Guideline switch, 43...Manual switch. Figure 2 and Figure 3 [Sphere Figure 4

Claims (1)

[Scope of Claims] 1. A frequency dividing means for dividing the frequency of a reference signal, a display means for displaying the time based on the output from the frequency dividing means, a switch that operates at a set time, a chirp switch, and a resistor. a switching means which receives the pulse signal from the frequency dividing means and produces one of two types of logical outputs and the pulse signal from the output terminal according to the switching state of each of the switches; and an output terminal of the switching means. It consists of a detection means for detecting the switching state of the switch according to the state, a sound generation device for generating an alarm sound, and a control means for controlling generation of the alarm sound from the sound production device according to the output of the detection means. alarm clock. 2. A frequency dividing means that divides the frequency of the reference signal, a display means that displays the time based on the output from the frequency dividing means, a switch that operates at a set time, a chirp switch, and a resistor, and the frequency dividing means switching means that receives a pulse signal from the switch and generates one of two types of logical outputs and the pulse signal from an output terminal depending on the switching state of the switch; and a detection means that detects the state of the output terminal of the switching means. , a timekeeping means that starts timekeeping based on a specific output from the detection means and produces an output after a certain period of time; a sounding device that generates an alarm sound; and cooperation between the output of the timekeeping means and the output of the detection means. and control means for controlling the generation of the alarm sound from the sounding device.