JPS6057028B2 - alarm clock - Google Patents

Description

[Detailed description of the invention] The present invention relates to an alarm clock.

Conventionally, clocks that generate an alarm sound and have a function of temporarily stopping the alarm sound and then restarting the alarm sound are provided with independent alarm set switches and temporary stop switches.

Furthermore, when generating an alarm sound after a temporary stop, the indicator switch is mechanically closed. As a result, the structure becomes large and various problems arise due to wear and the like, which is not desirable. For example, when a customer wants to know the specifications of the above-mentioned clock device at a store, once it is set to temporary stop, it takes several minutes for the alarm to sound, and the customer has to wait until then to hear the tone of the alarm. Ta.

Therefore, the present invention eliminates the drawbacks of the above-mentioned conventional examples,
One embodiment will be described based on the drawings.

In Figure 1, 1 is a crystal oscillator, 2 is a frequency divider, and their output terminals a, b, and c each output several KH2) 8H2
and 1H2 signals are generated. Reference numeral 3 denotes a motor device which receives the 1H2 signal from the frequency divider 2 and drives the display device 4.

5 and 6 are clock circuits, and the clock circuit 5 has a frequency division ratio of 1/64.
The output terminals d and e each have a frequency divider of 4
H2 and 1/8H2 pulses are generated.

The clock circuit 6 consists of a frequency divider with a frequency division ratio of 1/64. 7 is a 4-bit shift register, 8...
...18 is a gate circuit.

The gate circuits 11, 12, and 13 constitute a discrimination circuit, the timekeeping circuit 6, the inverter 19, etc. constitute a first control/control circuit, and the timekeeping circuit 5 and the gate circuit 15,
16 and 17 constitute a second control circuit. 1
9 is an inverter, 20 is a transistor, 21 is a resistor, 2
2 is a speaker.

The speaker 22 constitutes a sound generating device using a transistor 20 and the like. 23 is a reference switch, and 24 is a switch.

FIGS. 2 and 3 show the detailed configuration of the switch 24. In FIG. 2, 25 is a pressing knob, which is fixed to a shaft 26. 27 is a cylindrical body, the upper and lower halves of which have different thicknesses to form a step 27c, and the thicker upper half has recesses 27a and 27b.
has been formed.

Convex portions 26a formed on the shaft 26 are provided in the concave portions 27a and 27b.
26b has been inserted. 28 is a magnet, and 29 is a reed switch, each of which is fixed to a fixing member (not shown).

The reed switch 29 constitutes the switch 24 in FIG. The cylindrical body 27 is attached to a fixing plate 30 as shown in FIG.
One end of a spring 31 is fixed to the lower end of the inner surface thereof. Further, the end of the spring 31 is fixed to the shaft 26. Therefore, in the normal state, the shaft 26 is pushed upward by the spring 31, and in this state, the reed switch 29 shown in FIG. 2 is shielded by a shielding plate 32 fixed to the shaft 26. 33 is the outer frame of the watch.Next, the operation will be explained.

First, a case will be described in which the alarm is set after a sufficient period of time has elapsed since the switch 24 in FIG. 1 was closed. While the switch 24 is closed, the gate circuit 9
's power is kept at a low level and its output is kept at a high level. On the other hand, the memory circuit 7 has a frequency divider 2 to 8H.
Since the pulse of z is constantly supplied, its output D,・
... All D4s are held at a high level.
Therefore, the output of the gate circuit 10 is held at a high level,
Timing circuits 5 and 6 count 8Hz pulses from frequency divider 2. When the output of the clock circuit 6 becomes a high level, the output of the inverter 19 becomes a low level, closing the gate circuit 18 to block its timekeeping power and holding the output of the gate circuit 15 at a high level. On the other hand, since the output 52 of the memory circuit 7 is held at a low level, the gate circuit 17 is closed and no wake-up signal is supplied to the transistor 20.
Set the alarm in the above state.

That is, while setting the target time to a desired time, the switches shown in FIGS. 2 and 3 are kept in the normal state, and the reed switch 29 is shielded by the shielding plate 32 shown in FIG. 2, and the switch shown in FIG. 24 is held in the open state. Therefore, the power of the gate circuit 9 is at a high level, and since the output of the gate circuit 8 is also at a high level, the output of the gate circuit 9 is at a low level. By the 8 Hz pulse from the frequency divider 2, the outputs 'D, . On the other hand, the gate circuit 14 has frequency dividers 5 to 4.
A pulse of Hz (114 second period) is supplied, and a wake-up signal of 114 second period is generated from the gate circuit 14, which passes through the gate circuits 16 and 17 and is supplied to the transistor 20. When the desired time is reached, the guide switch 23
When the alarm is closed, an alarm sound is generated from the speaker 22 at a cycle of 1 h seconds. j After temporarily stopping the alarm sound,
The operation of generating the alarm sound will be explained again.

When the press knob 25 in FIG. 2 is pressed to stop the alarm sound, the shield plate 32 is pushed down, the shield is released, and the reed switch 29 is closed. Closing for this temporary/stopping is done by simply pressing the pressure knob 25 in Figure 2, and as soon as the hand is released, it will open again, so the closing time is usually extremely short, and in this example, the closing time is If the time is within 4 seconds, the alarm sound is generated again after 256 seconds.
Now, by pressing the pressure knob 25, the switch 24 shown in FIG. 1 is closed and the output of the gate circuit 9 is inverted to a high level. Since the output 'D4 of the memory circuit 7 is at a high level, the output of the gate circuit 8 is held at a low level, and the output of the gate circuit 9 is held at the above-mentioned high level. As a result of this level inversion, the outputs Dl and D2 of the memory circuit 7 are sequentially inverted to a high level, and since the output is held at a high level at this time, the output of the gate circuit 10 is inverted to a low level. Therefore, the output of the gate circuit 13 becomes high level, and
The clock circuits 5 and 6 are reset. Therefore, both the power levels of the gate circuit 15 are at a high level and the output thereof is at a low level, and the gate circuit 16 is closed, blocking the passage of the alarm signal and stopping the alarm sound. Since the closing of the switch 24 is instantaneous, the output of the gate circuit 9 is inverted to a low level when the switch 24 is opened. Therefore, the memory circuit 7
Output D1...D4 and Fil...6
4 are again inverted and held at low and high levels, respectively, sequentially. Then, when 2568 elapses after the reset of the timer circuits 5 and 6, the output of the timer circuit 6 is inverted to a high level, the output of the inverter 19 is inverted to a low level, closing the gate circuit 18, and closing the output of the gate circuit 15. Invert to high level. Therefore, the gate circuit 16 is opened and the wake-up signal from the gate circuit 14 passes through, and further passes through the gate circuit and is supplied to the transistor 20, and the wake-up sound is generated from the speaker 22. Next, when the alarm sound is to be completely stopped, the switch 24 shown in FIG. 1 is held in the closed state, and this switch operation is performed as follows.

Press the pressure knob 25 shown in FIG.
, 26b is pushed down below the lower ends of the recesses 27a, 27b of the cylinder 27, and the press knob 25 is rotated. Even if the handle is released, the upper ends of the convex portions 26a and 26b contact the stepped portion 27c of the cylindrical body 27, so that the shaft 26 is held in a pressed state. Therefore, the switch 24 in FIG. 1 is kept closed, and the output of the gate circuit 9 is kept at a high level. Therefore, the output I2 of the memory circuit 7 is held at a low level, the gate circuit 17 is closed, and the alarm sound is completely stopped. By the way, for example, when a customer tries to listen to the tone of the alarm sound at a store, once the alarm is set to temporary stop, it takes 25 minutes for the alarm sound to sound, but in this embodiment, the alarm sound is immediately generated as follows. It is something that makes you First, the switch 24 is operated by closing the reference switch 23, then closing the switch 24 for 4 seconds or more, and then opening it again. That is, if the switch 24 is closed for 4 seconds or more, the alarm sound is stopped during this time by the output D2 of the memory circuit 7 as described above. On the other hand, by closing the switch 24, the output of the gate circuit 10 falls and the clock circuits 5 and 6 are reset, as described above. That is, the clock circuits 5 and 6 start measuring time from the above-mentioned closing time. Furthermore, since the output D4 of the memory circuit 7 is held at a high level, when the clock circuit 5 clocks 4 seconds and its output is reversed to a high level,
The output of the gate circuit 11 is inverted to low level. Therefore, the output of the gate circuit 12 is inverted to a high level, and since the output of the gate circuit 10 is at a high level at this time, the output of the gate circuit 13 is inverted to a low level. As a result, the output of the gate circuit 15 is inverted to a high level, and the gate circuit 16 is opened. When the switch 24 is opened or closed, the output I5'2 of the memory circuit 7 is inverted to the power level, the gate circuit 17 is opened, the wake-up signal passes through the gate circuits 16 and 17, and the speaker 22 generates a wake-up sound. In this way, if you want to hear the alarm tone, you can hear it immediately. In the above embodiment, the memory circuit 7 and the gate circuits 8 and 9 are mainly used to eliminate the influence of the chattering of the switch 24. The logical output may be directly supplied to the gate circuit 11, and the output may be inverted in level and supplied to the gate circuit 17.

At this time, if a differentiating circuit is used in place of the gate circuit 10, the same operation as described above can be performed. Further, in the above embodiment, the temporary stop time is set to 256 seconds, and the alarm sound is generated immediately when the switch 24 is closed after 4 seconds or more and then opened, but these set times are limited to the above. First, by appropriately setting the timer circuits 6 and 5, an arbitrary time can be set. As detailed above, according to the present invention, when the switch is operated only within the set time, the alarm sound is temporarily stopped and then generated again, and after the switch is operated continuously for more than the set time, it is made inactive. In this case, the alarm sound is immediately generated, so you can completely stop the alarm sound, temporarily stop it, and cancel the temporary stop with a single switch.
The configuration is simplified, and the alarm sound can be generated immediately with a simple switch operation, which is particularly effective when explaining the specifications of the clock device to customers at a store.

Moreover, since a common clock circuit is used to determine the operating time of the switch and to set the temporary stop time, the configuration is simple.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; Fig. 1 is an electric circuit diagram thereof, Fig. 2 is a partially cutaway perspective view of the switch, and Fig. 3 shows the switch mechanism shown in Fig. 2 installed. It is a partially omitted sectional view. 5, 6... Clock circuit, 11, 12, 13...
... Discrimination circuit, 15, 16, 17 ... Gate circuit, 20 ... Transistor, 22 ... Speaker, 23 ... l timer, 24 ... Switch.

Claims (1)

[Claims] 1. A display device that displays the time, a sound device that generates an alarm sound when the display device displays the set time, a switch that stops the alarm sound, and the operation of this switch starts timekeeping and starts the set time. When the operating time of the switch is within the set time by a clock circuit that generates an output when the time is counted and when the temporary stop time of the alarm sound is counted, and the output from this clock circuit and the output of the switch, the operation time of the switch is within the set time. A discrimination circuit that produces different outputs when the above-mentioned set time is exceeded, an output of the above-mentioned discrimination circuit when the above-mentioned switch is activated and then returned to the non-operating state within the above-mentioned set time, and an output of the above-mentioned time measurement circuit. a first control circuit that causes the alarm sound to be generated again after temporarily stopping the output; and an output of the discrimination circuit when the switch becomes inactive after being operated for more than the set time. and a second control circuit that immediately generates an alarm sound.