JPS5936250U - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS5936250U JPS5936250U JP12919782U JP12919782U JPS5936250U JP S5936250 U JPS5936250 U JP S5936250U JP 12919782 U JP12919782 U JP 12919782U JP 12919782 U JP12919782 U JP 12919782U JP S5936250 U JPS5936250 U JP S5936250U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- circuit device
- powder resin
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図イは従来の回路基板を流動槽に浸漬する前後の状
態を示す説明図、同口は従来のチップ部品を実装した回
路基板に粉体樹脂が付着した状態を示す断面図、第２図
イは本考案の回路基板を流動槽に浸漬する前後の状態を
示す説明図、同図口は同図イのＡ部拡大図、同図ハはチ
ップ部品を実装した本考案の回路基板に粉体樹脂が付着
した状態を示す断面図である。
１・・・粉体樹脂、２・・・流動槽、３・・・チップ部
品、４・・・回路基板、５・・・リード部、６・・・回
路基板上に並設されたチップ部品間の部分、７・・・並
設されたチップ部品間の空間、８・・・ガラス皮膜。Figure 1A is an explanatory diagram showing the state before and after immersing a conventional circuit board in a fluidized bath; Figure 1A is a sectional view showing a state in which powder resin has adhered to a circuit board on which conventional chip components are mounted; Figure A is an explanatory diagram showing the state of the circuit board of the present invention before and after being immersed in a fluidized tank. FIG. 3 is a cross-sectional view showing a state in which powdered resin is attached. DESCRIPTION OF SYMBOLS 1...Powder resin, 2...Fluidization tank, 3...Chip parts, 4...Circuit board, 5...Lead part, 6...Chip parts arranged in parallel on circuit board Part between, 7... Space between chip components arranged in parallel, 8... Glass film.
Claims (1)
行う混成集積回路に於て、該装置上に実装された並設さ
れた部品間の前記回路装置表面にガラス被膜等の前記粉
体樹脂と接着性の良い皮膜を設けたことを特徴とする混
成集積回路装置。In a hybrid integrated circuit that is packaged by applying a powder resin coating layer by the fluidized dipping method, the powder resin such as a glass coating is applied to the surface of the circuit device between the parallel parts mounted on the device. A hybrid integrated circuit device characterized by having a film with good adhesive properties.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12919782U JPS5936250U (en) | 1982-08-28 | 1982-08-28 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12919782U JPS5936250U (en) | 1982-08-28 | 1982-08-28 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5936250U true JPS5936250U (en) | 1984-03-07 |
Family
ID=30292816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12919782U Pending JPS5936250U (en) | 1982-08-28 | 1982-08-28 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5936250U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5756990A (en) * | 1980-09-22 | 1982-04-05 | Matsushita Electric Works Ltd | Method of mounting electronic part |
-
1982
- 1982-08-28 JP JP12919782U patent/JPS5936250U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5756990A (en) * | 1980-09-22 | 1982-04-05 | Matsushita Electric Works Ltd | Method of mounting electronic part |
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