JPS5935217B2 - C-MOS circuit - Google Patents

C-MOS circuit

Info

Publication number
JPS5935217B2
JPS5935217B2 JP52037076A JP3707677A JPS5935217B2 JP S5935217 B2 JPS5935217 B2 JP S5935217B2 JP 52037076 A JP52037076 A JP 52037076A JP 3707677 A JP3707677 A JP 3707677A JP S5935217 B2 JPS5935217 B2 JP S5935217B2
Authority
JP
Japan
Prior art keywords
power supply
mos transistor
supply control
power
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52037076A
Other languages
Japanese (ja)
Other versions
JPS53122354A (en
Inventor
伸一 田中
多喜次 峰山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP52037076A priority Critical patent/JPS5935217B2/en
Publication of JPS53122354A publication Critical patent/JPS53122354A/en
Publication of JPS5935217B2 publication Critical patent/JPS5935217B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Description

【発明の詳細な説明】 本発明はＭＯＳトランジスタを電源制御用スイッチとし
て用いる電子機器のＣ−ＭＯ８回路に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a C-MO8 circuit for electronic equipment that uses a MOS transistor as a power supply control switch.

例えば、計算機等の電子機器において、機械的な電源ス
ィッチを使用せず、電子回路のみからなる電源制御回路
を設け、キー操作に応答する制御信号により演算部表示
部等の被電源制御回路への電源供給を制御するものがあ
る。For example, in electronic devices such as computers, a power control circuit consisting only of electronic circuits is installed without using a mechanical power switch, and control signals that respond to key operations are used to control power-controlled circuits such as arithmetic unit display units. There is something that controls the power supply.

電源制御用ＭＯ８Ｉ−ランジスタはこの電源供給の制御
に用イられるが、従来は第１図のようなＣ−ＭＯ８回路
をとっている。A power supply control MO8I transistor is used to control this power supply, and conventionally a C-MO8 circuit as shown in FIG. 1 is used.

電源端子Ｔには電池電源等が接続され、Ｎチャンネル、
ＰチャンネルＭＯＳトランジスタＴ１ｊＴ２等から構成
されるゲートをこの電源により駆動し、いわゆる電源制
御回路Ｃ１を構成する。A battery power supply etc. is connected to the power supply terminal T, and N channel,
The gates composed of P-channel MOS transistors T1jT2 and the like are driven by this power supply, thereby forming a so-called power supply control circuit C1.

ＮチャンネルＭＯＳトランジスタＴ３は基板と同タイプ
のトランジスタからなる電源制御用スイッチである。The N-channel MOS transistor T3 is a power supply control switch made of the same type of transistor as the substrate.

Ｎチャンネル、ＰチャンネルＭＯＳトランジスタＴ４．
Ｔ５及びＴ６．Ｔ７等は電源制御用ＭＯ８Ｉ−ランジス
タＴ３を介して駆動されるものであり、被電源制御回路
Ｃ２のゲートを構成する。N-channel, P-channel MOS transistor T4.
T5 and T6. T7 and the like are driven via the power supply control MO8I-transistor T3, and constitute the gate of the power supply controlled circuit C2.

なお、構造はＮ−基板のものを用い負電源で使用される
ものとする。It is assumed that the structure has an N-substrate and is used with a negative power source.

また、この例ではインバータのみを示しているが、他の
ゲートも同様である。Further, although only the inverter is shown in this example, the same applies to other gates.

一般にＮ−基板で構成されるＣ−ＭＯ８構造のＰ−ウェ
ルは最低電位にすることから、ＮチャンネルＭＯＳトラ
ンジスタＴ、Ｔ６のサブストレート５ｕｂ（Ｐ−ウェル
）は電源制御用ＭＯＳトランジスタＴ３のソースＳに接
続される。Generally, the P-well of the C-MO8 structure composed of an N-substrate is set to the lowest potential, so the substrate 5ub (P-well) of the N-channel MOS transistors T and T6 is the source S of the power control MOS transistor T3. connected to.

ところで、このように電源制御用ＭＯＳトランジスタＴ
３が介在する場合、ＭＯＳトランジスタＴ３の電圧降下
のため、ＭＯＳトランジスタＴ４．Ｔ６のソースＳとサ
ブストレートＳｕｂは同電位でなくなる。By the way, in this way, the power supply control MOS transistor T
If MOS transistors T4.3 are present, MOS transistors T4. The source S of T6 and the substrate Sub are no longer at the same potential.

従って、ＭＯＳトランジスタＴ、、Ｔ６はバックゲート
効果により見かけ上スレッシュホールド’！圧が大きく
なり低電圧で動作しにくくなる。Therefore, the MOS transistors T, , T6 appear to be at the threshold due to the back gate effect! voltage increases, making it difficult to operate at low voltage.

さらにまた、ＭＯＳトランジスタＴ４． Ｔ６のサブス
トレー１ｓｕｂは電源端子Ｔに直結され常時電源電圧が
印加されるので、電源制御用ＭＯＳトランジスタＴ３が
オフ時でもＮ−基板との間に逆方向バイアスがかかり、
ＰＮ接合に逆方向リーク電流が流れる。Furthermore, MOS transistor T4. Since the substray 1sub of T6 is directly connected to the power supply terminal T and the power supply voltage is constantly applied, a reverse bias is applied between it and the N-substrate even when the power supply control MOS transistor T3 is off.
A reverse leakage current flows through the PN junction.

本発明はこの点を解消するものであり、低電圧動作、低
電流動作の可能なＣ−ＭＯ８回路を提供する。The present invention solves this problem and provides a C-MO8 circuit capable of low voltage operation and low current operation.

第２図は本発明の一実施例を示すものであり、第１図と
同一機能を有するものは同一符号を付している。FIG. 2 shows an embodiment of the present invention, and parts having the same functions as those in FIG. 1 are given the same reference numerals.

ＮチャンネルＭＯＳトランジスタＴ６１は、第１図と同
様、ＰチャンネルＭＯＳトランジスタエフと被電源制御
回路Ｃ２のインバータゲートを構成するが、ここではそ
のサブストレートＳｕｂを電源制御用ＭＯＳトランジス
タＴ３のドレインＤに接続している。As in FIG. 1, the N-channel MOS transistor T61 constitutes the inverter gate of the power-controlled circuit C2 with the P-channel MOS transistor F, but here its substrate Sub is connected to the drain D of the power-controlled MOS transistor T3. are doing.

このような接続はＭＯＳトランジスタＴ４を含め被電源
制御回路Ｃ２のＮチャンネルＭＯＳトランジスタについ
て行なうことが可能であり、パターン配線の様子によっ
て、本実施例のようにパターン配線が複雑にならない限
り任意または必要なＮチャンネルＭＯ８Ｉ−ランジスタ
に施こすようにしてもよい。Such a connection can be made for the N-channel MOS transistor of the power-controlled circuit C2, including the MOS transistor T4, and may be optional or necessary depending on the pattern wiring, as long as the pattern wiring does not become complicated as in this example. It may also be applied to an N-channel MO8I-transistor.

第２図において、少なくともＭＯ８Ｉ−ランジスタＴ
６／はソースＳとサブストレートＳｕｂを同電位にして
おりバックゲート効果がなく低電圧動作が可能であると
ともに、電源制御用ＭＯＳトランジスタＴ３のオフ時に
はＭＯ８ｔ−ランジスタＴ６１のＰ−ウェルに電位が加
わらないため、バルクによるリーク電流がなく、従って
全体の低消費電流化もできる。In FIG. 2, at least MO8I-transistor T
6/ has the source S and the substrate Sub at the same potential, so there is no back gate effect and low voltage operation is possible, and when the power supply control MOS transistor T3 is off, a potential is not applied to the P-well of the MO8t transistor T61. Therefore, there is no leakage current due to the bulk, and the overall current consumption can therefore be reduced.

以上実施例ではＮ−基板について述べたが逆のＰ−基板
のものも同様である。In the above embodiments, the N-substrate has been described, but the same applies to the opposite P-substrate.

このように本発明はＭＯＳトランジスタを電源制御用ス
イッチとして用いるものにおいて、被電源制御部を構成
するＣ−ＭＯＳトランジスタのうち電源制御用ＭＯＳト
ランジスタと同導電型チャネルのＭＯＳトランジスタに
ついて、少なくとも一部のＭＯＳトランジスタのサブス
トレートを電源制御用ＭＯＳトランジスタのドレインに
接続することによって、簡単な構成でバックゲート効果
によるみかけ上のスレッシュホールド電圧の上昇を防止
し、それによって低電圧動作が可能になり、また電源制
御用ＭＯＳトランジスタのオフを利用してバルクとウェ
ル間のＰＮ接合でのリーク電流の発生を防止することが
でき、低電圧及び低消費電力型の電源制御回路を得るこ
とができる。In this way, the present invention uses a MOS transistor as a power supply control switch, in which at least some of the MOS transistors having the same conductivity type channel as the power supply control MOS transistor among the C-MOS transistors constituting the power supply controlled section are By connecting the substrate of the MOS transistor to the drain of the power supply control MOS transistor, an increase in the apparent threshold voltage due to the back gate effect can be prevented with a simple configuration, thereby enabling low voltage operation. It is possible to prevent leakage current from occurring at the PN junction between the bulk and the well by turning off the power supply control MOS transistor, and it is possible to obtain a power supply control circuit with low voltage and low power consumption.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例を示す回路図、第２図は本発明の一実施
例を示す回路図である。 Ｔ・・・・・・電源端子、Ｃ１・・・・・・電源制御回
路、Ｃ２・・・・・・被電源制御回路、Ｔ３・・・・・
・電源制御用ＭＯＳトランジスタ。FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. T: power supply terminal, C1: power supply control circuit, C2: power supply controlled circuit, T3: power supply control circuit
・MOS transistor for power supply control.

Claims (1)

【特許請求の範囲】[Claims] １ 電源制御部と、Ｃ−ＭＯＳトランジスタ回路で構成
された被電源制御部と、上記電源制御部の出力がゲート
に与えられて被電源制御部との間に直列に接続され、且
つ基板と同導電型チャネルからなる電源制御用ＭＯＳト
ランジスタと、上記被電源制御部に含まれた電源制御用
ＭＯ８）ランジスタと同導型チャネルからなるＭＯＳト
ランジスタのサブストレートを、電源制御用ＭＯ８）ラ
ンジスタのドレインに接続する配線とを備えてなること
を特徴とするＣ−ＭＯ８回路。1. A power supply control unit, a power supply control unit composed of a C-MOS transistor circuit, and the output of the power supply control unit being applied to the gate and connected in series with the power supply control unit, and A power control MOS transistor having a conductivity type channel and a substrate of the power control MO8) transistor included in the power control target section and a MOS transistor having the same conductivity type channel as the drain of the power supply control MO8) transistor. A C-MO8 circuit characterized by comprising connecting wiring.
JP52037076A 1977-03-31 1977-03-31 C-MOS circuit Expired JPS5935217B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52037076A JPS5935217B2 (en) 1977-03-31 1977-03-31 C-MOS circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52037076A JPS5935217B2 (en) 1977-03-31 1977-03-31 C-MOS circuit

Publications (2)

Publication Number Publication Date
JPS53122354A JPS53122354A (en) 1978-10-25
JPS5935217B2 true JPS5935217B2 (en) 1984-08-27

Family

ID=12487452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52037076A Expired JPS5935217B2 (en) 1977-03-31 1977-03-31 C-MOS circuit

Country Status (1)

Country Link
JP (1) JPS5935217B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57118442A (en) * 1981-01-14 1982-07-23 Toshiba Corp Semiconductor integrated circuit
JPS59153331A (en) * 1983-02-21 1984-09-01 Toshiba Corp Semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MOSFET IN CIRCUIT DESIGN *

Also Published As

Publication number Publication date
JPS53122354A (en) 1978-10-25

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