JPS6334653B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor complementary circuit, and more particularly to a field effect transistor complementary circuit suitable for circuits such as watches, calculators, and microprocessors requiring speed, which require low power supplies.

Complementary circuits using currently used insulated gate field effect transistors (IGFETs), so-called
CMOS circuits have the problem that a considerable amount of leakage current still flows in the gate voltage region slightly lower than the threshold voltage, and that the junction capacitance formed at the junction cannot be ignored. Generally, the threshold voltage is a constant voltage between source and drain (usually 5V)
the gate voltage required to cause a current of 1 μA to flow between the source and drain, or connect the drain and gate and apply a constant current between the source and drain (usually
The source-drain-gate voltage required to flow 1μA) is used. Here, we will use the former definition.

First, with reference to Figures 1 and 2, the conventional CMOS
Explain the circuit configuration and problems. Figure 1 shows
Figure 2 is a cross-sectional view showing an example of the structure of a CMOS circuit.
It is a circuit diagram showing the connection. This circuit is designed as an inverter.

As shown in Figure 1, first, the concentration is 1×
A P-type P-well with a concentration of ¹ ×10 ¹⁶ atom/cm ³ is placed on an N-type Si single crystal substrate 1 with a concentration of about 1×10 ¹⁵ atom/cm ³
A region or substrate 2 is formed. Next, the source 3 and drain 4 in the P channel region and the guard ring parts 5 and ⁶ in the N channel region are
Create a P ⁺ diffusion of about ^cm3 . N ⁺ diffusion of about 1×10 ²⁰ atoms/cm ³ is created in the source 7, drain 8 and guard ring parts 9 and 10 of the P channel region in the N channel region, and the gate part 11 of these P channel and N channel transistor parts is made. , to 12
A thin insulating film (usually SiO ₂ film) of about 2500 Å is applied. Contact holes 13 are formed where necessary, and circuit connections are made using a conductor such as metal. An inverter circuit as shown in FIG. 2 is formed. Furthermore, if necessary, the CMOS semiconductor element (so-called chip) is completed by covering the surface with a protective film. As is clear from the above explanation and FIG. It is connected to the.

Currently, there is a strong demand for the power supply voltage of watches, calculators, etc. to be as low as possible, and the threshold voltages of P-channel transistors and N-channel transistors must also be kept below 1.0V in absolute value.
Furthermore, there is a strong demand for higher speeds in microprocessors. Known methods for reducing the threshold voltage include lowering the substrate concentration, reducing the thickness of the gate insulating film, and implanting ions of a different type in the substrate into the channel portion of the gate. If the thickness of the gate insulating film is made thinner, the gate portion will be destroyed, so there is a limit to its thickness. Lowering the substrate concentration and implanting ions of different types of impurities into the substrate into the gate channel region are effective in lowering the threshold voltage as defined above, and these and thinning the gate film thickness A combination of methods has been used to effectively lower the threshold.

However, in the method of lowering the substrate concentration or ion-implanting impurities of a different type from the substrate, a considerable current close to 1 μA flows below the threshold voltage. △I _DS / △V _G is also found in the area. FIG. 3 is a graph for explaining this problem. In the figure, the curve shown by a dotted line shows the original characteristic without using the above-mentioned method, while the curve shown by a solid line shows the characteristic when the threshold value is reduced using at least one of the above-mentioned methods. As is clear from this figure, when the gate-source voltage V _GS is zero, a leakage current that is two orders of magnitude larger flows in the case where the threshold value is reduced than in the case where the threshold value is not reduced. Figure 3 is N
Although the channel transistor is shown,
Similarly, in a P-channel transistor, a large leakage current flows if the threshold value is made small when the gate-source voltage V _GS is zero. As a result, total power consumption increases, and in circuits that require retention characteristics, the retention time becomes shorter.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a field effect transistor complementary circuit that can operate at a low power supply voltage without significantly increasing leakage current.

The present invention reduces the threshold voltages of both P-channel and N-channel transistors connected in series, and applies a back gate bias voltage to at least the P-channel transistor to increase the threshold voltage of this transistor. It is characterized in that a signal is commonly supplied to the gates of both transistors connected in series.

Since the threshold values of both the P-channel and N-channel transistors are made small, the operating power supply voltage can be made small. However, simply reducing the threshold value increases the leakage current of both transistors as described above. Therefore, a back gate bias voltage is applied to at least the P channel transistor to increase the threshold value of the transistor. It is well known that when a back bias voltage is applied to a substrate serving as a back gate, the threshold value shifts to become larger in response. In other words, the gate-source voltage
The V _GS vs. drain-source current I _DS characteristic shifts from the characteristic shown by the solid line in FIG. 3 to the characteristic shown by the dotted line. In a field-effect transistor complementary circuit, as is clear from its circuit operation, a signal having a voltage amplitude such that the gate-source voltage V _GS of the transistor is approximately zero or approximately the power supply voltage is supplied to the gate. Therefore, at least for a P-channel transistor, the leakage current when its gate-source voltage V _GS is approximately zero is considerably smaller than that of a transistor whose threshold value is only reduced. Since the complementary circuit has a basic configuration of P-channel and N-channel transistors connected in series, a reduction in the leakage current of the P-channel transistor is equivalent to a reduction in the leakage current of the series-connected circuit. Therefore, it is possible to provide a complementary circuit that can operate at a low power supply voltage while suppressing an increase in leakage current.

Furthermore, as shown in Figure 4, which shows the change in junction capacitance when a reverse bias voltage is applied to a PN junction formed by forming a P-type region in an N-type region, by applying a backgate bias voltage. The junction capacitance of the P-channel transistor becomes smaller. Since the majority carriers of a P-channel transistor are holes, its current driving ability is inferior to that of an N-channel transistor, but since the junction capacitance is smaller, the inferior current driving ability can be compensated for.

Next, while comparing a four-phase complementary shift register circuit (FIG. 6) constructed using a field-effect transistor complementary circuit according to an embodiment of the present invention and a conventional complementary shift register circuit (FIG. 5), explain. The difference between the two circuits is that the substrates of the P-channel transistors 20, 23, 26, and 27 (Fig. 6) are
The difference is that it is connected to V _SS2 and a back bias is applied to the source. In each figure, parts used for the same purpose are designated by the same reference numerals. FIG. 7 is a waveform diagram for explaining the operation of the circuit shown in FIGS. 5 and 6 above. In each circuit, when clock φ, at time M in FIG. 7 is applied, transistors 20 and 21 are turned on. At this time, node A is at V _DD , node B is at V _SS (Fig. 5), V _SS1
(Figure 6). Next, at time N, the clock φ ₂ , ₂
is applied, transistors 24 and 27 are turned on, node C becomes V _DD , and point D becomes V _SS (Fig. 5), V _SS1
(Figure 6).

Therefore, at time O, due to the presence of the input IN, the transistor 22 is turned on and the transistor 23 is turned off, and the terminal voltage of the capacitor C _L connected to the node E is discharged to V _DD . At time point P, the potential V _DD at the node E turns off the transistor 25 and turns on the transistor 26, and the node F at the output terminal OUT becomes at the potential of V _SS and V _SS1 . X
At this point, the clock φ _1,1 causes _the transistor 20,
21 is turned on, and node E becomes V _DD due to the state of input IN.
to V _SS and V _SS1 , respectively. At time Y, the transistors 24 and 27 are turned on by the clocks φ _{2 and 2} , and the potential of OUT F changes from V _SS and V _SS1 to V _DD depending on the state of node E, respectively.

In order to operate such a complementary shift register circuit at a low power supply voltage, if the threshold voltage is lowered by the method described above in connection with FIG. 3, I _DS is large below the threshold voltage, so that The effect of off-state transistors appears. As shown by the dotted line in Figure 7, the voltage changes from V _DD due to leakage current, and when the φ ₂ input at time P should produce an output at the V _SS level shown at F, no output occurs.
There is a possibility that the V _DD level will be maintained.

However, if back bias is applied to the P-channel transistors 20, 23, 26, and 27 as shown in FIG. 6, the leakage current will almost disappear as explained earlier, and such malfunctions can be completely prevented. be done.

Although the embodiment circuits have been shown and explained in detail above, the present invention can be applied not only to the above embodiment circuits but also to all circuits using CMOS transistors.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing an example of the structure of a CMOS circuit.
Figure 2 is a circuit diagram showing the connections, Figure 3 is a graph showing changes in characteristics when changing the threshold voltage through ion implantation, and Figure 4 is a graph showing the relationship between reverse bias voltage and junction capacitance. , Figure 5 shows the conventional 4
6 shows a four-phase shift register configured with back bias according to the present invention, and FIG. 7 shows a circuit for explaining the operation of the circuit shown in FIGS. 5 and 6. FIG. 1...Substrate, 2...P-well, 11, 12...
Gate, 6, 5, 9, 10...guard ring, 2
1, 22, 24, 25...N channel transistor, 20, 23, 26, 27...P channel transistor.

Claims (1)

[Claims] 1. By using at least one of reducing the thickness of the gate insulating film, lowering the substrate concentration, and introducing impurities of different conductivity types into the channel part, the Both thresholds of the channel field effect transistor are reduced, and at least the P
Applying a back gate bias voltage to the P-channel field-effect transistor to increase the threshold value of the P-channel field-effect transistor, and in this state, applying a signal in common to the gates of the P-channel and N-channel field-effect transistors connected in series. A field effect transistor complementary circuit characterized in that: