JPS5933870A - Manufacture of transistor - Google Patents
Manufacture of transistorInfo
- Publication number
- JPS5933870A JPS5933870A JP14360582A JP14360582A JPS5933870A JP S5933870 A JPS5933870 A JP S5933870A JP 14360582 A JP14360582 A JP 14360582A JP 14360582 A JP14360582 A JP 14360582A JP S5933870 A JPS5933870 A JP S5933870A
- Authority
- JP
- Japan
- Prior art keywords
- region
- impurity
- base
- base region
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 5
- 230000003321 amplification Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- -1 cationic ions Chemical class 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 150000002500 ions Chemical group 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000001768 cations Chemical class 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）技術分野
本発明はトランジスタの製造方法、特に高電流増巾率（
ｈｎ）を有するトランジスタの製造方法の改良に関する
。Detailed Description of the Invention (a) Technical field The present invention relates to a method for manufacturing a transistor, particularly a method for manufacturing a transistor with a high current amplification rate (
hn).
（ロ）従来技術
二重拡散型プレーナトランジスタは第１図に示す如く、
コレクタ領域（１）、ベース領域（２）およびエミッタ
領域（３）より構成される。(b) The conventional double diffused planar transistor is as shown in Figure 1.
It is composed of a collector region (1), a base region (2) and an emitter region (3).
斯るプレーナ型ＮＰＮ ）ランジスタではｌ塙が１００
０以上の高ｈ□ トランジスタを得られ難くかった。こ
の理由は高ｈ７アとするためにベース領域（２）の不純
物濃度を低（設定して注入効率を上げると、ベース領域
（２）表面に酸化膜（４）中の陽イオンや界面準位によ
り空乏層や反転層が形成され易くなる。反対にベース領
域（２）の不純物濃度を高くすると、エミッタ領域（３
）の拡散が難しくなり高ｈｖｚを得られない。In such a planar type NPN) transistor, the liter is 100.
It was difficult to obtain a transistor with a high h□ of 0 or more. The reason for this is that when the impurity concentration in the base region (2) is set to a low level to increase the implantation efficiency in order to obtain a high h7A, cations in the oxide film (4) and interface states are formed on the surface of the base region (2). On the other hand, if the impurity concentration of the base region (2) is increased, the emitter region (3) becomes more likely to form.
) becomes difficult to diffuse, making it impossible to obtain high hvz.
（ハ）発明の開示
本発明は斯る欠点に鑑みてなされ、従来の欠点を完全に
除去したトランジスタの製造方法を提供するものである
。本発明はベース領域表面に高不純物領域を形成するこ
とに特徴を有する。(C) Disclosure of the Invention The present invention has been made in view of the above drawbacks and provides a method of manufacturing a transistor that completely eliminates the conventional drawbacks. The present invention is characterized in that a highly impurity region is formed on the surface of the base region.
に）実施例
本発明の第１の工程はシリコン基板０９表面に二重拡散
によりベース領域（イ）およびエミッタ領域０３を形成
することにある（第２図Ａ）。本工程においてベース領
域（１２はボロンの選択拡散によりＰ型に形成され、不
純物濃度は４ Ｘ Ｉ ０１７ＣＩｎ−３以下に設定さ
れ高ｈＦｇを確保する。B) Embodiment The first step of the present invention consists in forming a base region (a) and an emitter region 03 on the surface of a silicon substrate 09 by double diffusion (FIG. 2A). In this step, the base region (12) is formed into a P type by selective diffusion of boron, and the impurity concentration is set to 4×I017CIn-3 or less to ensure a high hFg.
次に本発明の第２の工程はベースおよびエミッタ領域（
１２（１３表面の酸化膜α→を除去し、その表面にＰ型
不純物をイオン注入もしくはデポジションして高不純物
領域００を形成することにある（第２図Ｂ）。本工程は
本発明の最も特徴とする工程であり、べ〜ス領域０２０
表面不軸物濃度をＩ Ｘ １．０”ｆｆ１３以上にして
寄生効果を抑えることを目的とする。Next, the second step of the present invention is the base and emitter regions (
12 (13) The oxide film α→ on the surface is removed and a P-type impurity is ion-implanted or deposited on the surface to form a high impurity region 00 (FIG. 2B). This is the most characteristic process, and the base area 020
The purpose is to suppress parasitic effects by increasing the surface axes concentration to I x 1.0”ff13 or higher.
イオン注入を行う場合は、露出表面に数１００ｔのシリ
コン酸化膜を形成した後、２０ＫｅＶの低い加速電圧で
約１×１０ｄ位注入してやるとベース領域０２の表面不
純物濃度は］、Ｘｌ、０ｃｒｒＬ 以上になる。また
ボロンのデポジションを行う場合は全面にボロングラス
をデポジションした後グラス除去して、その表面をｌＸ
ｌｏＣＴＬ以上にする。When performing ion implantation, after forming a silicon oxide film of several 100 tons on the exposed surface, implanting approximately 1×10 d at a low acceleration voltage of 20 KeV, the surface impurity concentration of base region 02 will be greater than ], Xl, 0 crrL. Become. Also, when performing boron deposition, deposit boron glass on the entire surface, remove the glass, and then
Set it to loCTL or higher.
なお本工程においてエミッタ領域（至）表面にもボロン
が注入されるが、エミッタ領域（ト）は元々１×１０儂
以上の不純物濃度を有しているので、１本発明の第
３の工程はベースおよびエミッタ領域（６）０１表面に
ＣＶＤ法による酸化膜θＱを形成することにある（第２
図Ｃ）。本工程ではＣＶＤ法により低温でシリコン表面
にシリコン酸化膜ＯＱを釣人
５００ ｏ７程度付着１−ろ事により高不純物領域０均
から不純物が酸化膜Ｏｅ中に食われてベース領域０２の
表面不純物濃度が低下する事を防止Ｉ〜ている。In this step, boron is also implanted into the surface of the emitter region (to), but since the emitter region (to) originally has an impurity concentration of 1×10 or more, the third step of the present invention is The purpose is to form an oxide film θQ on the surface of base and emitter region (6) 01 by CVD method (second
Figure C). In this step, a silicon oxide film OQ is deposited on the silicon surface at a low temperature by the CVD method at a low temperature. Preventing the decline.
（ホ）効果
本発明に依れば、ベース領域０２全体の不純物濃度を低
く設定でき、かつベース領域（イ）表面のみに高不純物
領域θつを形成するので、高り、、 ）ランジスタを大
量製造できる。またベース領域０力表面も陽イオンや界
面準位の影響を受けず高信頼性の高り、２トランジスタ
を得ることができる。(e) Effects According to the present invention, the impurity concentration of the entire base region 02 can be set low, and the high impurity regions θ are formed only on the surface of the base region (a), so that the impurity concentration of the transistors is large. Can be manufactured. Furthermore, the base region's zero-force surface is not affected by cations or interface states, resulting in high reliability and two transistors can be obtained.
第１図は従来例を説明する断面図、第２図Ａ、Ｂ、Ｃは
本発明の一実施例を説明する断面図である。
０］）は半導体基板、０２はベース領域、θ１はエミッ
タ領域、０→は酸化膜、θ→は高不純物領域、θＱはＣ
ＶＤ法による酸化膜である。
出願人 三洋電機株式会社 外１名
第Ｕ図FIG. 1 is a sectional view illustrating a conventional example, and FIGS. 2A, B, and C are sectional views illustrating an embodiment of the present invention. 0]) is the semiconductor substrate, 02 is the base region, θ1 is the emitter region, 0→ is the oxide film, θ→ is the high impurity region, θQ is C
This is an oxide film formed by the VD method. Applicant Sanyo Electric Co., Ltd. and 1 other person Figure U
Claims (1)
を低く設定したトランジスタにおいて、ベースおよびエ
ミッタ領域を二重拡散した後肢ベースおよびエミッタ領
域表面の酸化膜を除去し、前記ベースおよびエミッタ領
域表面に選択的に前記ベース領域と同導電型を与える不
純物をイオン注入もしくはデポジションし、然る後前記
ベースおよびエミッタ領域表面をＣＶＤ法により形成し
た酸化膜で被覆することを特徴とするトランジスタの製
造方法。1. In a transistor in which the impurity concentration of the base region is set low in order to obtain a high current amplification rate, the oxide film on the surface of the base and emitter regions of the base and emitter regions that have been double-diffused is removed, and the oxide film on the surface of the base and emitter regions is removed. A transistor characterized in that an impurity that imparts the same conductivity type as the base region is selectively ion-implanted or deposited on the surface, and then the surfaces of the base and emitter regions are covered with an oxide film formed by a CVD method. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14360582A JPS5933870A (en) | 1982-08-18 | 1982-08-18 | Manufacture of transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14360582A JPS5933870A (en) | 1982-08-18 | 1982-08-18 | Manufacture of transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5933870A true JPS5933870A (en) | 1984-02-23 |
Family
ID=15342612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14360582A Pending JPS5933870A (en) | 1982-08-18 | 1982-08-18 | Manufacture of transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933870A (en) |
-
1982
- 1982-08-18 JP JP14360582A patent/JPS5933870A/en active Pending
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