JPS5930341B2 - Encoding clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention shares a DA converter as a local decoder in an encoder with a DA converter of a decoder in a time-sharing manner, and
The present invention relates to an encoding clock generation circuit for a code decoder that performs non-uniform encoding.

In a general encoder, analog signals are sampled and held and encoded in accordance with clocks having uniform time intervals using a successive approximation feedback type AD converter configuration.

However, depending on the time allocated for one encoding, the characteristics of the DA converter, etc., it may be necessary to employ non-uniform encoding clocks.

Furthermore, an economical code decoder (CODEC) has already been proposed in which a DA converter as a local decoder in an encoder is shared in a time-sharing manner as a DA converter for decoding.

Such code decoders are often used for encoding and decoding when transmission and reception are performed asynchronously, and even within one encoding period, an interrupt signal may be generated due to the arrival of a received signal. In addition, the DA converter as a local decoder is switched to operate as a DA converter of the decoder, and is switched again to operate as a local decoder upon completion of decoding of the received signal.

By switching the A converter in this way, the DA converter is shared for encoding and decoding, and if the encoding clocks are at uniform intervals, switching of the DA converter is not possible. However, in the case of non-uniform intervals, when re-applying, the order must follow the order before the interruption, so the encoded clock generation circuit is complicated. It becomes something that must be configured.

It is an object of the present invention to simplify the configuration of the encoding clock generation circuit of the code decoder as described above, and also to make it possible to arbitrarily change the non-uniform pattern of the encoding clock.

Examples will be described in detail below.

FIG. 1 is a block diagram of the main part of the code decoder. An analog signal A1 for transmission is sampled by a sample-and-hold circuit SH, held by a hold capacitor, etc., and applied to a comparator COMP.

Also, the output of the comparator COMP is applied to the memory logic circuit ML, and the next data to be compared is sent to D via the selection circuit SEL.
A converter is added to the DAC.

This memory logic circuit ML operates according to the encoding clock CDCL and outputs the encoding signal DT.

The received signal DI is converted into a parallel signal and applied to the selection circuit SEL, and an interrupt signal 4WR is generated by detecting the arrival of the received signal DI.
is applied to the selection circuit SEL, the received signal DI is selected and applied to the DA converter DAC, and the DA conversion output becomes the received analog signal AT.

Further, the application of the encoding clock CDCL is interrupted by the interrupt signal WR, and the memory logic circuit ML retains the contents at the time when the encoding operation was interrupted.

FIG. 2 is a block diagram of an embodiment of the encoding clock CDCL generation circuit, and the m-phase lock generator mCL generates the m-phase clocks a1 to am shown in FIG. 3, for example.
am is output.

τ2 to τm are clocks a2 to am with respect to clock a1
, and T indicates the clock cycle of each phase.

These m-phase locks are added to selector 5ELT,
The clock selected by the output of the decoder DEC is output as the encoded clock CDCL.

The counter CUNT is reset by using a reset signal R8T, which indicates the delimitation of one word of the encoded signal, and is counted up at the falling edge of the encoding clock CDCL.

Note that the reset signal R8T is generally generated when the sample and hold circuit SH changes from the sample mode to the hold mode.

The count contents of the counter CUNT are decoded by the decoder DEC and added to the selector 5ELT. For example, the count contents of the counter CUNT are 0, 2, 4.
．． . . . when the clock a1 is set to 1, 3, 5, . ...
If the decoder DEC is configured to select clock a3 when , then encoding clocks with non-uniform intervals will be obtained, as shown by CDCL in FIG.

Figure 4 shows that when m of the m-phase lock is set to 2,
One word consists of 8 bits, and the interval of the encoding clock CDCL is set to T2 after entering the hold mode. T.I., T.
2. T2. TI, T2. This shows a time chart when the clock is set to T2°T2, and the clock a1. a2. each has a period of T2, clock a1 and clock a2 have an interval of T1, and the sampling mode in the sample and hold circuit is "1" and the hold mode is "0", as shown in S&H. , when the hold mode is entered, the reset signal R8T is applied to the counter CUNT, and the count content of the counter CUNT becomes O as shown by CT.

The decoder DEC is the count content CT of the counter CUNT.
When is 0, 4, 5, 6.7, clock a1 is 1, 2
, 3, a decode output that selects the clock a2 is obtained.The counter CUNT counts up each time the encoded clock CDCL is output, and when the count reaches 8, the decode output of the decoder DEC is obtained. clock a1. a2 is blocked in selector 5ELT.

As mentioned above, since the next state is determined at the trailing edge of the encoding clock CDCL, the problem of generation of excessively small pulses that often occur in ordinary decoders is solved, and the encoding clock CDCL determines the next state. For an interrupt signal that is applied asynchronously to the signal, it is sufficient to provide an inhibit gate 1NH as in the embodiment shown in FIG.

In FIG. 5, the same reference numerals as in FIG. 2 indicate the same parts, and an interrupt signal WR is applied as an inhibit input to an inhibit gate INH.

Figure 6 shows a time chart when there is an interrupt.
This corresponds to the time chart shown in FIG.

When the count content CT of the counter CLINT is 2, if the interrupt signal WR suddenly becomes 1'' due to the arrival of a received signal, the encoding clock CDCL is inhibited by the inhibition gate INH, and therefore the count content of the counter CUNT remains 2 and changes. I'll end up not doing it.

Then, when the decoding of the received signal is completed, the interrupt signal WR becomes "0".
”, the count content CT of counter CUNT is 2.
The clock a2 is selected in response to the encoding clock C
Becomes DCL.

That is, after the time T2+α, the encoding clock CDCL with predetermined non-uniform intervals is outputted again.

In the above embodiment, when the interrupt signal WR becomes "1", the inhibit gate INH inhibits the output of the encoding clock CDCL and accordingly inhibits the counter CUNT from counting up. Including signal WR is '1''
Therefore, it is also possible to adopt a configuration in which the m-phase locks a1 to am applied to the selector 5ELT are prohibited or the output of the decoder DEC is prohibited.

As explained above, in code decoding using non-uniform encoded clocks, the present invention selects a clock of a predetermined phase from a plurality of phase clocks as an encoding clock according to the count contents of the counter CUNT. A non-uniform coding clock is generated by incrementing the counter CUNT at the trailing edge of the coding clock, and the non-uniform pattern can be easily changed by changing the configuration of the decoder DEC that decodes the count contents of the counter CUNT. be able to.

Furthermore, when a received signal arrives, the DA converter is used as a decoder, and the output of the encoding clock is prohibited, and the operation as an encoder is interrupted. Since counting up is prohibited, when operation as an encoder is restarted, non-uniform encoding clocks will be output in accordance with the order from before the interruption.

That is, even if decoding is interrupted in the middle of one encoding period, encoding using the non-uniform encoding clock will be performed in a predetermined order after the interruption.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the main part of the encoder, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of its operation, and Fig. 4 is a diagram of the encoding of an 8-bit configuration. FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is a diagram explaining its operation. mCL is m-phase clock generator, CUNT is counter, D
EC is a decoder, 5ELT is a selector, CDCL is an encoding clock, INH is an inhibit gate, and WR is an interrupt signal.

Claims (1)

[Claims] 1. In a circuit that generates encoding clocks with non-uniform intervals in a code decoder that uses a DA converter as a local decoder in an encoder in a time-sharing manner as a DA converter in a decoder, multiple phase clocks are used. a multi-phase clock generator that generates the encoded clock, a counter that counts up at the trailing edge of the encoded clock, and a circuit that selects a predetermined phase clock from the multiple phase clocks as the encoded clock according to the count contents of the counter. and a circuit for inhibiting the count-up of the counter and the output of the encoding clock by an interrupt signal for use as the DA converter.