JPS5929141B2 - Manufacturing method for semiconductor devices - Google Patents

Abstract

PURPOSE:To reduce forward voltage drop by providing crevasses on the N<+> surface layer of a Si substrate and brazing a W or Mo plate by using an Al brazing material.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for brazing a tungsten plate or a molybdenum plate to an N+ type surface layer of a silicon substrate using an aluminum brazing material.

A metal plate made of tungsten or molybdenum is contacted on one or both sides of the silicon substrate to improve its mechanical properties.

On the one hand, this metal plate also serves as an electrode.
Aluminum is widely used as a brazing material because of its good electrical conductivity and strong adhesive properties. however,
The N+ surface of a silicon substrate generally has very coarse hemispherical protrusions with a high phosphorus concentration as a result of diffusing phosphorus at a very high concentration in order to eliminate the regrowth layer. When aluminum is bonded to the surface, a P-type regrowth layer is generated on the entire surface of the silicon, resulting in an undesirable result in which the forward voltage drop increases. In order to solve these drawbacks, conventional methods have been used such as reducing the thickness of the aluminum or rapidly cooling the joint portion during joining, but these methods have not yet been sufficiently effective. An object of the present invention is to provide a method for manufacturing a semiconductor device suitable for reducing forward voltage drop.

The present invention is characterized by the fact that a regrowth layer is difficult to grow in crevasses containing phosphorus, and by using an At-Si eutectic alloy as a brazing material, it is possible to bond at a lower temperature than when using pure Al. This is a combination of two advantages: the absolute amount of Si that dissolves into the brazing filler metal is reduced, and the amount that grows as a regrowth layer is also reduced. A crevasse with a high phosphorus concentration can be easily formed in the following manner. First, an alkaline solution containing 0.10% NaOH as a main component is kept at 40° C., silicon is immersed in it, and etched for 5 hours to form a crevasse on the surface. Next, phosphorus diffusion is performed using PoCl3 (or red phosphorus may be used) as an impurity source, and the material is again immersed in alkaline solution for 0.5 to 51 hours to restore the crevasses to their original shape. In this case, the phosphorus concentration is 1019 to 1021 atoms/c (
$■! ) range is fine. Further, the Al-Si eutectic alloy brazing material can be easily made into foil by melting and rolling. Regarding the adhesion temperature between the N+ type surface layer of semiconductor Si and the Al-Si eutectic alloy foil, the melting point of the Al-Si eutectic alloy is 577°C, which is considerably lower than the melting point of Al, which is 660°C. . Therefore, even if the bonding temperature is considerably lowered, the adhesiveness will not deteriorate. Examples of the present invention will be described in detail below using drawings and micrographs.

In Figure 1, 1 is a metal plate (W or MO) 2 is A
l-Si eutectic alloy filler metal, 3 is crevasse, 4 is N+ type S
il5 is N-type Si.

FIG. 2 is a cross-sectional view of such a product after it has been heat-bonded.

2a is an At-Si alloy layer, and 6 is a regrown layer.

As shown in the figure, the regrowth layer is finely fragmented, but if the ratio of the total fragmented area to the total length is expressed as a breakage rate of 11+12+13+14 (1 × 100), L
Discontinuation rate of regrowth layer and N+ type S! The regrowth layer formed on top (
The increase in forward voltage drop caused by the P-type inversion layer (
(expressed as ΔFVD) is as shown in FIG.

In other words, as the discontinuity rate increases, the forward voltage drop decreases; for example, if the discontinuity rate is 10%, △FV
It is clear that D has a very small value of 0.2V, and the number of product defects is reduced. Therefore, we decided to compare the synergistic effects of crevasse and Al-Si eutectic alloy brazing filler metal based on the breakage rate. Fig. 4 shows the N+ side of a semiconductor Si having a conventional surface shape (l in the figure) and a semiconductor S1 having a crevasse (in the figure) and an MO plate using a brazing material.
It shows the relationship between bonding temperature and breakage rate when bonding is performed using l-S1 eutectic alloy foil.

Figure 5 shows the conventional product (a) and the N+ with crevasse.
A scanning electron micrograph of the type Si surface (b) is shown. In all cases, the breakage rate tends to decrease as the heating temperature increases, but it can be seen that the breakage rate is clearly higher when using the N+ surface with crevasses compared to the conventional product.

Figure 6 shows the cross-sectional view a) of the N-face with a crevasse and the Al-Sl eutectic alloy after adhesion, and the N+ face of the conventional product and the Al-
A cross-sectional photograph (b) after adhesion with a Si eutectic alloy is shown. It can be seen that the regrowth layer is more finely broken in the former case than in the latter case. The reason why the breakage rate increases due to the synergistic effect of the Al-Si eutectic alloy foil and the crevasses on the N+ surface is thought to be as follows. That is, since the crevasse has a high concentration of phosphorus due to diffusion, Si preferentially dissolves into the Al-Si alloy during heating, and the crevasse is maintained even by heating.

On the other hand, as can be seen from the Al-Si secondary phase diagram in Figure 7, the Al-Sl eutectic alloy has a lower melting point of 577°C than Al.
Therefore, even if the bonding temperature is set to 660° C. or lower, the adhesion between the metal plate and S1 is good. When using pure Al solder, the heating temperature must be set to 700°C or higher, otherwise the adhesion will deteriorate, so between the former and the latter, the absolute amount of Si dissolved into the filler metal during bonding is only the symbol △S shown in the figure. It makes a difference. Now, in the case of solidification, the regrowth layer is difficult to grow in crevasses, so it grows first in protrusions. and,
If there is a large amount of Si dissolved in the brazing filler metal, it will eventually grow into a crevasse, but in this case, the dissolved Si
Because the amount is so small, it rarely grows into crevasses.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a front view showing the state after adhesion. FIG. 3 is a graph showing the relationship between the breakage rate and ΔFVD. FIG. 4 is a graph showing the synergistic effect between the crevasse and the Al-Si eutectic alloy solder. FIG. 5 is a scanning electron micrograph of the conventional product and the N+ surface with a crevasse. FIG. 6 is a micrograph showing the cross-sectional structure after adhesion. Figure 7 shows Al-S
i is a binary state diagram. 1...Metal plate, 2...
...Al-Si eutectic alloy brazing material, 3...Crevasse, 4...N+ type Sil5...N type Sil6...Regrowth layer.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor element in which a metal plate having a coefficient of thermal expansion similar to that of the semiconductor substrate is brazed to the surface layer of a semiconductor substrate having an N^+ type surface layer in which phosphorus is diffused. A method for manufacturing a semiconductor element, which comprises providing a crevasse in an N^+ type surface layer of a semiconductor substrate, and brazing the semiconductor substrate and a metal plate using a eutectic alloy of aluminum and silicon as a brazing material. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is silicon and the metal plate is tungsten or molybdenum.