JPS5856255B2 - semiconductor element - Google Patents
semiconductor elementInfo
- Publication number
- JPS5856255B2 JPS5856255B2 JP7432976A JP7432976A JPS5856255B2 JP S5856255 B2 JPS5856255 B2 JP S5856255B2 JP 7432976 A JP7432976 A JP 7432976A JP 7432976 A JP7432976 A JP 7432976A JP S5856255 B2 JPS5856255 B2 JP S5856255B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- present
- layer
- phosphorus
- voltage drop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はシリコン基体のN十面に金属支持板を接着して
なる構造の半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor element having a structure in which a metal support plate is adhered to the N0 surface of a silicon substrate.
シリコン基体はその機械的性質を良好にするため片面あ
るいは両面にタングステンあるいはモリブデンからなる
金属支持板を接着する。A metal support plate made of tungsten or molybdenum is bonded to one or both sides of the silicon substrate in order to improve its mechanical properties.
この金属支持板は一方ではまた電極の役割もはたしてい
る。On the one hand, this metal support plate also plays the role of an electrode.
接着材としてはアルミニウムがその良好な電気伝導性、
強力な接着性から広く使われている。Aluminum is used as an adhesive because of its good electrical conductivity,
Widely used due to its strong adhesive properties.
しかしながら、シリコン基体のN十面は一般に非常に粗
大化した、P濃度の高い半球状の突起を持っているため
、N十面にアルミニウムを接合すると、アルミニウムと
N+シリコンとの反応によりP型の再成長層がN十面の
全面に生じて、順方向電圧降下が大きくなるという好ま
しくない結果を生じる。However, since the N0 surface of a silicon substrate generally has very coarse hemispherical protrusions with high P concentration, when aluminum is bonded to the N0 surface, the reaction between aluminum and N+ silicon causes P-type formation. A regrowth layer is generated over the entire surface of the N10 plane, resulting in an undesirable result that the forward voltage drop becomes large.
このような欠点を解決するために、従来から、アルミニ
ウムの厚さを薄くするとか、接合の際に接合部を急冷す
るとか、またはN型表面層にりん、ひ素等の5価元素を
多量に入れるとかの方法がとられてきたが、未だ十分な
効果が得られてない。In order to solve these drawbacks, conventional methods have been to reduce the thickness of aluminum, rapidly cool the joint during joining, or add large amounts of pentavalent elements such as phosphorus and arsenic to the N-type surface layer. Methods have been taken to include it, but sufficient effects have not yet been achieved.
本発明の目的は、順方向電圧降下を小さくするのに適し
た構造の半導体素子を提供するにある。An object of the present invention is to provide a semiconductor element having a structure suitable for reducing forward voltage drop.
本発明は、シリコン基体のN十面に生成する再成長層を
とぎらせれば順方向電圧降下が小さくなるという観点に
立ち、再成長層をとぎらせることのできる構造を究明し
たもので、基本的な着想はりんを含むフレバスには再成
長層が成長しにくいことを見出したことにある。The present invention is based on the viewpoint that if the regrowth layer generated on the N0 surface of the silicon substrate is stopped, the forward voltage drop will be reduced, and a structure that can stop the regrowth layer has been investigated. The basic idea was that it was found that regrowth layers are difficult to grow in flea baths that contain phosphorus.
りん濃度の高いフレバスは赤りんをシリコン基体のN十
面に拡散させることによって容易に形成することができ
る。A flea bath with a high phosphorus concentration can be easily formed by diffusing red phosphorus into the N0 surface of a silicon substrate.
フレバスの数は、赤りんの量と温度および拡散時間を調
整することによって調節される。The number of flavours is controlled by adjusting the amount of red phosphorus and the temperature and diffusion time.
一例として赤りんの量を3.6〜4.6gにした場合に
は1220℃で1時間、さらに1250℃で4時間りん
拡散を行ない、拡散の際に生じたりんガラスを除去して
から再度3.6〜4.6gの赤りんを同じ条件で拡散さ
せれば、シリコン基体のN十面に1crfL当り300
個以上のフレバスを設けることができる。As an example, when the amount of red phosphorus is 3.6 to 4.6 g, phosphorus diffusion is performed at 1220°C for 1 hour and then at 1250°C for 4 hours, and the phosphorus glass produced during the diffusion is removed and then re-diffused. If 3.6 to 4.6 g of red phosphorus is diffused under the same conditions, 300 g of red phosphorus per 1 crfL is diffused on the N10 surface of the silicon substrate.
More than one frebas can be provided.
また赤りんを13.8gにする場合には1160℃で1
時間、さらに1250℃で4時間拡散させればICrr
L当り300個以上のフレバスを設けることができる。In addition, when making 13.8g of red phosphorus, 1 at 1160℃
ICrr if further diffused for 4 hours at 1250℃
300 or more flebaths can be provided per L.
フレバス数を350個、500個及び650個形成する
場合の条件の一例を次表に示す。An example of conditions when forming 350, 500, and 650 frevases is shown in the following table.
本発明によるシリコン基体のN平面にりん濃度の高いフ
レバスを設けたものを用いれは、アルミニウムの接着材
は合金元素を入れなくてもすむようになるので、接着性
が低下しないという利点も得られる。When the silicon substrate according to the present invention is provided with a high-phosphorus-concentration frebus on the N-plane, there is no need to add alloying elements to the aluminum adhesive, so there is an advantage that the adhesiveness does not deteriorate.
以下本発明の実施例について詳細に説明する。Examples of the present invention will be described in detail below.
第1図は再成長層のとぎれ率(再成長層の成長していな
い所の割合)と△FVD(再成長層に起因する電圧降下
の増大)との関係を表わしている。FIG. 1 shows the relationship between the discontinuity rate of the regrown layer (ratio of areas where the regrown layer does not grow) and ΔFVD (increase in voltage drop due to the regrown layer).
とぎれ率が増大するにつれて△FVDが低くなることが
わかる。It can be seen that as the breakage rate increases, ΔFVD decreases.
第2図a、bに本発明になるシリコン基体のN十表面形
状を示す。Figures 2a and 2b show the surface shape of the silicon substrate according to the present invention.
この図aはN+衣表面500倍に拡大して縦52μm1
横66μmの部分を示している。This figure a is enlarged 500 times on the N+ coating surface and has a vertical length of 52 μm1.
A 66 μm horizontal portion is shown.
この表面におけるICr/Lあたりの平均フレバス数は
、515個であり、後述するように従来素子に比べて多
いことがわかる。The average number of freckles per ICr/L on this surface is 515, which is found to be larger than that of the conventional element, as will be described later.
第3図は1cr/′Lあたりのフレバスの数と再成長層
のとぎれ率との関係を表わしている。FIG. 3 shows the relationship between the number of fleas per 1 cr/'L and the breakage rate of the regrowth layer.
明らかにフレバスの数が増大するにつれて再成長層のと
ぎれ率は増大することがわかる。It is clearly seen that as the number of flavours increases, the breakage rate of the regrowth layer increases.
従来の半導体素子は△FVDが0.3〜0.4であるか
ら、この値は第1図から再成長層のとぎれ率が約2係で
得られることがわかる。Since a conventional semiconductor device has a ΔFVD of 0.3 to 0.4, it can be seen from FIG. 1 that this value can be obtained at a rate of discontinuity of the regrown layer of about 2.
また、再成長層のとぎれ率を2%以上にするには第3図
によりフレバスの数を1crI′L当り300個以上に
すればよいことがわかる。Furthermore, it can be seen from FIG. 3 that in order to increase the breakage rate of the regrown layer to 2% or more, the number of flavours should be increased to 300 or more per 1 crI'L.
第4図は本発明の一実施例を示す写真で、aはシリコン
基体のN+面にアルミニウムを5μm蒸着したものの走
査電顕写真である。FIG. 4 is a photograph showing an embodiment of the present invention, and a is a scanning electron micrograph of a silicon substrate with aluminum deposited to a thickness of 5 μm on the N+ surface.
bはaの状態のものを純窒素雰囲気中で720’Cで加
熱接着後、アルミニウムーシリコン共晶合金をエッチオ
フしたあとの走査電顕写真である。b is a scanning electron micrograph of the state shown in a after heat bonding at 720'C in a pure nitrogen atmosphere and after etching off the aluminum-silicon eutectic alloy.
シリコン基体のN平面にはフレバスが多数認められる。Many frebuses are observed on the N plane of the silicon substrate.
Cは再成長層を断面と平面から同時に写した写真であり
、くぼみが再成長層1の成長してない所であることを考
慮すると、フレバスには再成長層が成長しないことが明
らかである。C is a photograph showing the regrowth layer from both the cross section and the plane. Considering that the depression is the area where regrowth layer 1 has not grown, it is clear that the regrowth layer does not grow on the frebas. .
符号2はシリコン基体のN+面である。Reference numeral 2 represents the N+ surface of the silicon substrate.
本発明による半導体素子および従来の半導体素子を用い
てガラスダイオードを組立て、順方向電圧降下値を測定
した。Glass diodes were assembled using semiconductor devices according to the present invention and conventional semiconductor devices, and forward voltage drop values were measured.
本発明の半導体素子は1cr/L当りのフレバスの数が
約500個である。The semiconductor device of the present invention has approximately 500 frebus per 1 cr/L.
従来のものは順方向電圧降下値が1.6〜2.4■の範
囲でばらつき、平均が1.8■であったが、本発明の実
施例によるものは1.4〜1.5■の狭い範囲でばらつ
いたにすぎず、平均値も約1.45Vであって、従来の
ものにくらべると著しく小さかった。In the conventional device, the forward voltage drop value varied in the range of 1.6 to 2.4 ■, with an average of 1.8 ■, but in the case of the embodiment of the present invention, the forward voltage drop value varied in the range of 1.6 to 2.4 ■. It only varied within a narrow range, and the average value was about 1.45V, which was significantly smaller than the conventional one.
このように、本発明の半導体素子は再成長層がとぎれて
生成する。In this manner, the semiconductor device of the present invention is produced with the regrowth layer interrupted.
したがって、順方向電圧降下を小さくすることができる
。Therefore, forward voltage drop can be reduced.
第1図は再成長層のとぎれ率とΔFVDとの関係を示す
特性図、第2図a、l)は本発明の実施例でシリコン基
体のN平面形状を示す写真、第3図はフレバスの数と再
成長層のとぎれ率との関係を示す特性図および第4図a
、b、cは本発明の実施例を示す写真である。
符号の説明、1・・・・・・再成長層、2・・・・・シ
リコン基体のN平面。Fig. 1 is a characteristic diagram showing the relationship between the discontinuity rate of the regrown layer and ΔFVD, Fig. 2 a, l) are photographs showing the N-plane shape of the silicon substrate in an example of the present invention, and Fig. 3 is a characteristic diagram showing the relationship between the breakage rate of the regrown layer and ΔFVD. Characteristic diagram showing the relationship between the number and the breakage rate of the regrowth layer and Fig. 4a
, b, and c are photographs showing examples of the present invention. Explanation of symbols: 1...Regrowth layer; 2...N plane of silicon substrate.
Claims (1)
ものにおいて、上記シリコン基体のN十面にP濃度の高
いフレバスを1crrL当り300個以上設けたことを
特徴とする半導体素子。 2 接着材がアルミニウムからなる特許請求の範囲第1
項記載の半導体素子。[Scope of Claims] 1. A metal support plate is bonded to the N0 surface of a silicon substrate, characterized in that 300 or more frebus having a high P concentration are provided per 1 crrL on the N1 surface of the silicon substrate. semiconductor elements. 2 Claim 1 in which the adhesive is made of aluminum
Semiconductor device described in section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7432976A JPS5856255B2 (en) | 1976-06-25 | 1976-06-25 | semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7432976A JPS5856255B2 (en) | 1976-06-25 | 1976-06-25 | semiconductor element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS53973A JPS53973A (en) | 1978-01-07 |
JPS5856255B2 true JPS5856255B2 (en) | 1983-12-14 |
Family
ID=13543957
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7432976A Expired JPS5856255B2 (en) | 1976-06-25 | 1976-06-25 | semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5856255B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2640082B1 (en) * | 1988-12-07 | 1991-03-29 | Telemecanique | SYMMETRIC POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
-
1976
- 1976-06-25 JP JP7432976A patent/JPS5856255B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS53973A (en) | 1978-01-07 |
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