JPS5928285A - キヤツシユバツフア制御装置 - Google Patents

キヤツシユバツフア制御装置

Info

Publication number
JPS5928285A
JPS5928285A JP57135313A JP13531382A JPS5928285A JP S5928285 A JPS5928285 A JP S5928285A JP 57135313 A JP57135313 A JP 57135313A JP 13531382 A JP13531382 A JP 13531382A JP S5928285 A JPS5928285 A JP S5928285A
Authority
JP
Japan
Prior art keywords
circuit
cache buffer
tag memory
column
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57135313A
Other languages
English (en)
Japanese (ja)
Other versions
JPS629943B2 (enrdf_load_stackoverflow
Inventor
Hiroyuki Nishimura
西村　弘行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57135313A priority Critical patent/JPS5928285A/ja
Publication of JPS5928285A publication Critical patent/JPS5928285A/ja
Publication of JPS629943B2 publication Critical patent/JPS629943B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57135313A 1982-08-03 1982-08-03 キヤツシユバツフア制御装置 Granted JPS5928285A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57135313A JPS5928285A (ja) 1982-08-03 1982-08-03 キヤツシユバツフア制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57135313A JPS5928285A (ja) 1982-08-03 1982-08-03 キヤツシユバツフア制御装置

Publications (2)

Publication Number Publication Date
JPS5928285A true JPS5928285A (ja) 1984-02-14
JPS629943B2 JPS629943B2 (enrdf_load_stackoverflow) 1987-03-03

Family

ID=15148811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57135313A Granted JPS5928285A (ja) 1982-08-03 1982-08-03 キヤツシユバツフア制御装置

Country Status (1)

Country Link
JP (1) JPS5928285A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61145905A (ja) * 1984-12-19 1986-07-03 Rohm Co Ltd Ｆｍ復調回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61145905A (ja) * 1984-12-19 1986-07-03 Rohm Co Ltd Ｆｍ復調回路

Also Published As

Publication number Publication date
JPS629943B2 (enrdf_load_stackoverflow) 1987-03-03

Similar Documents

Publication Publication Date Title
JP2557174B2 (ja) データのセット位置の予測装置
US5091851A (en) Fast multiple-word accesses from a multi-way set-associative cache memory
US5418927A (en) I/O cache controller containing a buffer memory partitioned into lines accessible by corresponding I/O devices and a directory to track the lines
JPH03142644A (ja) キャッシュメモリ制御方法とこのキャッシュメモリ制御方法を用いたプロセッサおよび情報処理装置
JPS58212694A (ja) メモリシステム
JPS624745B2 (enrdf_load_stackoverflow)
JPS6043540B2 (ja) デ−タ処理装置
US11403226B2 (en) Cache with set associativity having data defined cache sets
US11372648B2 (en) Extended tags for speculative and normal executions
US11734015B2 (en) Cache systems and circuits for syncing caches or cache sets
US20220100657A1 (en) Data defined caches for speculative and normal executions
US6332179B1 (en) Allocation for back-to-back misses in a directory based cache
US11010288B2 (en) Spare cache set to accelerate speculative execution, wherein the spare cache set, allocated when transitioning from non-speculative execution to speculative execution, is reserved during previous transitioning from the non-speculative execution to the speculative execution
JPS604493B2 (ja) マイクロプログラム化データ処理システム
US5590310A (en) Method and structure for data integrity in a multiple level cache system
JP2010033480A (ja) キャッシュメモリおよびキャッシュメモリ制御装置
US20030236947A1 (en) Prevention of conflicting cache hits without an attendant increase in hardware
US5287482A (en) Input/output cache
US6751700B2 (en) Date processor and storage system including a set associative cache with memory aliasing
US20210034369A1 (en) Cache systems for main and speculative threads of processors
US7523290B2 (en) Very high speed page operations in indirect accessed memory systems
US6665787B2 (en) Very high speed page operations in indirect accessed memory systems
JP4047281B2 (ja) キャッシュメモリをメインメモリに同期させる方法
JP2846697B2 (ja) キャッシュメモリ制御装置
JPS5928285A (ja) キヤツシユバツフア制御装置