JPS5928285A - Cache buffer controller - Google Patents

Abstract

PURPOSE:To improve both cache hit factor and tag memory use efficiency, by providing a tag memory control circuit which informs the level information to a clearing circuit in order to dissolve a significant display flag which causes the invalidity. CONSTITUTION:A tag memory control circuit 8 performs an update of a tag memory 2 owing to loading during a mishit as well as the control of invalidity of the memory 2 to an invalidity request K given from another data processor. Either one of levels of an invalidated stack circuit 5 contains a significant display flag P with no access request H nor invalidity request K. In such a case, the control of invalidity is carried out. An access is given to the level of the circuit 5 from a certain level of the flag P in accordance with a prescribed procedure. Then a validated address C and an invalidated column R are delivered to the memory 2 to designate the position to be invalidated, and ''0'' is written to a V bit S at the designated position of invalidation. At the same time, the dissolved level information T is delivered to a clearing circuit 6 for the invalidated level of the circuit 5.

Description

[Detailed description of the invention] The present invention relates to a cache-buffer control device.

In particular, a cache comprising a plurality of data processing devices sharing one main memory (hereinafter referred to as main memory), at least one of these data processing devices holding copies of a plurality of data blocks of the main memory over at least one column per address. The present invention relates to a cache buffer control device in a data processing system including a buffer and a cache buffer control device.

In order to bridge the operational speed gap between a data processing device and a main memory, a method is often adopted in which a cache buffer consisting of a high-speed, small-capacity memory is provided between the two, as is well known. The main memory is divided into blocks of a fixed capacity, the data of multiple blocks among these blocks are held in a cache buffer, and the block address information indicating which data block of the main memory is held in the cache buffer is stored. Write to the tag memory location corresponding to the location determined by the address and column of the cache buffer.

When a data processing device that uses the cache buffer (hereinafter referred to as the data processing device) accesses the cache buffer, it first accesses the tag memory and checks whether the data block containing the access address is held in the cache buffer. Find out. If it is determined that the data is not held (a miss), the data processing device reads the data from the main memory, writes the data block containing this data to the specified position of the cache buffer according to a predetermined procedure, and
It is necessary to commit the block address information for the newly loaded data block to the tag memory location corresponding to the rewrite location in the cache buffer. The probability of a miss is usually designed to be on the order of a few percent.On the other hand, in addition to a central processing unit with a cache buffer, a data processing system equipped with an input/output control unit, a cache, and at least one processor with a buffer are designed. In a data processing system where multiple data processes share the main memory, such as a multiprocessor system that includes It is necessary to reflect the behavior. In other words, if another data processing device performs store access to the main memory, the contents of the tag memory for the relevant cache buffer will be incorrect, so the block address information held at the relevant location in the tag memory will be It becomes necessary to disable it.

This invalidation request occurs more frequently as the number of data processing devices that share the main memory increases, and the probability that it will conflict with an access request from the data processing device increases.

A conventional cache buffer control device of this type includes a tag memory that stores block address information for a data block held by a cache JL buffer at a position determined by an address and column of the cache buffer, and a tag memory that stores block address information for a data block held by the cache JL buffer. (by a predetermined procedure) which column of the cache buffer should be loaded with a new data block from main memory when there is a miss.
There is a request to enable the cache butterf P due to the specified replacement column designation circuit and the execution of store access to the main memory from another data processing device. If valid block address information is held in the tag memory, positional information regarding the holding position of this tag memory and its significance indicating flag (at least across the blocks) are stored, for example, according to a first-in, first-out (FIFO) procedure. The addressable stack circuit is used to update the tag memory along with the data block load (hereinafter referred to as load). and a tag memory control circuit that invalidates the block address information of the tag memory corresponding to the position information according to the FIFO procedure.

In such a conventional configuration, if positional information is meaningfully stored in the stack circuit, the corresponding location in the tag memory is always invalidated, so a ξ hit occurs and the positional information is stored in the stack circuit. Even if the cache buffer location corresponding to the tag memory location is loaded and the tag memory is updated, that location in the tag memory will be invalidated afterwards, and the loaded data block will be invalidated. The first drawback is that it is assumed that the data is not held in the cache buffer, reducing the hit rate.

In addition, invalidating the relevant location in the tag memory after the load is an unnecessary operation, and there is a second drawback that the use efficiency of the tag memory decreases due to such an unnecessary invalidation request.

An object of the present invention is to provide a cache buffer control device that improves hit rate and tag memory usage efficiency.

The device of the present invention includes a plurality of data processing devices that share a main memory, and at least one of these data processing devices has a cache buffer and cache buffer control for holding copies of a plurality of data blocks in the main memory over at least one column per address. and a tag held at a position relative to a position determined by block address information for a data block held by the cache buffer and an address and column of the cache buffer. a memory; a replacement column designation circuit that designates, in a predetermined manner, a column of the cache buffer into which a new data block is to be loaded from the main memory when the cache buffer is hit; and the other data processing. If valid block address information for the data block that is the target of the main memo request from the device is held in the tag memory, the position information regarding the holding position of the tag memory and the significance display flag thereof are stored at least in the label. An addressable stack circuit for storing data, a clearing circuit for clearing the marking significance display flag stored in a separately notified level of the stack circuit, and a spinning cage gourd buffer when the thread is hit. When 9-, the access address to the cache buffer and the column specified by the replacement column designation circuit are compared with all the position information stored in the stack circuit together with the significance flag, and if they match, the level is changed to the corresponding level. a comparison circuit that notifies the clearing circuit of information on the level in order to clear the stored significance display flag; and a comparison circuit that updates the tag memory in conjunction with the loading, and also updates the tag memory at any level of the stack circuit. If there is a significance display flag, the block address information of the tag memory corresponding to the position information with the significance display flag is invalidated according to a predetermined procedure, and the significance display that caused the invalidation is performed. The present invention is characterized by further comprising a tag memory control circuit that notifies the clearing circuit of the level information in order to clear the flag.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention together with a cache memory 9 and a main memory 10.

The main memory 10 has 4, 0 addresses each having 16 addresses.
It is divided into 96K (K=1,024) blocks, and 256 of these 4,096 blocks (data blocks) are held in the cache buffer 9. The cache buffer 9 has 64 addresses each consisting of 4 columns, and is adapted to hold a copy of one data block at each of 256 positions determined by the address and column.

This embodiment includes a switching circuit 1, a tag memory 2, a first comparison circuit 3, a replacement column designation circuit 4, a stack circuit 5,
It is composed of a clear circuit 6, a second comparison circuit 7, and a tag memory control circuit 8.

The switching circuit 1 selects the access address A from the data processing device concerned and the invalidation request address B from another data processing device.
and an internally generated invalidation address C, select only one of these three addresses, divide the block address among them into a first block address D and a second block address E, and output them. . The first block address D and the second block address E are respectively composed of 16 bits and 6 bits, and a total of 22 bits specify one of the 4.096K data blocks. The second block address E becomes an access address for the tag memory 2, replacement column specifying circuit 4, and cache buffer 9, which will be described below.

Tag memory 2 is held by cache buffer 9 256
Four sets of the first block address D for each data block and one bit indicating its validity are held at each of the 64 addresses specified by the second block address E.

The first comparator circuit 3 converts the first block address D output from the switching circuit l into the content held in the tag memory 2 with a valid indication (which is specified by the second block address E that is paired with it) and read out ( 1st block address). As a result of the comparison, if the contents match any of the contents held in the tag memory 2, a hit signal Fl and hit column information F2 are output, and if the contents do not match any of the contents held in the tag memory 2, a miss signal G is output.

The replacement column designation circuit 4 should load a new data block from the main memory IO when there is an access request H and a read command U from the data processing device and the first comparison circuit 3 outputs the ξ hit signal G. Replacement column information J for specifying a column in the cache buffer 9 is outputted in accordance with a predetermined procedure.

When there is an invalidation request K for validating the cache buffer 9B from another data processing device in response to execution of a store access to the main memory 10 from another data processing device, the stack circuit 5 responds to this invalidation request. If a valid first block address for the target data block is held in the tag memory 2, the second block address E
and human column information F2 and their significance display flag P
is stored as position information regarding the holding position.

13- The first request for the data block subject to the invalidation request
Checking whether the block address D is retained in the tag memory 2 is performed by checking the first block address D of the invalidation request addresses B and the second block address of the invalidation request addresses B output by the switching circuit 1 in this case. This is done by comparing the content stored in the tag memory 2 with validity indication, which is accessed and read by Eβ, in the first comparison circuit 3. The stack circuit 5 has four storage spaces (levels).

The clear circuit 6 stores the above information stored in a separately notified level of the four levels of the stack circuit 5.
--Output a clear signal to eliminate the significance display flag P.

When the cache buffer 9 misses, the second comparison circuit 7 transfers the second block address E and the replacement column information J at this time to all the invalidated blocks with the significance display flag P stored in the stack circuit 5. It compares the information M and the invalidation column information N, and if there is a matching level, it outputs matching bell information Q to the clear circuit 6 in order to notify the level.

The tag memory control circuit 8 updates the tag memory 2 upon loading in the event of a miss, and controls the invalidation of the tag memory 2 in response to an invalidation request K from another data processing device.

Invalidation is performed when the significance display flag P is on at any level of the stack circuit 5 and there is neither an access request H nor an invalidation request. It is predetermined from among the levels of the significance display flag P.・Access the level of the stack circuit 5, output the invalidation address C and invalidation column R to the tag memory 2, and set the significance display flag P for the invalidated level of the stack circuit 5. In order to resolve the problem, the resolution level information @T is output to the clear circuit 6.

FIG. 2 shows a detailed circuit diagram of the switching circuit 1, tag memory 2, first comparison circuit 3, and replacement column designation circuit 4 shown in FIG.

The switching circuit 1 is composed of two switches 11 and 12 and a register 13, and the tag memory 2 is composed of a random access memory 21 of 64 words x 68 bits/word.

Selection of one word out of 64 words in random access memory 21 is made by second block address E or invalidation address C. The 64 bits of l@atashi are divided into 4 columns of 17 bits each, and 1 column of υ is further divided into 4 columns of 17 bits each.
The 7 bits are 16 bits representing the first block address D and 1 bit V representing the validity of these 16 bits.
It consists of bit S.

The first comparison circuit 3 is composed of four comparators 31, 32, 33 and 34 and a gate 35, and the replacement column designation circuit 4 is composed of two registers 4t, 42 (each bit configuration), and a gate 35.
4 words x 4 bits/word random access memory 43;
10 gates 44-4D.

, write pulse generator 4E, flip 70 tube 4F
It has a well-known round-tropin shift function.

FIG. 3 shows a detailed circuit diagram of the stack circuit 5, clear circuit 6, second comparison circuit 7, and tag memory control circuit 8 shown in FIG.

The stack circuit 5 includes four registers 54, 55, 56 and 57 each having a 6-bit configuration, four registers 58, 59, 5A and 5B each having a 4-bit configuration, four flip-flops 5c, 5I), 5B, and 5F, a gate 51, a counter 52, and a decoder 53. A set consisting of a 6-bit register, a 4-bit register, and a flip-flop, for example, register 54, register 58, and register 7, located in the same horizontal position.
One level is constituted by the lip-flop 5C.

The clear circuit 6 is composed of four gates 61 to 64 corresponding to each of the four levels of the stack circuit 5, and the second comparison circuit 7 is composed of eight comparators 71 to 78 and bamboo gates 74 to 7E. There is.

The tag memory control circuit 8 includes four switchers 81 to 84, and four switchers 81 to 84.
A bit register 85, nine gates 86 to 8E, etc.
It consists of a write pulse generator 8H, a decoder 17-8F, and a counter 8G.

All registers operate in synchronization with the clock, but the clock input display has been omitted to avoid complicating the drawing.

Next, the operation of this embodiment will be explained for each operation mode.

(At the time of 11 read access request, this is a case where there is a read request from the data processing device to the cache buffer control device.

As is clear from the above-mentioned definition of other data processing devices, it is impossible for the cache buffer control device to be accessed by another data processing device. ,
The first block address D and the second block address E of the access address A are output to the register 13.

In this case, since there is an access request H, the output of the gate 8A supplied from the tag memory control circuit 8 to the switching circuit 1 becomes uO"', and the switching circuit 12 switches to the second block 18-lock held by the register 13. Address E is output.The address of the tag memory 2 specified by this second block address E is accessed, and the contents of all four digits are outputted together with the V bit S to the comparators 31 to 31 of the first comparator circuit 3. 34. In the comparators 31 to 34, among the contents held from the tag memory 2, the contents held in which pip 8 is 1'' are compared with the first block address D from the register 13, and the Check for consistency.

(1,1) In the case of a hit If the above-mentioned -dispersion is detected in any of the comparators 31 to 34, the gate 35 (AND circuit) outputs a hit signal F1 and hit column information F2. The hit column information F2 is 4-bit data in which only 1 bit is 11'' and the remaining 3 bits are 10''. The data is read out by the means.

The hit signal Fl that has passed through 4C (logical sum circuit) is logically ANDed with the access request H and read command U in 4D (logical product circuit), excites the write pulse generator 4E, and writes it to the register 41. The input hit column information F2 is shifted to the right by 1 bit by gates 44 to 47 (NAND circuits), and then transferred to the random access memory 4.
Write in 3. Random access memory 43 at this time
The store address is the second block address E, which is the same as the access address to the tag memory 2 described above.

The right shifting of the gates 44-47 described above is performed as follows. When the write pulse is input from the write pulse generator 4E to the random access memory 43, the random access memory 43 is configured to output 10'', and the register 42 is set to υ'''O by the hit signal F1.
Therefore, all the outputs of the gates 48 to 4B (AND circuits) are "L", and the outputs of the connected gates 44 to 4B are shifted to the right by one bit from the register 41.
The output of the register 41 is input to 47 and written to the random access memory 43. The written contents of the random access memory 43 are outputted to the register 42 and become replacement column information J when an access request H and a read command U are given and a miss signal G is generated.

This shift processing is to specify the column to the right of the hit column as the column in which a new data block is to be loaded from the main memory IO to the cache buffer 9 in the event of a miss, which will be described next. Since the access request H is ``1'' and the miss signal G is wO''j, the output of the tag memory control circuit 8) is 10''. However, the tag memo 1 control circuit 8 does not function.

(1, 2) In the case of a mishit If no coincidence is detected in any of the comparators 31 to 34, the gate 35 outputs a mishit signal G.

21- The data processing device reads data from the address of the main memory 10 designated by the access address person by means not shown. A copy of the data block including this booter is accessed by the second block address E, read from the random access memory 43, and stored in the cache buffer 9 determined by the replacement column information J and the second block address E, which is read from the random access memory 43 and set in the register 42. The location is loaded from main memory lO.

The ξ hit signal G is delayed by l clocks in the flip-flop 4F and activates the write pulse generator 4D to write the random access memory 4 specified by the same second block address that accessed the tag memory 2.
The contents held in the register 42 (replacement column information J) are shifted to the right by 1 bit using gates 48 to 4B and gates 44 to 47 and written to address 3 by °C%. This right 7ft is UOW when the register 41 is cleared by the miss signal G and the random access memory 43 receives the write pulse input 22- from the write pulse generator 4D like the spinning speed. This is done by outputting , and is used to sequentially forward columns to be replaced.

The mishit signal G and replacement column information J are supplied to the gate 8E (AND circuit) of the tag memory control circuit 8 and the switch 82, respectively. The output of 8E becomes the switching signal of the switch 82 via the gate 8B, and the replacement column information J
is input from the switch 82 to the register 85, and
Excite the write pulse generator 8H, supply the replacement column information J input to the register 85 to the tag memory 2 as column designation R via gates 86 to 89 (AND circuit),
The first block address D is written to the location in the random access memory 21 determined by the second block address E and this column designation R.

At this time, since there is an access request H, gate 8D (NOR circuit), therefore gate 8A (AND circuit)
The output V is supplied to the tag memory 2 from the switch 81 as V bit 8, and "1" is written in the column specified by the above-mentioned power specification R. . ■
When bit S is “ul”, the content held in the column (first
Block address D) is valid and ■bit S is 10.
', K indicates that the content held in the column is invalid and cannot be compared in the first comparator circuit 3.

The comparators 1671 to 74 and the comparators 75 to 78 in the second comparison circuit 7 respectively compare the second block address E, the contents held in the registers 54 to 57 of the stack circuit 5, the replacement column information J, and the registers 58 to 5B of the stack circuit 5.
(corresponding level 7 lip-flops 58 to 5F)
The content held in the file is 111). If the results of both comparisons show that both levels match, a match is output via gates 7A to 7D (NAND circuits) in response to a miss signal GK, and bell information Q is output. Clear circuit 6 corresponding to the level specified by this matching level information Q) 61 to 64 (
The gate of the NAND circuit (NAND circuit) outputs a positive signal and resets the flip-flops at the corresponding level among the flip-flops 50 to 5F.

(2) At the time of a write access request This is a case where there is a write request from the data processing device to the Φ Yakuni buffer control device.

The consistency of the first block address D is checked in the same manner as in the case of (1) read access request for spinning speed.

(2,1) When a hit occurs, data is written from the data processing device to the addresses of the cache buffer 9 and main memory 10 specified by the access address A by means not shown.

In this case, the read command U is 0'', so the replacement column designation circuit 4 does not operate, and for the same reason as in the case of (1.1) hit, the stack circuit 5 and tag memory control circuit 8 also operate. do not.

(2, 2) In the case of a miss, data p is simply written to the address of the main memory IO specified by the access address A from the data processing by means not shown.

(3) At the time of invalidation request 25- When another data processing device executes a store access, that is, when writing data to the main memory IO, if the data of the written data block before being rewritten is If a copy is held in the cache memory 9, an invalidation request K is input from another data processing device in order to invalidate it.

In this case, the switch 11 outputs the invalidation request address B to the register 13 in response to the invalidation request K, and outputs the invalidation request address B to the first block address D and the second block address E of the invalidation request address B. The presence or absence of consistency is checked in the same manner as described above between the content held in the tag memory 2 that is accessed and read out by the user.

(3,1) When a hit occurs, the gate 51 of the stack circuit 5 outputs 111' to excite the decoder 53 and registers 54 to 57 and register 58.
The second block address E% hit column information F2 and the output of the gate 51 are stored in each of the flip-flops 5B and 50 to 5F at a level specified by the decoder 53).

At the same time, the output of the gate 51 increments the counter 52 and instructs the decoder 53 about the next storage level.

In this case, the access request H is uO'', so
Writing to the 4D replacement column designation circuit 4 is blocked, and the tag memory control circuit 8 also does not operate for the same reason as described above.

(3, 2) When a mishit occurs, circuits other than the second comparison circuit 7 and clear circuit 6 do not operate.

(4) Case where there is no access request or invalidation request This is a case where the cache control device is not used as a slave.

Flip-flop 5 in gate 8C (OR circuit)
When it is found that any one of 0 to 5F holds alltl, the output () of 8A outputs "1"', and in response to this output, the switch 81 sets uO" to V bit 8. Supplied to tag memory 2.

In response to the output of the counter 8G, the switchers 83 and 84 select the contents held at the same level from among invalidation block M information M and invalidation column information N, which are the contents held in registers 54 to 57 and registers 58 to 5B, respectively. are selected one by one. The output of the switch 83 becomes the invalidation address C and is supplied to the switch 12 of the tag memory 2, and the switch 12 transfers this invalidation address C to the tag memory 2 in response to the output V of the gate 8A. Output.

The output of the switch 84 is output from the switch 82 in response to the output of the gate 8B (in this case, Goo is equal to the output ■ of the gate 8A), and is input to the register 85.

On the other hand, the output of Goo) 8B excites the write pulse generator 8H to output a write pulse to gates 86 to 89, and the gates 86 to 89 logically AND the contents held in the register 85 and the write pulse, and Output the designation R to the tag memory 2.

In this way, the V bit 5KuO of the tag memory 2 location specified by the invalidation address C and the column specification ratio is
” is written in, invalidating the contents held at the same position.

The output (■) of 8A also excites the decoder 8F and outputs the signal from one of the gates 61 to 64 at a level designated by the decoder 8F (equal to the level at which the invalidation was performed).
Output I''. Among flip-flops 50 to 5F, the flip-flops at the same level as this level are u
O'', indicating that the contents stored in registers at the same level have become meaningless.In other words, the position information of the invalidation method is removed from the invalidation queue.

The output V of the gate 8A simultaneously increments the counter 8G to set the next invalidation target level.

The embodiment shown in FIG. 1 described above has only one tag memory, but it has two tag memories that hold the same contents, and each one receives the access request H from the data processing device and other data. A cache buffer control device is known that divides the reference processing for the invalidation request K from the processing device, thereby alleviating the conflict between the two requests and improving the processing performance.

FIG. 4 is a block diagram showing, together with the cache puffer 9 and the main memory 10, a second embodiment in which the present invention is applied to the cache S/& buffer 29-control device having such a configuration.

This embodiment includes a first switching circuit 100 and a second switching circuit 110.
, a first tag memory 200, and a second tag memo') 210
, a first comparison circuit 300 , a third comparison circuit 310 ,
A replacement column designation circuit 400, a stack circuit 500,
It is composed of a clear circuit 600, a second comparison circuit 700, and a tag memory control circuit 800.

The first switching circuit 100 is composed of a switch 12 and a register γ in the switching circuit l shown in FIG.
0 is configured to switch between the invalidation request address B and the invalidation address C in response to the output (2) of the gate 8A. The first tag memory 200 and the second tag memory 210 hold the same contents and handle reference processing for access requests from the data processing device and invalidation requests from other data processing devices, respectively. Further, the first comparison circuit 300 and the third comparison circuit 310 are used to perform hit/miss hit judgment and extraction of hit columns in response to an access request H from the data processing device 30 and an invalidation request K from another data processing device, respectively. It's from.

Other circuits are similar to the detailed circuit diagrams shown in FIGS. 2 and 3 with respect to the first embodiment shown in FIG.

According to the present invention, by employing the above-described configuration, the tag memory location information that is stored in the stack circuit and is waiting to be invalidated is compared with the cache buffer location information that is to be loaded to see if they match. This makes it possible to make the portrait tag memory location information stored in the stack circuit meaningless, so it is possible to avoid invalidating the content held in the portrait buffer loaded from the main memory. This improves the hit rate and ignores unnecessary invalidation requests, making it possible to improve the efficiency of tag memory use.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the invention, FIGS. 2 and 3 show details of this embodiment, and FIG. 4 shows another embodiment of the invention. 1...Switching circuit, 10o...Serious 1 switching circuit, 110...2nd switching circuit, 2...Tag memory, 3,300...・First comparison circuit, 4.
400...Replacement column designation circuit, 5,500.
...Stack circuit, 6,600...Clear circuit, 7,700 Old...Second comparison circuit, 8,80
0...Tag memory control circuit, 9...Charatsuyu buffer, 10...Main memory (main memory), 200...First tag memory, 21
0...Second tag memory, 310...Third comparison circuit, 11, 12, 81, 82, 83°84...
...Switcher, 13.41, 42.54.55.5
6.57゜58.59, 5A, 5B, 85...
Register, 21.43... Random access memory (RAM), 31.32° 33.34, 71, 72
, 73, 74, 75, 76. 77. 78... Comparator, 35, 44, 45, 46, 47, 48, 49
．． 4A. 4B, 4C, 4D, 51, 61, 62, 63.64. 7A. 7B, 7C, 7D, 7E, 86.87, 88, 89.8
A. 8B, 8C, 8D, 8E...Gate, 4E
, 8H...Write pulse generator, 4F, 50.
5D, 5B, 5F...Flip-flop, 52
．． 8G...Counter, 53.8F...
Decoder, A...Access address, B...
... Invalidation request address, C ... Invalidation address, D ... First block address, E ...
...Second block address, Fl...Hit signal, F2...Hit column information, G...
・Poor hit signal, H...Access request, J.
...Replacement column information, K...Invalidation request, L...Clear signal, M...Invalidation block information, N...Invalidation column information, P...
... Significance display, Q ... Matching level information,
R...Column specification, S...V bit,
T: Elimination level information, U: Read command, ■: Output of gate 8A. 33- Measure 1 Figure '5 Figure 4

Claims (1)

[Scope of Claims] A plurality of data processing devices sharing a main storage device are provided, and at least one of the data processing devices has a cache buffer that holds copies of a plurality of data blocks in the main storage device over at least one column per address. In the cache buffer control device in the data processing system, the cache buffer control device includes a cache buffer control device that stores block address information for a data block held by the cache buffer in a position corresponding to a position determined by an address and a column of the cache buffer. a replacement column designation circuit that designates a column of the cache buffer to which a new data block is to be loaded from the main storage device according to a predetermined procedure when a cache buffer misses; , If valid block address information for the data block that is the target of the main storage request from another data processing device is held in the tag memory, position information regarding the holding position of the tag memory and its significance. an addressable stack circuit that stores a display flag over at least one level; a clear circuit that clears the significance display flag stored in a separately notified level of the stack circuit; When this happens, the access address to the cache buffer and the column designated by the replacement column designation circuit are compared with all of the position information stored in the stack circuit together with the significance flag, and if they match, the column designated by the replacement column designation circuit is stored at the relevant level. a comparison circuit that notifies the clearing circuit of information on the level in order to clear the significance display flag that is present in the stack circuit; If there is a significance display flag, the block address information of the tag memory corresponding to the position information with the significance display flag is invalidated according to a predetermined procedure, and the significance display that caused the invalidation is performed. A cache buffer control device comprising: a tag memory control circuit that notifies the clearing circuit of the level information in order to clear the flag.